diff options
Diffstat (limited to 'tests/long/fs')
7 files changed, 5261 insertions, 5386 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 0876dc614..a9e8e7d4a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903548 # Number of seconds simulated -sim_ticks 1903548166500 # Number of ticks simulated -final_tick 1903548166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.902683 # Number of seconds simulated +sim_ticks 1902682770000 # Number of ticks simulated +final_tick 1902682770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123505 # Simulator instruction rate (inst/s) -host_op_rate 123505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4187441182 # Simulator tick rate (ticks/s) -host_mem_usage 303204 # Number of bytes of host memory used -host_seconds 454.59 # Real time elapsed on the host -sim_insts 56143492 # Number of instructions simulated -sim_ops 56143492 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 879488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24796480 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 101696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 559552 # Number of bytes read from this memory -system.physmem.bytes_read::total 28986880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 879488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 101696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7925376 # Number of bytes written to this memory -system.physmem.bytes_written::total 7925376 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387445 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1589 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8743 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452920 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123834 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123834 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 462026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13026453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 293952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15227815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 462026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4163475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4163475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4163475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 462026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13026453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 293952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19391291 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 346033 # number of replacements -system.l2c.tagsinuse 65330.743124 # Cycle average of tags in use -system.l2c.total_refs 2608063 # Total number of references to valid blocks. -system.l2c.sampled_refs 411178 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.342905 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6380526000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53708.225390 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5276.213951 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6113.589929 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 198.792297 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 33.921558 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.819522 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080509 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093286 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003033 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000518 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996868 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 970913 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 780748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 107670 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 39067 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1898398 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 832636 # number of Writeback hits -system.l2c.Writeback_hits::total 832636 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 238 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits +host_inst_rate 192931 # Simulator instruction rate (inst/s) +host_op_rate 192931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6436506827 # Simulator tick rate (ticks/s) +host_mem_usage 296908 # Number of bytes of host memory used +host_seconds 295.61 # Real time elapsed on the host +sim_insts 57032045 # Number of instructions simulated +sim_ops 57032045 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 906816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24518592 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 73984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 789824 # Number of bytes read from this memory +system.physmem.bytes_read::total 28940032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 906816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 73984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7895360 # Number of bytes written to this memory +system.physmem.bytes_written::total 7895360 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 383103 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1156 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12341 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452188 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123365 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 476599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12886327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1393199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 38884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 415111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15210119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 476599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 38884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4149593 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4149593 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4149593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 476599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12886327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1393199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 38884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 415111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19359713 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 345291 # number of replacements +system.l2c.tagsinuse 65280.360301 # Cycle average of tags in use +system.l2c.total_refs 2575351 # Total number of references to valid blocks. +system.l2c.sampled_refs 410382 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.275497 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6143524000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53635.672684 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5378.326569 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6042.958234 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 144.667579 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 78.735234 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.818415 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.082067 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.092208 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002207 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001201 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996099 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 798441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 696934 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 292090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 99595 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1887060 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 812223 # number of Writeback hits +system.l2c.Writeback_hits::total 812223 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 566 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 46 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 168538 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 13567 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 182105 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 970913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 949286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 107670 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 52634 # number of demand (read+write) hits -system.l2c.demand_hits::total 2080503 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 970913 # number of overall hits -system.l2c.overall_hits::cpu0.data 949286 # number of overall hits -system.l2c.overall_hits::cpu1.inst 107670 # number of overall hits -system.l2c.overall_hits::cpu1.data 52634 # number of overall hits -system.l2c.overall_hits::total 2080503 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13744 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272909 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1606 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 887 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289146 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2478 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 531 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 43 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 77 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 120 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114968 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7955 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122923 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13744 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387877 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1606 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8842 # number of demand (read+write) misses -system.l2c.demand_misses::total 412069 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13744 # number of overall misses -system.l2c.overall_misses::cpu0.data 387877 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1606 # number of overall misses -system.l2c.overall_misses::cpu1.data 8842 # number of overall misses -system.l2c.overall_misses::total 412069 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 731783998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14210594000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 85626000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 48439997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15076443995 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2486000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1250500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 3736500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 522000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 678500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6190320497 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 441967499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6632287996 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 731783998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20400914497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 85626000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 490407496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21708731991 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 731783998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20400914497 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 85626000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 490407496 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21708731991 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 984657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1053657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 109276 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 39954 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2187544 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 832636 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832636 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2662 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 585 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3247 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 70 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 106 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 176 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 283506 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 21522 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305028 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 984657 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1337163 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 109276 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61476 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2492572 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 984657 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1337163 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 109276 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61476 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2492572 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013958 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259011 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.022201 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.132178 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.930879 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.907692 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.926702 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.614286 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726415 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.681818 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.405522 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.369622 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.402989 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013958 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290075 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014697 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.143828 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165319 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013958 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290075 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014697 # 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miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119392.034091 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276451.550010 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 276451.550010 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 275789.105732 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 275789.105732 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 201643000 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119367.220339 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119367.220339 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276437.158404 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 276437.158404 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 275770.921997 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 275770.921997 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 200533 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24752 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24673 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8146.533613 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.127629 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11860000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11860000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9326257976 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9326257976 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9338117976 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9338117976 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9338117976 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9338117976 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11923998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11923998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9325812806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9325812806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9337736804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9337736804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9337736804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9337736804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224447.871968 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 224447.871968 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67367.220339 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67367.220339 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224437.158404 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224437.158404 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9377828 # DTB read hits -system.cpu0.dtb.read_misses 33360 # DTB read misses -system.cpu0.dtb.read_acv 521 # DTB read access violations -system.cpu0.dtb.read_accesses 633373 # DTB read accesses -system.cpu0.dtb.write_hits 6221809 # DTB write hits -system.cpu0.dtb.write_misses 7167 # DTB write misses -system.cpu0.dtb.write_acv 341 # DTB write access violations -system.cpu0.dtb.write_accesses 216042 # DTB write accesses -system.cpu0.dtb.data_hits 15599637 # DTB hits -system.cpu0.dtb.data_misses 40527 # DTB misses -system.cpu0.dtb.data_acv 862 # DTB access violations -system.cpu0.dtb.data_accesses 849415 # DTB accesses -system.cpu0.itb.fetch_hits 1073423 # ITB hits -system.cpu0.itb.fetch_misses 26403 # ITB misses -system.cpu0.itb.fetch_acv 1051 # ITB acv -system.cpu0.itb.fetch_accesses 1099826 # ITB accesses +system.cpu0.dtb.read_hits 8304100 # DTB read hits +system.cpu0.dtb.read_misses 28307 # DTB read misses +system.cpu0.dtb.read_acv 549 # DTB read access violations +system.cpu0.dtb.read_accesses 542239 # DTB read accesses +system.cpu0.dtb.write_hits 5411904 # DTB write hits +system.cpu0.dtb.write_misses 5987 # DTB write misses +system.cpu0.dtb.write_acv 347 # DTB write access violations +system.cpu0.dtb.write_accesses 182798 # DTB write accesses +system.cpu0.dtb.data_hits 13716004 # DTB hits +system.cpu0.dtb.data_misses 34294 # DTB misses +system.cpu0.dtb.data_acv 896 # DTB access violations +system.cpu0.dtb.data_accesses 725037 # DTB accesses +system.cpu0.itb.fetch_hits 908718 # ITB hits +system.cpu0.itb.fetch_misses 19910 # ITB misses +system.cpu0.itb.fetch_acv 927 # ITB acv +system.cpu0.itb.fetch_accesses 928628 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,277 +483,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 120667689 # number of cpu cycles simulated +system.cpu0.numCycles 102599658 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13362893 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11185412 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 402804 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9622475 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5627170 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11825647 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9917652 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 342692 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8240217 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5044056 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 884758 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37477 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 30221705 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 67571030 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13362893 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6511928 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12734942 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1928304 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 41309111 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 28714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 205220 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 305503 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8304621 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 277902 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 86063714 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.785128 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.113854 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 768623 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31919 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 23566044 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60418395 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11825647 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5812679 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11434253 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1624928 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 35275815 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31363 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 170412 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 309547 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7444211 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 224420 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 71849758 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.840899 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.174060 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 73328772 85.20% 85.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 837915 0.97% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1666262 1.94% 88.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 768356 0.89% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2658731 3.09% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 585060 0.68% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 622966 0.72% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 967713 1.12% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4627939 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 60415505 84.09% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 744936 1.04% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1526054 2.12% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 669496 0.93% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2482176 3.45% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 513952 0.72% 92.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 559997 0.78% 93.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 746719 1.04% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4190923 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 86063714 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.110741 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.559976 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 31149327 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 41124977 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11584676 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 985581 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1219152 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 571369 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 39493 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 66407813 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 120728 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1219152 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 32233219 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 16872016 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 20344281 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10880828 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4514216 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 62880643 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6942 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 700700 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1661735 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 42005938 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 76144064 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 75702119 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 441945 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36517182 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5488748 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1574453 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 239002 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12018911 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9888186 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6523659 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1201517 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 824194 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55665948 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1995313 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54317533 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 112244 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6696159 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3338542 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1358752 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 86063714 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.631132 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.280124 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 71849758 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.115260 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.588875 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 24832568 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34702410 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10423010 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 862232 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1029537 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 502827 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32976 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 59359454 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 95150 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1029537 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25748676 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14416729 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17004300 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9792924 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3857590 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56337606 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6610 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 598180 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1362975 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 37819724 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 68629747 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 68286150 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 343597 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33121112 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4698612 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1343902 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 201432 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10333121 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8734327 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5677673 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1105299 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 704273 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50005822 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1695696 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 48865145 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 103608 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5731519 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2860845 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1151664 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 71849758 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680102 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.326568 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 61486843 71.44% 71.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 11432526 13.28% 84.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5063556 5.88% 90.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3287093 3.82% 94.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2517985 2.93% 97.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1255115 1.46% 98.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 648079 0.75% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 319509 0.37% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53008 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50068220 69.68% 69.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9955153 13.86% 83.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4454682 6.20% 89.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2911875 4.05% 93.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2358569 3.28% 97.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1157257 1.61% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 610758 0.85% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 286058 0.40% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 47186 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 86063714 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 71849758 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 73354 10.53% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 330176 47.38% 57.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 293358 42.10% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 80509 12.84% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 294043 46.91% 59.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 252280 40.25% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3296 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37287239 68.65% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60152 0.11% 68.76% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.76% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15662 0.03% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1646 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9781142 18.01% 86.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6293081 11.59% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 875315 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2557 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 33918404 69.41% 69.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54116 0.11% 69.53% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 12070 0.02% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8648673 17.70% 87.25% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5478002 11.21% 98.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 750056 1.53% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54317533 # Type of FU issued -system.cpu0.iq.rate 0.450141 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 696889 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012830 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 194880881 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 64065914 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53156794 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 627031 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 303977 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294706 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 54682626 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 328500 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 571695 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 48865145 # Type of FU issued +system.cpu0.iq.rate 0.476270 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 626833 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012828 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 169818867 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57206555 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 47890608 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 491622 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 238128 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 232129 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 49232078 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 257343 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 523556 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1271953 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2828 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12731 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 517788 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1075506 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2442 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11895 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 454594 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18545 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 107284 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 86028 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1219152 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 12163042 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 861940 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61112544 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 659342 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9888186 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6523659 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1757966 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 617572 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 9941 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12731 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 210191 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 389993 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 600184 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 53834482 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9436308 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 483050 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1029537 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10326104 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 769928 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 54791843 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 549393 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8734327 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5677673 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1493453 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 559696 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5669 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11895 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 183351 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 329192 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 512543 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 48451300 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8354077 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 413845 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3451283 # number of nop insts executed -system.cpu0.iew.exec_refs 15679571 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8587439 # Number of branches executed -system.cpu0.iew.exec_stores 6243263 # Number of stores executed -system.cpu0.iew.exec_rate 0.446138 # Inst execution rate -system.cpu0.iew.wb_sent 53546468 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53451500 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26356174 # num instructions producing a value -system.cpu0.iew.wb_consumers 35593959 # num instructions consuming a value +system.cpu0.iew.exec_nop 3090325 # number of nop insts executed +system.cpu0.iew.exec_refs 13784796 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7754310 # Number of branches executed +system.cpu0.iew.exec_stores 5430719 # Number of stores executed +system.cpu0.iew.exec_rate 0.472236 # Inst execution rate +system.cpu0.iew.wb_sent 48208648 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48122737 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24107105 # num instructions producing a value +system.cpu0.iew.wb_consumers 32426814 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.442964 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.740468 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.469034 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743431 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7303960 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 636561 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 562819 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 84844562 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.633202 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.547709 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6216029 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 544032 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 479899 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 70820221 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.684637 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.594318 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 64556270 76.09% 76.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8510919 10.03% 86.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4635841 5.46% 91.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2494817 2.94% 94.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1390539 1.64% 96.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 576056 0.68% 96.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 484846 0.57% 97.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 456978 0.54% 97.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1738296 2.05% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 52470926 74.09% 74.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7676401 10.84% 84.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4235846 5.98% 90.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2227139 3.14% 94.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1283042 1.81% 95.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 528527 0.75% 96.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 441494 0.62% 97.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 421867 0.60% 97.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1534979 2.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 84844562 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53723778 # Number of instructions committed -system.cpu0.commit.committedOps 53723778 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 70820221 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48486178 # Number of instructions committed +system.cpu0.commit.committedOps 48486178 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14622104 # Number of memory references committed -system.cpu0.commit.loads 8616233 # Number of loads committed -system.cpu0.commit.membars 216543 # Number of memory barriers committed -system.cpu0.commit.branches 8113778 # Number of branches committed -system.cpu0.commit.fp_insts 292474 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49705714 # Number of committed integer instructions. -system.cpu0.commit.function_calls 703203 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1738296 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12881900 # Number of memory references committed +system.cpu0.commit.loads 7658821 # Number of loads committed +system.cpu0.commit.membars 183715 # Number of memory barriers committed +system.cpu0.commit.branches 7346956 # Number of branches committed +system.cpu0.commit.fp_insts 229898 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 44900899 # Number of committed integer instructions. +system.cpu0.commit.function_calls 613493 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1534979 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 143945633 # The number of ROB reads -system.cpu0.rob.rob_writes 123274808 # The number of ROB writes -system.cpu0.timesIdled 1363780 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 34603975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3686422279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50608732 # Number of Instructions Simulated -system.cpu0.committedOps 50608732 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 50608732 # Number of Instructions Simulated -system.cpu0.cpi 2.384325 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.384325 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.419406 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.419406 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 70600527 # number of integer regfile reads -system.cpu0.int_regfile_writes 38607300 # number of integer regfile writes -system.cpu0.fp_regfile_reads 144193 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146198 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1863622 # number of misc regfile reads -system.cpu0.misc_regfile_writes 886886 # number of misc regfile writes +system.cpu0.rob.rob_reads 123809295 # The number of ROB reads +system.cpu0.rob.rob_writes 110434143 # The number of ROB writes +system.cpu0.timesIdled 1033297 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 30749900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3702120338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 45684021 # Number of Instructions Simulated +system.cpu0.committedOps 45684021 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 45684021 # Number of Instructions Simulated +system.cpu0.cpi 2.245854 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.245854 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.445265 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.445265 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 63838240 # number of integer regfile reads +system.cpu0.int_regfile_writes 34928793 # number of integer regfile writes +system.cpu0.fp_regfile_reads 112215 # number of floating regfile reads +system.cpu0.fp_regfile_writes 113746 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1561574 # number of misc regfile reads +system.cpu0.misc_regfile_writes 757779 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -785,245 +785,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 984085 # number of replacements -system.cpu0.icache.tagsinuse 509.993322 # Cycle average of tags in use -system.cpu0.icache.total_refs 7264923 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984594 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.378598 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23948219000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.993322 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996081 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996081 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7264923 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7264923 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7264923 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7264923 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7264923 # number of overall hits -system.cpu0.icache.overall_hits::total 7264923 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1039697 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1039697 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1039697 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1039697 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1039697 # number of overall misses -system.cpu0.icache.overall_misses::total 1039697 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16868456488 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 16868456488 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 16868456488 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 16868456488 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 16868456488 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 16868456488 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8304620 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8304620 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8304620 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8304620 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8304620 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8304620 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125195 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125195 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125195 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125195 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125195 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125195 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16224.396616 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16224.396616 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16224.396616 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16224.396616 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1612994 # number of cycles access was blocked +system.cpu0.icache.replacements 812060 # number of replacements +system.cpu0.icache.tagsinuse 510.054551 # Cycle average of tags in use +system.cpu0.icache.total_refs 6590229 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 812572 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.110332 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23200943000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.054551 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996200 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996200 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6590229 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6590229 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6590229 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6590229 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6590229 # number of overall hits +system.cpu0.icache.overall_hits::total 6590229 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 853981 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 853981 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 853981 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 853981 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 853981 # number of overall misses +system.cpu0.icache.overall_misses::total 853981 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11857055495 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11857055495 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11857055495 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11857055495 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11857055495 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11857055495 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7444210 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7444210 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7444210 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7444210 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7444210 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7444210 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114717 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.114717 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114717 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.114717 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114717 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.114717 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13884.448828 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13884.448828 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13884.448828 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13884.448828 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2511 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 9432.713450 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.771654 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54925 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54925 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54925 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54925 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54925 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54925 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 984772 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 984772 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 984772 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13041683494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13041683494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13041683494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13041683494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13041683494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13041683494 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118581 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.118581 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.118581 # 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number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 41272 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 812709 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 812709 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 812709 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 812709 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 812709 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 812709 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9799988995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9799988995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9799988995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9799988995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9799988995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9799988995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109173 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.109173 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.109173 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12058.423119 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1341345 # number of replacements -system.cpu0.dcache.tagsinuse 506.494858 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11161433 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1341857 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.317900 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 23750000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.494858 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989248 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989248 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6822568 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6822568 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3942957 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3942957 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181355 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 181355 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208341 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208341 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10765525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10765525 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10765525 # number of overall hits -system.cpu0.dcache.overall_hits::total 10765525 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1719034 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1719034 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1839372 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1839372 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22429 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22429 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 711 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 711 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3558406 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3558406 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3558406 # 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number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14323931 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14323931 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14323931 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.201254 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.201254 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318102 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.318102 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003401 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003401 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248424 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248424 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248424 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248424 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27033.131398 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27033.131398 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38860.689686 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38860.689686 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18126.443444 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18126.443444 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9488.748242 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9488.748242 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33146.902436 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33146.902436 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 754476476 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 245500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 70452 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10709.085278 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 27277.777778 # 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number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19429 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19429 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4062 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4062 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3105177 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3105177 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3105177 # number of overall misses +system.cpu0.dcache.overall_misses::total 3105177 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34499425000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34499425000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55944257946 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 55944257946 # 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number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5030078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 171416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 171416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178505 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 178505 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12585701 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12585701 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12585701 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12585701 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197528 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197528 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320617 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.320617 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113344 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113344 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.022756 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.022756 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.246723 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.246723 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.246723 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.246723 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23116.028989 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23116.028989 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34689.144033 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34689.144033 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13635.827886 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13635.827886 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11721.935007 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11721.935007 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 29126.739940 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 29126.739940 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1403245 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 435 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 52795 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.579127 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 62.142857 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 796119 # number of writebacks -system.cpu0.dcache.writebacks::total 796119 # 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number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 286627 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 286627 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17372 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17372 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 711 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 711 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330614 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1330614 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330614 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1330614 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27461612037 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27461612037 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9493856805 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9493856805 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 250184001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 250184001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4525001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4525001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36955468842 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 36955468842 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36955468842 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 36955468842 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1456541500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1456541500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2062903998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2062903998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3519445498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3519445498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049569 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049569 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085247 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085247 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003401 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003401 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092894 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092894 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26304.553636 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26304.553636 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33122.688389 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33122.688389 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14401.565796 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14401.565796 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6364.277075 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6364.277075 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 710192 # number of writebacks +system.cpu0.dcache.writebacks::total 710192 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 524907 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 524907 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1358576 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1358576 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4179 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4179 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1883483 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1883483 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1883483 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1883483 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 967539 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 967539 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254155 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 254155 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15250 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15250 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4062 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4062 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1221694 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1221694 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1221694 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1221694 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23357450000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23357450000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8081474275 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8081474275 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 163906000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 163906000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 39490500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 39490500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31438924275 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31438924275 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31438924275 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31438924275 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451861000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451861000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167064498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167064498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3618925498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3618925498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128055 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128055 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050527 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050527 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.022756 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.022756 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097070 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097070 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24141.094054 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24141.094054 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31797.423915 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31797.423915 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10747.934426 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10747.934426 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9721.935007 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9721.935007 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1035,22 +1035,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1298594 # DTB read hits -system.cpu1.dtb.read_misses 11503 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 332098 # DTB read accesses -system.cpu1.dtb.write_hits 765153 # DTB write hits -system.cpu1.dtb.write_misses 2957 # DTB write misses -system.cpu1.dtb.write_acv 47 # DTB write access violations -system.cpu1.dtb.write_accesses 125840 # DTB write accesses -system.cpu1.dtb.data_hits 2063747 # DTB hits -system.cpu1.dtb.data_misses 14460 # DTB misses -system.cpu1.dtb.data_acv 53 # DTB access violations -system.cpu1.dtb.data_accesses 457938 # DTB accesses -system.cpu1.itb.fetch_hits 372513 # ITB hits -system.cpu1.itb.fetch_misses 8563 # ITB misses -system.cpu1.itb.fetch_acv 155 # ITB acv -system.cpu1.itb.fetch_accesses 381076 # ITB accesses +system.cpu1.dtb.read_hits 2472786 # DTB read hits +system.cpu1.dtb.read_misses 14686 # DTB read misses +system.cpu1.dtb.read_acv 33 # DTB read access violations +system.cpu1.dtb.read_accesses 413814 # DTB read accesses +system.cpu1.dtb.write_hits 1645990 # DTB write hits +system.cpu1.dtb.write_misses 3399 # DTB write misses +system.cpu1.dtb.write_acv 61 # DTB write access violations +system.cpu1.dtb.write_accesses 158815 # DTB write accesses +system.cpu1.dtb.data_hits 4118776 # DTB hits +system.cpu1.dtb.data_misses 18085 # DTB misses +system.cpu1.dtb.data_acv 94 # DTB access violations +system.cpu1.dtb.data_accesses 572629 # DTB accesses +system.cpu1.itb.fetch_hits 546471 # ITB hits +system.cpu1.itb.fetch_misses 10636 # ITB misses +system.cpu1.itb.fetch_acv 251 # ITB acv +system.cpu1.itb.fetch_accesses 557107 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1063,516 +1063,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 10640951 # number of cpu cycles simulated +system.cpu1.numCycles 20144234 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1701905 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1402674 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 62577 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 862370 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 552113 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3332472 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2756183 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 108633 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2168857 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1160511 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 115027 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5500 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3435420 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8139615 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1701905 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 667140 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1472350 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 326710 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 4537469 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24627 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 73138 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47601 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1039363 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 39149 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9806707 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.830005 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.196976 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 228547 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 10150 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 7838813 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 15883595 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3332472 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1389058 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2861385 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 534677 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 7961253 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 27792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 84864 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 61219 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1925840 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 71197 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 19177134 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.828257 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199800 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 8334357 84.99% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 78230 0.80% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 173812 1.77% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 130927 1.34% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 215769 2.20% 91.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 90418 0.92% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 98526 1.00% 93.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 62686 0.64% 93.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 621982 6.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 16315749 85.08% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 188313 0.98% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 313367 1.63% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 233008 1.22% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 393584 2.05% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151826 0.79% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 167771 0.87% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 278696 1.45% 94.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1134820 5.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9806707 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.159939 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.764933 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3510066 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4639401 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1367694 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 78184 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 211361 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 75357 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4832 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 7943726 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 14591 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 211361 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3646380 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 524692 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3638231 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1300485 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 485556 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7343826 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 139 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 57550 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 136110 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 4921664 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 8958013 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 8905584 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52429 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3978815 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 942849 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 306458 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22346 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1365387 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1395502 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 827989 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 138090 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 96967 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6484639 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 311488 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6173957 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 24546 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1207593 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 679802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236614 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9806707 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.629565 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.304884 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 19177134 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.165431 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.788493 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7716271 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8310209 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2661595 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 156637 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 332421 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 147192 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 9531 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 15577857 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 28018 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 332421 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7986115 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 672083 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6791538 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2542197 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 852778 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 14454091 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 131 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 86206 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 218054 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 9478411 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 17286766 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 17086477 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 200289 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 8045295 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1433108 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 570111 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 60569 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2590157 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2624799 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1738404 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 257229 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 149585 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12667252 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 630653 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 12308685 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 34992 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1859186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 963032 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 447479 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 19177134 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.641842 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.313805 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 7075152 72.15% 72.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1257607 12.82% 84.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 548751 5.60% 90.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 366543 3.74% 94.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 274418 2.80% 97.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 146525 1.49% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 78833 0.80% 99.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 55100 0.56% 99.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 3778 0.04% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 13743416 71.67% 71.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2506419 13.07% 84.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1066336 5.56% 90.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 706714 3.69% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 606260 3.16% 97.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 273557 1.43% 98.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 174545 0.91% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 89739 0.47% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10148 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9806707 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 19177134 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2937 2.09% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 77829 55.26% 57.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60078 42.66% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4629 1.86% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 131937 52.95% 54.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 112626 45.20% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3992 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3816770 61.82% 61.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10118 0.16% 62.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.05% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10095 0.16% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1996 0.03% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1354962 21.95% 84.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 784960 12.71% 96.91% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 191064 3.09% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7659302 62.23% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 19564 0.16% 62.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14781 0.12% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2596890 21.10% 83.66% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1675725 13.61% 97.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 335297 2.72% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6173957 # Type of FU issued -system.cpu1.iq.rate 0.580207 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 140844 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.022813 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 22242262 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 7966601 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 5994284 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 77749 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 38725 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37333 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6270612 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40197 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 68178 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 12308685 # Type of FU issued +system.cpu1.iq.rate 0.611028 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 249192 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020245 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 43789272 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15018387 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 11932725 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 289415 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 141077 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 136872 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12402102 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 151024 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 115183 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 253497 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 450 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1694 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 109535 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 382493 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2469 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 155910 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 346 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8387 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 398 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 20099 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 211361 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 294243 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 17071 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7057887 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 102198 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1395502 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 827989 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 289869 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6102 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1694 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 30581 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 71547 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 102128 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6103512 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1313696 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 70445 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 332421 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 409059 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 59053 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13963733 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 192284 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2624799 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1738404 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 567278 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49311 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2791 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2469 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 54746 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 126604 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 181350 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 12183266 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2497630 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 125418 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 261760 # number of nop insts executed -system.cpu1.iew.exec_refs 2085126 # number of memory reference insts executed -system.cpu1.iew.exec_branches 894247 # Number of branches executed -system.cpu1.iew.exec_stores 771430 # Number of stores executed -system.cpu1.iew.exec_rate 0.573587 # Inst execution rate -system.cpu1.iew.wb_sent 6061366 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6031617 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2917806 # num instructions producing a value -system.cpu1.iew.wb_consumers 4086073 # num instructions consuming a value +system.cpu1.iew.exec_nop 665828 # number of nop insts executed +system.cpu1.iew.exec_refs 4154589 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1827055 # Number of branches executed +system.cpu1.iew.exec_stores 1656959 # Number of stores executed +system.cpu1.iew.exec_rate 0.604802 # Inst execution rate +system.cpu1.iew.wb_sent 12107744 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 12069597 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5640555 # num instructions producing a value +system.cpu1.iew.wb_consumers 7931807 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.566831 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.714086 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.599159 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.711131 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1232464 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 74874 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 96289 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9595346 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.599743 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.518608 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1943114 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 183174 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170211 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 18844713 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633421 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.575988 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 7360615 76.71% 76.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1091727 11.38% 88.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 382276 3.98% 92.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 236221 2.46% 94.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 149500 1.56% 96.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 68368 0.71% 96.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 77096 0.80% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 48958 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 180585 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 14387001 76.35% 76.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2066578 10.97% 87.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 777942 4.13% 91.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 478446 2.54% 93.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 347277 1.84% 95.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 135394 0.72% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 132721 0.70% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 138400 0.73% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 380954 2.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9595346 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5754744 # Number of instructions committed -system.cpu1.commit.committedOps 5754744 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 18844713 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 11936636 # Number of instructions committed +system.cpu1.commit.committedOps 11936636 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1860459 # Number of memory references committed -system.cpu1.commit.loads 1142005 # Number of loads committed -system.cpu1.commit.membars 20259 # Number of memory barriers committed -system.cpu1.commit.branches 814036 # Number of branches committed -system.cpu1.commit.fp_insts 36051 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5384897 # Number of committed integer instructions. -system.cpu1.commit.function_calls 87726 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 180585 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3824800 # Number of memory references committed +system.cpu1.commit.loads 2242306 # Number of loads committed +system.cpu1.commit.membars 59908 # Number of memory barriers committed +system.cpu1.commit.branches 1711003 # Number of branches committed +system.cpu1.commit.fp_insts 135276 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 11053668 # Number of committed integer instructions. +system.cpu1.commit.function_calls 186526 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 380954 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 16310969 # The number of ROB reads -system.cpu1.rob.rob_writes 14184459 # The number of ROB writes -system.cpu1.timesIdled 82580 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 834244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3796004491 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5534760 # Number of Instructions Simulated -system.cpu1.committedOps 5534760 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5534760 # Number of Instructions Simulated -system.cpu1.cpi 1.922568 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.922568 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.520138 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.520138 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 7951221 # number of integer regfile reads -system.cpu1.int_regfile_writes 4345022 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24272 # number of floating regfile reads -system.cpu1.fp_regfile_writes 22982 # number of floating regfile writes -system.cpu1.misc_regfile_reads 283160 # number of misc regfile reads -system.cpu1.misc_regfile_writes 134137 # number of misc regfile writes -system.cpu1.icache.replacements 108736 # number of replacements -system.cpu1.icache.tagsinuse 452.848051 # Cycle average of tags in use -system.cpu1.icache.total_refs 924017 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 109246 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.458131 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1880838222000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 452.848051 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.884469 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.884469 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 924017 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 924017 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 924017 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 924017 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 924017 # number of overall hits -system.cpu1.icache.overall_hits::total 924017 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 115346 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 115346 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 115346 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 115346 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 115346 # number of overall misses -system.cpu1.icache.overall_misses::total 115346 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1915256999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1915256999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1915256999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1915256999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1915256999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1915256999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1039363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1039363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1039363 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1039363 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1039363 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1039363 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110978 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.110978 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110978 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.110978 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110978 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.110978 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16604.450948 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 16604.450948 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 16604.450948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 16604.450948 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 222999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 32234171 # The number of ROB reads +system.cpu1.rob.rob_writes 28090700 # The number of ROB writes +system.cpu1.timesIdled 170938 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 967100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3785218747 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11348024 # Number of Instructions Simulated +system.cpu1.committedOps 11348024 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 11348024 # Number of Instructions Simulated +system.cpu1.cpi 1.775131 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.775131 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.563339 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.563339 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 15713233 # number of integer regfile reads +system.cpu1.int_regfile_writes 8535659 # number of integer regfile writes +system.cpu1.fp_regfile_reads 74431 # number of floating regfile reads +system.cpu1.fp_regfile_writes 74222 # number of floating regfile writes +system.cpu1.misc_regfile_reads 667576 # number of misc regfile reads +system.cpu1.misc_regfile_writes 284444 # number of misc regfile writes +system.cpu1.icache.replacements 292722 # number of replacements +system.cpu1.icache.tagsinuse 471.494279 # Cycle average of tags in use +system.cpu1.icache.total_refs 1621349 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 293230 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.529274 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1876700215000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 471.494279 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.920887 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.920887 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1621349 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1621349 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1621349 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1621349 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1621349 # number of overall hits +system.cpu1.icache.overall_hits::total 1621349 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 304491 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 304491 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 304491 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 304491 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 304491 # number of overall misses +system.cpu1.icache.overall_misses::total 304491 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4065162500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4065162500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4065162500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4065162500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4065162500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4065162500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1925840 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1925840 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1925840 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1925840 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1925840 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1925840 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158108 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.158108 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158108 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.158108 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158108 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.158108 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13350.681958 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13350.681958 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13350.681958 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13350.681958 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7433.300000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.826087 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6038 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6038 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6038 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6038 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6038 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6038 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 109308 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 109308 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 109308 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 109308 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 109308 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 109308 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1491398999 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1491398999 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1491398999 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1491398999 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1491398999 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1491398999 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105168 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.105168 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.105168 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13644.005919 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11170 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 11170 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 11170 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 11170 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 11170 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 11170 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 293321 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 293321 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 293321 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 293321 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 293321 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 293321 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3385018500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3385018500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3385018500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3385018500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3385018500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3385018500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.152308 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.152308 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11540.321013 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # 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number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 541491 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16674 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16674 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14757 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 14757 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1641949 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1641949 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1641949 # number of overall hits -system.cpu1.dcache.overall_hits::total 1641949 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 110209 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 110209 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 156496 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 156496 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1520 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1520 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 666 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 666 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 266705 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 266705 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 266705 # number of overall misses -system.cpu1.dcache.overall_misses::total 266705 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2207117500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2207117500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6428377585 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6428377585 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 25057000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 25057000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8004500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 8004500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8635495085 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8635495085 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8635495085 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8635495085 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1210667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1210667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 697987 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 697987 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18194 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18194 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15423 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15423 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1908654 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1908654 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1908654 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1908654 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.091032 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.091032 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224210 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.224210 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083544 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083544 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.043182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.139735 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.139735 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.139735 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.139735 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20026.653903 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20026.653903 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41076.945002 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41076.945002 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16484.868421 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16484.868421 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12018.768769 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12018.768769 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32378.452166 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32378.452166 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 48117991 # number of cycles access was blocked +system.cpu1.dcache.replacements 154238 # number of replacements +system.cpu1.dcache.tagsinuse 492.768701 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3312022 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 154750 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 21.402404 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 38606824000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 492.768701 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.962439 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.962439 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2009764 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2009764 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1195197 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1195197 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47136 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47136 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 45762 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 45762 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3204961 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3204961 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3204961 # number of overall hits +system.cpu1.dcache.overall_hits::total 3204961 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 288765 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 288765 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 330549 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 330549 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7490 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7490 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4284 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 4284 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 619314 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 619314 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 619314 # number of overall misses +system.cpu1.dcache.overall_misses::total 619314 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4275169500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4275169500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8473061608 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8473061608 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77853000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77853000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49370500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49370500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12748231108 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12748231108 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12748231108 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12748231108 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2298529 # 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number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125630 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.125630 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.216647 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.216647 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137114 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137114 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085601 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085601 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.161943 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.161943 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.161943 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.161943 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14805.012727 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14805.012727 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25633.299777 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25633.299777 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10394.259012 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10394.259012 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11524.393091 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11524.393091 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20584.438763 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20584.438763 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20584.438763 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20584.438763 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 148655 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 4997 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7912 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9629.375825 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.788549 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 36517 # number of writebacks -system.cpu1.dcache.writebacks::total 36517 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66699 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 66699 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 133155 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 133155 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 347 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 347 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 199854 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 199854 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 199854 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 199854 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43510 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 43510 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23341 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 23341 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1173 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1173 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 665 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 665 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 66851 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 66851 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 66851 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 66851 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 664874003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 664874003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 774412476 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 774412476 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13964500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13964500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5940500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5940500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1439286479 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1439286479 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1439286479 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1439286479 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25429000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25429000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 545455000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 545455000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 570884000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 570884000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035939 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035939 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064472 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064472 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043117 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043117 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.035025 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035025 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15280.946978 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15280.946978 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33178.204704 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33178.204704 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11904.944587 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.944587 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8933.082707 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8933.082707 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 102031 # number of writebacks +system.cpu1.dcache.writebacks::total 102031 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180109 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 180109 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 273076 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 273076 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 765 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 453185 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 453185 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 453185 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 453185 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 108656 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 108656 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57473 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57473 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6725 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6725 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4282 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 4282 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 166129 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 166129 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 166129 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 166129 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1328748500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1328748500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1211037987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1211037987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54734500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54734500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 40806500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 40806500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539786487 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2539786487 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539786487 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2539786487 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 686558000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 686558000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047272 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047272 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123110 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123110 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085561 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085561 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043441 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043441 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12228.947320 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12228.947320 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21071.424617 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21071.424617 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8138.959108 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8138.959108 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9529.775806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9529.775806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1581,162 +1581,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199157 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71465 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.10% 41.78% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 9 0.01% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102444 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 175976 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70100 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.35% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 9 0.01% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70091 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142258 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862744375000 97.86% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 69542000 0.00% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 583001500 0.03% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5982500 0.00% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40144359500 2.11% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903547260500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980900 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6652 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 169834 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 59752 40.24% 40.24% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.32% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.30% 41.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 283 0.19% 41.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 86412 58.19% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 148505 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 58939 49.14% 49.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.61% 50.86% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 283 0.24% 51.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 58656 48.91% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 119936 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864736682500 98.02% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62604500 0.00% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 575436000 0.03% 98.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 137989000 0.01% 98.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36850597000 1.94% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1902363309000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.986394 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684188 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808394 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.65% 3.65% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.68% 12.33% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.37% 13.70% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.61% 28.31% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.46% 28.77% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.65% 32.42% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.57% 36.99% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.74% 39.73% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.46% 40.18% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.37% 41.55% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.74% 44.29% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.91% 45.21% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.44% 61.64% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.37% 63.01% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.57% 67.58% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.57% 72.15% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.46% 72.60% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.74% 75.34% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.50% 85.84% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.37% 87.21% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.74% 89.95% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.46% 90.41% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.37% 91.78% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.11% 95.89% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.91% 96.80% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.91% 97.72% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.46% 98.17% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.91% 99.09% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.91% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 219 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.678795 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.807623 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed +system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed +system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed +system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed +system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed +system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed +system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed +system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed +system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 178 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 101 0.05% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3850 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169235 91.57% 93.74% # number of callpals executed -system.cpu0.kern.callpal::rdps 6384 3.45% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4673 2.53% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 133 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184824 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7179 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1251 # number of protection mode switches +system.cpu0.kern.callpal::wripir 383 0.25% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3188 2.04% 2.29% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.32% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed +system.cpu0.kern.callpal::swpipl 141921 90.80% 93.12% # number of callpals executed +system.cpu0.kern.callpal::rdps 6055 3.87% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 97.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4242 2.71% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 315 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 156308 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6637 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1250 -system.cpu0.kern.mode_good::user 1251 +system.cpu0.kern.mode_good::kernel 1098 +system.cpu0.kern.mode_good::user 1098 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.174119 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.165436 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.296679 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901642531000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1904721500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.283904 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1900423407500 99.92% 99.92% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1609733000 0.08% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3851 # number of times the context was actually changed +system.cpu0.kern.swap_context 3189 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2262 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38430 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10197 33.29% 33.29% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1926 6.29% 39.58% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 101 0.33% 39.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18406 60.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30630 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10185 45.68% 45.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1926 8.64% 54.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 101 0.45% 54.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10084 45.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22296 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876291886000 98.58% 98.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533607500 0.03% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 52904000 0.00% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 26445439500 1.39% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903323837000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998823 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2560 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 70963 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 22970 38.17% 38.17% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.20% 41.37% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 383 0.64% 42.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 34900 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 60178 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 22406 47.94% 47.94% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 4.12% 52.06% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 383 0.82% 52.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22023 47.12% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 46737 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874192202500 98.50% 98.50% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532510000 0.03% 98.53% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 178162000 0.01% 98.54% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 27779026000 1.46% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1902681900500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.975446 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.547865 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.727914 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.28% 10.28% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.93% 11.21% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.35% 20.56% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.93% 21.50% # number of syscalls executed -system.cpu1.kern.syscall::17 7 6.54% 28.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.80% 30.84% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.80% 33.64% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.67% 38.32% # number of syscalls executed -system.cpu1.kern.syscall::45 18 16.82% 55.14% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.80% 57.94% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.93% 58.88% # number of syscalls executed -system.cpu1.kern.syscall::71 31 28.97% 87.85% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.35% 97.20% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.80% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 107 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.631032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.776646 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed +system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed +system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed +system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed +system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed +system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed +system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed +system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed +system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 148 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 9 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.04% # number of callpals executed -system.cpu1.kern.callpal::swpctx 385 1.22% 1.26% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.27% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.29% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26077 82.56% 83.85% # number of callpals executed -system.cpu1.kern.callpal::rdps 2376 7.52% 91.38% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.38% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.39% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.40% # number of callpals executed -system.cpu1.kern.callpal::rti 2525 7.99% 99.40% # number of callpals executed -system.cpu1.kern.callpal::callsys 142 0.45% 99.85% # number of callpals executed -system.cpu1.kern.callpal::imb 47 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 283 0.45% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1593 2.54% 3.00% # number of callpals executed +system.cpu1.kern.callpal::tbi 5 0.01% 3.00% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.01% # number of callpals executed +system.cpu1.kern.callpal::swpipl 54358 86.66% 89.67% # number of callpals executed +system.cpu1.kern.callpal::rdps 2709 4.32% 93.99% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.99% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 94.00% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 94.00% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.01% # number of callpals executed +system.cpu1.kern.callpal::rti 3511 5.60% 99.60% # number of callpals executed +system.cpu1.kern.callpal::callsys 200 0.32% 99.92% # number of callpals executed +system.cpu1.kern.callpal::imb 48 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31584 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 861 # number of protection mode switches -system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 514 -system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 26 -system.cpu1.kern.mode_switch_good::kernel 0.596980 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 62728 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1948 # number of protection mode switches +system.cpu1.kern.mode_switch::user 639 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2607 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 948 +system.cpu1.kern.mode_good::user 639 +system.cpu1.kern.mode_good::idle 309 +system.cpu1.kern.mode_switch_good::kernel 0.486653 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.012677 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.302353 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2103355500 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 871184500 0.05% 0.16% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1899849485000 99.84% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 386 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.118527 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.365037 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6500961500 0.34% 0.34% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1047066000 0.06% 0.40% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1895133865000 99.60% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1594 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 05077073e..76f868d7e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.855236 # Nu sim_ticks 1855236450500 # Number of ticks simulated final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87142 # Simulator instruction rate (inst/s) -host_op_rate 87142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3050446700 # Simulator tick rate (ticks/s) -host_mem_usage 299400 # Number of bytes of host memory used -host_seconds 608.19 # Real time elapsed on the host +host_inst_rate 182093 # Simulator instruction rate (inst/s) +host_op_rate 182093 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6374280472 # Simulator tick rate (ticks/s) +host_mem_usage 298212 # Number of bytes of host memory used +host_seconds 291.05 # Real time elapsed on the host sim_insts 52998368 # Number of instructions simulated sim_ops 52998368 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory @@ -87,11 +87,11 @@ system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -105,14 +105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -121,14 +121,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -258,12 +258,12 @@ system.cpu.iq.iqSquashedOperandsExamined 3652702 # Nu system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle @@ -521,11 +521,11 @@ system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -541,24 +541,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1021072 system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930954998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11930954998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930954998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11930954998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930955996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11930955996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930955996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11930955996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930955996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11930955996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.735255 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.735255 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1402622 # number of replacements system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use @@ -595,16 +595,16 @@ system.cpu.dcache.overall_misses::cpu.data 3739889 # system.cpu.dcache.overall_misses::total 3739889 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417909184 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56417909184 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91795917177 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91795917177 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91795917177 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91795917177 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91795913684 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91795913684 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91795913684 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91795913684 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses) @@ -631,22 +631,22 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.254608 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.254608 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24545.090425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24545.090425 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1615102 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 442 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7343.815084 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24555.555556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.681144 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49.111111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks @@ -675,16 +675,16 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1385390 system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402021809 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402021809 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402034783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402034783 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065688309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32065688309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065688309 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32065688309 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065701283 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32065701283 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065701283 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32065701283 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles @@ -705,16 +705,16 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.470406 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.470406 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,19 +765,19 @@ system.cpu.l2cache.demand_misses::total 404416 # nu system.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses system.cpu.l2cache.overall_misses::total 404416 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808284498 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808283500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15073473498 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15073472500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187378482 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6187378482 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 808284498 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20452567482 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21260851980 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 808284498 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20452567482 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21260851980 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187369500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6187369500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 808283500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20452558500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21260842000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 808283500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20452558500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21260842000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses) @@ -808,19 +808,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.166826 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.590720 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.524850 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.851444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.847991 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.091888 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.091888 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52571.737963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52571.737963 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.014041 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.014041 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52571.713285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52571.713285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,25 +850,25 @@ system.cpu.l2cache.demand_mshr_misses::total 404415 system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986768000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609687500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777818000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16400737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777818000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16400737500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses @@ -882,19 +882,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.798680 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.529821 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40167.064542 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.094297 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.094297 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index a59fc99d0..156205699 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534231 # Number of seconds simulated -sim_ticks 2534231333000 # Number of ticks simulated -final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534230 # Number of seconds simulated +sim_ticks 2534229746000 # Number of ticks simulated +final_tick 2534229746000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44913 # Simulator instruction rate (inst/s) -host_op_rate 57771 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1878262368 # Simulator tick rate (ticks/s) -host_mem_usage 387000 # Number of bytes of host memory used -host_seconds 1349.24 # Real time elapsed on the host -sim_insts 60598653 # Number of instructions simulated -sim_ops 77947265 # Number of ops (including micro ops) simulated +host_inst_rate 65745 # Simulator instruction rate (inst/s) +host_op_rate 84567 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2749446134 # Simulator tick rate (ticks/s) +host_mem_usage 380664 # Number of bytes of host memory used +host_seconds 921.72 # Real time elapsed on the host +sim_insts 60598794 # Number of instructions simulated +sim_ops 77947430 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory -system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095568 # Number of bytes read from this memory +system.physmem.bytes_read::total 129434640 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784256 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 142152 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47169229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1313 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51074548 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47169229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1313 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4779219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53758065 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -69,9 +69,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15049411 # DTB read hits +system.cpu.checker.dtb.read_hits 15049421 # DTB read hits system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11294478 # DTB write hits +system.cpu.checker.dtb.write_hits 11294481 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -82,13 +82,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056713 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296667 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056723 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296670 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26343889 # DTB hits +system.cpu.checker.dtb.hits 26343902 # DTB hits system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26353380 # DTB accesses -system.cpu.checker.itb.inst_hits 61777417 # ITB inst hits +system.cpu.checker.dtb.accesses 26353393 # DTB accesses +system.cpu.checker.itb.inst_hits 61777557 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -105,36 +105,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61781888 # ITB inst accesses -system.cpu.checker.itb.hits 61777417 # DTB hits +system.cpu.checker.itb.inst_accesses 61782028 # ITB inst accesses +system.cpu.checker.itb.hits 61777557 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61781888 # DTB accesses -system.cpu.checker.numCycles 78237836 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61782028 # DTB accesses +system.cpu.checker.numCycles 78238000 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51729232 # DTB read hits -system.cpu.dtb.read_misses 76957 # DTB read misses -system.cpu.dtb.write_hits 11808980 # DTB write hits -system.cpu.dtb.write_misses 17307 # DTB write misses +system.cpu.dtb.read_hits 51729015 # DTB read hits +system.cpu.dtb.read_misses 77642 # DTB read misses +system.cpu.dtb.write_hits 11810988 # DTB write hits +system.cpu.dtb.write_misses 17459 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7736 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7775 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2642 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51806189 # DTB read accesses -system.cpu.dtb.write_accesses 11826287 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51806657 # DTB read accesses +system.cpu.dtb.write_accesses 11828447 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63538212 # DTB hits -system.cpu.dtb.misses 94264 # DTB misses -system.cpu.dtb.accesses 63632476 # DTB accesses -system.cpu.itb.inst_hits 13079160 # ITB inst hits -system.cpu.itb.inst_misses 12175 # ITB inst misses +system.cpu.dtb.hits 63540003 # DTB hits +system.cpu.dtb.misses 95101 # DTB misses +system.cpu.dtb.accesses 63635104 # DTB accesses +system.cpu.itb.inst_hits 13083995 # ITB inst hits +system.cpu.itb.inst_misses 12083 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -143,121 +143,121 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5196 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5178 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3112 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13091335 # ITB inst accesses -system.cpu.itb.hits 13079160 # DTB hits -system.cpu.itb.misses 12175 # DTB misses -system.cpu.itb.accesses 13091335 # DTB accesses -system.cpu.numCycles 475963827 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13096078 # ITB inst accesses +system.cpu.itb.hits 13083995 # DTB hits +system.cpu.itb.misses 12083 # DTB misses +system.cpu.itb.accesses 13096078 # DTB accesses +system.cpu.numCycles 475967538 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits +system.cpu.BPredUnit.lookups 15172784 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12163693 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783478 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10392072 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8320250 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454874 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82640 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31374160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100930999 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15172784 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9775124 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22189039 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5936170 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131560 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97680943 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 99805 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208737 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 364 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13080141 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1016234 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6355 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155765235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799529 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166844 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 784165 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155765235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031878 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.212054 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33515539 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97301422 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20013824 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1028268 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3906182 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022458 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174763 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117645711 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 578390 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3906182 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35614317 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37590587 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53594123 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18875472 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6184554 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110140296 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21341 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4143290 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32170 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114983026 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504387694 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504296628 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91066 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78733405 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36249620 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891466 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797109 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12509806 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21006076 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13841580 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1961226 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2453000 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100941360 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057614 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126221061 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189445 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24437015 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65086313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513058 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155765235 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110569920 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13988875 8.98% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7307591 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6076063 3.90% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12752921 8.19% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2780626 1.79% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1679008 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 481895 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128336 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155765235 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57759 0.65% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available @@ -286,13 +286,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370724 94.64% 95.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416242 4.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59912166 47.47% 47.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95497 0.08% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued @@ -305,10 +305,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued @@ -316,365 +316,365 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53392141 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12455427 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued -system.cpu.iq.rate 0.265193 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126221061 # Type of FU issued +system.cpu.iq.rate 0.265188 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844727 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070073 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417312910 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127452442 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87180232 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23310 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12552 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134689743 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12379 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 626582 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5289586 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7312 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30140 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2042757 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106883 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1034668 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3906182 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28670725 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 450645 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103223935 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233802 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21006076 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13841580 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466072 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114504 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3680 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30140 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409816 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293009 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 702825 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122971529 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52416599 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3249532 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 225525 # number of nop insts executed -system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed -system.cpu.iew.exec_branches 11734992 # Number of branches executed -system.cpu.iew.exec_stores 12321310 # Number of stores executed -system.cpu.iew.exec_rate 0.258373 # Inst execution rate -system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47712496 # num instructions producing a value -system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value +system.cpu.iew.exec_nop 224961 # number of nop insts executed +system.cpu.iew.exec_refs 64739842 # number of memory reference insts executed +system.cpu.iew.exec_branches 11733959 # Number of branches executed +system.cpu.iew.exec_stores 12323243 # Number of stores executed +system.cpu.iew.exec_rate 0.258361 # Inst execution rate +system.cpu.iew.wb_sent 121621677 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87190526 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47712664 # num instructions producing a value +system.cpu.iew.wb_consumers 88871095 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183186 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536875 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24296365 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544556 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 611758 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151941485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.495079 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124150656 81.71% 81.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13572481 8.93% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3978264 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132059 1.40% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949397 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 999089 0.66% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1584839 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727042 0.48% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2847658 1.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60749034 # Number of instructions committed -system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151941485 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749175 # Number of instructions committed +system.cpu.commit.committedOps 78097811 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27515291 # Number of memory references committed -system.cpu.commit.loads 15716471 # Number of loads committed +system.cpu.commit.refs 27515313 # Number of memory references committed +system.cpu.commit.loads 15716490 # Number of loads committed system.cpu.commit.membars 413125 # Number of memory barriers committed -system.cpu.commit.branches 10023270 # Number of branches committed +system.cpu.commit.branches 10023277 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69135938 # Number of committed integer instructions. +system.cpu.commit.int_insts 69136099 # Number of committed integer instructions. system.cpu.commit.function_calls 996018 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2849213 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2847658 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249559242 # The number of ROB reads -system.cpu.rob.rob_writes 208759201 # The number of ROB writes -system.cpu.timesIdled 1773088 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320203271 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592410806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60598653 # Number of Instructions Simulated -system.cpu.committedOps 77947265 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60598653 # Number of Instructions Simulated -system.cpu.cpi 7.854363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.854363 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127318 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127318 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556742715 # number of integer regfile reads -system.cpu.int_regfile_writes 89972067 # number of integer regfile writes +system.cpu.rob.rob_reads 249572720 # The number of ROB reads +system.cpu.rob.rob_writes 208783952 # The number of ROB writes +system.cpu.timesIdled 1774345 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320202303 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592403923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60598794 # Number of Instructions Simulated +system.cpu.committedOps 77947430 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60598794 # Number of Instructions Simulated +system.cpu.cpi 7.854406 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.854406 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556725628 # number of integer regfile reads +system.cpu.int_regfile_writes 89967061 # number of integer regfile writes system.cpu.fp_regfile_reads 8371 # number of floating regfile reads -system.cpu.fp_regfile_writes 2922 # number of floating regfile writes -system.cpu.misc_regfile_reads 133101437 # number of misc regfile reads -system.cpu.misc_regfile_writes 912914 # number of misc regfile writes -system.cpu.icache.replacements 989669 # number of replacements -system.cpu.icache.tagsinuse 511.593818 # Cycle average of tags in use -system.cpu.icache.total_refs 12001618 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990181 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.120630 # Average number of references to valid blocks. +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 133111894 # number of misc regfile reads +system.cpu.misc_regfile_writes 912902 # number of misc regfile writes +system.cpu.icache.replacements 989535 # number of replacements +system.cpu.icache.tagsinuse 511.594104 # Cycle average of tags in use +system.cpu.icache.total_refs 12006884 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990047 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.127590 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.593818 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.594104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12001618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12001618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12001618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12001618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12001618 # number of overall hits -system.cpu.icache.overall_hits::total 12001618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1073577 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1073577 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1073577 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1073577 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1073577 # number of overall misses -system.cpu.icache.overall_misses::total 1073577 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14108104991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14108104991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14108104991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14108104991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14108104991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14108104991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13075195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13075195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13075195 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13075195 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13075195 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13075195 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082108 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082108 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082108 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082108 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082108 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082108 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13141.213896 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13141.213896 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13141.213896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13141.213896 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13142.418162 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7993.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.244068 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83350 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11447874492 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075733 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075733 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075733 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.745671 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13934718 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13934718 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7288473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7288473 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 284342 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 284342 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285730 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148087 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148087 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148087 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148087 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12985.481441 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12985.481441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35165.833379 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35165.833379 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13320.551582 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13320.551582 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30796.592580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30796.592580 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12775922 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7850000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2526 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3689903 # number of overall misses +system.cpu.dcache.overall_misses::total 3689903 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441506500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9441506500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104195765238 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104195765238 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181224000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181224000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 305500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113637271738 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24908023 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24908023 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24908023 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24908023 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049623 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049623 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289005 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289005 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045671 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045671 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000049 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000049 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148141 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148141 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12981.138418 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12981.138418 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35170.640313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35170.640313 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.273991 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.273991 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21821.428571 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21821.428571 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30796.818165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30796.818165 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25623 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15683 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2532 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.119668 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.211470 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609206 # number of writebacks -system.cpu.dcache.writebacks::total 609206 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339325 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 339325 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713436 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713436 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1355 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1355 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3052761 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3052761 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3052761 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3052761 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387400 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387400 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249042 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249042 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12206 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12206 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636442 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636442 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636442 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636442 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4757620458 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4757620458 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8541364957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8541364957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141415500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141415500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 332500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 332500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13298985415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13298985415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13298985415 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13298985415 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407548000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407548000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41944273253 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41944273253 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224351821253 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224351821253 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026423 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026423 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040973 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040973 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025547 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12280.899479 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12280.899479 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.885493 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34296.885493 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11585.736523 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11585.736523 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609265 # number of writebacks +system.cpu.dcache.writebacks::total 609265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339927 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 339927 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713517 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713517 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1356 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1356 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3053444 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3053444 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3053444 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3053444 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387398 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387398 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249061 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249061 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12243 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12243 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636459 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636459 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636459 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636459 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4758834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4758834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8540298916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8540298916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141913000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141913000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13299132916 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13299132916 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13299132916 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13299132916 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407357500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407357500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42045203371 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42045203371 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224452560871 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224452560871 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024296 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024296 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000049 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000049 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025552 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025552 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12284.095426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12284.095426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.988862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.988862 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11591.358327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11591.358327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19821.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19821.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -682,149 +682,149 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64397 # number of replacements -system.cpu.l2cache.tagsinuse 51351.941492 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1929097 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129792 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.862988 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2499029961500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36885.832563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 46.221263 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64402 # number of replacements +system.cpu.l2cache.tagsinuse 51349.814622 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1928941 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129796 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.861329 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2499028808000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36883.442332 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 42.609278 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8173.888273 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6245.999155 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.562833 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000705 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 8182.264424 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6241.498349 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.562797 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000650 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124724 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095306 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5793337496 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6302064496 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730274500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735566500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32529244761 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730210500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735502500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32612370999 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32612370999 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199259519261 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199264811261 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026667 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985863 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985863 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541185 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541185 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090356 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090356 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199342581499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199347873499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015539 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986806 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986806 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541036 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541036 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090316 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090316 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41054.524670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40455.603435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40776.100499 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.926255 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.817791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40457.094439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40770.241468 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.942407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.942407 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40256.545723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40256.545723 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40255.737727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40255.737727 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -959,16 +959,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307054297856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307054297856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307562103462 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307562103462 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88032 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 8459be5ac..820ef6b3e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616879 # Number of seconds simulated -sim_ticks 2616878893500 # Number of ticks simulated -final_tick 2616878893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.004001 # Number of seconds simulated +sim_ticks 1004001369000 # Number of ticks simulated +final_tick 1004001369000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63327 # Simulator instruction rate (inst/s) -host_op_rate 81506 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2627232906 # Simulator tick rate (ticks/s) -host_mem_usage 387740 # Number of bytes of host memory used -host_seconds 996.06 # Real time elapsed on the host -sim_insts 63077499 # Number of instructions simulated -sim_ops 81184436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 397632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4358324 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 424512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5245616 # Number of bytes read from this memory -system.physmem.bytes_read::total 131538596 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 397632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 424512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4254848 # Number of bytes written to this memory +host_inst_rate 89245 # Simulator instruction rate (inst/s) +host_op_rate 114826 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1450204701 # Simulator tick rate (ticks/s) +host_mem_usage 385792 # Number of bytes of host memory used +host_seconds 692.32 # Real time elapsed on the host +sim_insts 61785538 # Number of instructions simulated +sim_ops 79495701 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 44040192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 411712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4381300 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 403392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5239536 # Number of bytes read from this memory +system.physmem.bytes_read::total 54478052 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 411712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 403392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4277248 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7283984 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6213 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6633 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301853 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66482 # Number of write requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 5505024 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6433 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81894 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5668214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66832 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823766 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46280525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 73 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1665466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 162221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2004531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50265450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 162221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1625925 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1151041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2783462 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1625925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46280525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1671963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 162221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3155573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53048913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43864673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 410071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4363839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 401784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5218654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54260934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 410071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 401784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 811855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4260201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 16932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2998092 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7275225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4260201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43864673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 410071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4380771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 401784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 8216746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 61536159 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -75,246 +75,246 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72648 # number of replacements -system.l2c.tagsinuse 53148.103120 # Cycle average of tags in use -system.l2c.total_refs 1925510 # Total number of references to valid blocks. -system.l2c.sampled_refs 137845 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.968660 # Average number of references to valid blocks. +system.realview.nvmem.bw_read::cpu0.inst 64 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 382 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 446 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 64 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 382 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 446 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 64 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 382 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 446 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72797 # number of replacements +system.l2c.tagsinuse 53893.248657 # Cycle average of tags in use +system.l2c.total_refs 1879341 # Total number of references to valid blocks. +system.l2c.sampled_refs 137955 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.622855 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37769.007236 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.653962 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.872957 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4238.981277 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2955.984743 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 14.025683 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4027.816705 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4137.760558 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.576309 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39653.380215 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.693619 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000676 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4026.678241 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2797.052262 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.937877 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3656.015551 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3744.490216 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.605063 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000056 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064682 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045105 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061460 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.063137 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.810976 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 34723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398866 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166115 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 54785 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6733 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 615111 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 202597 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1484651 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 585034 # number of Writeback hits -system.l2c.Writeback_hits::total 585034 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1035 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 803 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1838 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48272 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107268 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 34723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5721 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 398866 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214387 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 54785 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6733 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 615111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 261593 # number of demand (read+write) hits -system.l2c.demand_hits::total 1591919 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 34723 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5721 # number of overall hits -system.l2c.overall_hits::cpu0.inst 398866 # number of overall hits -system.l2c.overall_hits::cpu0.data 214387 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 54785 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6733 # number of overall hits -system.l2c.overall_hits::cpu1.inst 615111 # number of overall hits -system.l2c.overall_hits::cpu1.data 261593 # number of overall hits -system.l2c.overall_hits::total 1591919 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6086 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6313 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6595 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6354 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25379 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5710 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4349 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10059 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 787 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1376 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63248 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76888 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140136 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6086 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69561 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6595 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83242 # number of demand (read+write) misses -system.l2c.demand_misses::total 165515 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6086 # number of overall misses -system.l2c.overall_misses::cpu0.data 69561 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6595 # number of overall misses -system.l2c.overall_misses::cpu1.data 83242 # number of overall misses -system.l2c.overall_misses::total 165515 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 469500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 164500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 324649999 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40513.611874 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40924.743030 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9084291 # DTB read hits -system.cpu0.dtb.read_misses 36586 # DTB read misses -system.cpu0.dtb.write_hits 5291622 # DTB write hits -system.cpu0.dtb.write_misses 6420 # DTB write misses +system.cpu0.dtb.read_hits 8992964 # DTB read hits +system.cpu0.dtb.read_misses 35495 # DTB read misses +system.cpu0.dtb.write_hits 5204763 # DTB write hits +system.cpu0.dtb.write_misses 6364 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2157 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2149 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1250 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 357 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9120877 # DTB read accesses -system.cpu0.dtb.write_accesses 5298042 # DTB write accesses +system.cpu0.dtb.perms_faults 536 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9028459 # DTB read accesses +system.cpu0.dtb.write_accesses 5211127 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14375913 # DTB hits -system.cpu0.dtb.misses 43006 # DTB misses -system.cpu0.dtb.accesses 14418919 # DTB accesses -system.cpu0.itb.inst_hits 4432740 # ITB inst hits -system.cpu0.itb.inst_misses 5766 # ITB inst misses +system.cpu0.dtb.hits 14197727 # DTB hits +system.cpu0.dtb.misses 41859 # DTB misses +system.cpu0.dtb.accesses 14239586 # DTB accesses +system.cpu0.itb.inst_hits 4345219 # ITB inst hits +system.cpu0.itb.inst_misses 5468 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -536,542 +536,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1406 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1393 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1571 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1660 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4438506 # ITB inst accesses -system.cpu0.itb.hits 4432740 # DTB hits -system.cpu0.itb.misses 5766 # DTB misses -system.cpu0.itb.accesses 4438506 # DTB accesses -system.cpu0.numCycles 73427885 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4350687 # ITB inst accesses +system.cpu0.itb.hits 4345219 # DTB hits +system.cpu0.itb.misses 5468 # DTB misses +system.cpu0.itb.accesses 4350687 # DTB accesses +system.cpu0.numCycles 69454344 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6227156 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4741082 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 330435 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3793257 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3054809 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6140299 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4680843 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 325697 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3967848 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3011514 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 703344 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 32160 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12941361 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33277959 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6227156 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3758153 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7819599 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1599392 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 82441 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 23494459 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 62047 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 92342 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 197 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4430967 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 174323 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2958 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 45648361 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.940627 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.320252 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 689087 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31971 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11903950 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32719278 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6140299 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3700601 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7697719 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1567081 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66811 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21663795 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4784 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 55267 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90495 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4343360 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 170443 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2579 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42607741 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.991445 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.370542 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 37836918 82.89% 82.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 627349 1.37% 84.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 824369 1.81% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 703980 1.54% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 786046 1.72% 89.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 579188 1.27% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 721067 1.58% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 372009 0.81% 93.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3197435 7.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34918154 81.95% 81.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 615023 1.44% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 811777 1.91% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 689946 1.62% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 788421 1.85% 88.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 570027 1.34% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 709248 1.66% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 365635 0.86% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3139510 7.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 45648361 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.084806 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.453206 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13430389 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 23511343 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7018661 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 602696 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1085272 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 979924 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 65913 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41505511 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 215463 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1085272 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14040409 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6748642 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14460031 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6960379 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2353628 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40289777 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2418 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 473813 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1332712 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 81 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40678861 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 182059364 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 182024641 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34723 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31700311 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8978549 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 462421 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 418498 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5663645 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7939186 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5895346 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1154000 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1239736 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 38066358 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 944329 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38270432 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91181 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6810597 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14485199 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 255192 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 45648361 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.838375 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.464052 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42607741 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088408 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471090 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12410407 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21637687 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6924723 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 574768 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1060156 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 960041 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65781 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40808812 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 215037 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1060156 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12993427 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5870248 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13615125 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6864393 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2204392 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39624437 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2198 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 433654 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1244123 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39987634 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 178950817 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178916692 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34125 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31114791 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8872842 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 451750 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 410482 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5405254 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7790925 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5788375 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1121917 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1222446 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37402937 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 939151 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37702557 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87742 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6716452 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14173286 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 260083 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42607741 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.884876 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.498206 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 29755811 65.18% 65.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6343756 13.90% 79.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3236490 7.09% 86.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2520305 5.52% 91.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2106581 4.61% 96.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 935116 2.05% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 513948 1.13% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 183643 0.40% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52711 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27166804 63.76% 63.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5957097 13.98% 77.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3214078 7.54% 85.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2477962 5.82% 91.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2111115 4.95% 96.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 940986 2.21% 98.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 497762 1.17% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188040 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53897 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 45648361 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42607741 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27042 2.53% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 835512 78.03% 80.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207702 19.40% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 24897 2.34% 2.34% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 455 0.04% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841667 79.11% 81.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 196890 18.51% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22977707 60.04% 60.18% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50299 0.13% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9565645 24.99% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5623724 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22610692 59.97% 60.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48707 0.13% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 696 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9470500 25.12% 85.36% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5519656 14.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38270432 # Type of FU issued -system.cpu0.iq.rate 0.521198 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070720 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.027978 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 123385364 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45829388 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35329971 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8465 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4764 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3918 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39284390 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323676 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37702557 # Type of FU issued +system.cpu0.iq.rate 0.542839 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1063909 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028218 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119197860 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45066260 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34725350 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8284 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4664 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3878 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38709880 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4307 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 311315 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1511954 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3775 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13508 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 616210 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1483597 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3551 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13024 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 603760 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149507 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5450 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2189792 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1085272 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4652854 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 126877 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39130245 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 91852 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7939186 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5895346 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 610877 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49621 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17387 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13508 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 175421 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 130280 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 305701 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37846246 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9402583 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 424186 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1060156 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4217100 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98020 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38461133 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 95338 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7790925 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5788375 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 610075 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39436 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2994 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13024 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 172050 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 129143 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 301193 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37281122 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9309198 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 421435 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119558 # number of nop insts executed -system.cpu0.iew.exec_refs 14967440 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4996145 # Number of branches executed -system.cpu0.iew.exec_stores 5564857 # Number of stores executed -system.cpu0.iew.exec_rate 0.515421 # Inst execution rate -system.cpu0.iew.wb_sent 37628600 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35333889 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18696932 # num instructions producing a value -system.cpu0.iew.wb_consumers 35648829 # num instructions consuming a value +system.cpu0.iew.exec_nop 119045 # number of nop insts executed +system.cpu0.iew.exec_refs 14772448 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4922535 # Number of branches executed +system.cpu0.iew.exec_stores 5463250 # Number of stores executed +system.cpu0.iew.exec_rate 0.536772 # Inst execution rate +system.cpu0.iew.wb_sent 37065432 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34729228 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18441672 # num instructions producing a value +system.cpu0.iew.wb_consumers 35371865 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.481205 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524475 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.500030 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.521366 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6705821 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 689137 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 265687 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 44599494 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.717911 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.673991 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6577828 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 679068 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 261125 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41583448 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.756316 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.712971 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32451965 72.76% 72.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6077972 13.63% 86.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1948934 4.37% 90.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1034999 2.32% 93.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 805126 1.81% 94.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 506776 1.14% 96.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 402342 0.90% 96.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 201836 0.45% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1169544 2.62% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29716852 71.46% 71.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5893148 14.17% 85.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1935709 4.65% 90.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 983715 2.37% 92.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 787040 1.89% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 514741 1.24% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 394337 0.95% 96.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216625 0.52% 97.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1141281 2.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 44599494 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24278814 # Number of instructions committed -system.cpu0.commit.committedOps 32018477 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41583448 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23837222 # Number of instructions committed +system.cpu0.commit.committedOps 31450221 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11706368 # Number of memory references committed -system.cpu0.commit.loads 6427232 # Number of loads committed -system.cpu0.commit.membars 234590 # Number of memory barriers committed -system.cpu0.commit.branches 4349138 # Number of branches committed +system.cpu0.commit.refs 11491943 # Number of memory references committed +system.cpu0.commit.loads 6307328 # Number of loads committed +system.cpu0.commit.membars 231960 # Number of memory barriers committed +system.cpu0.commit.branches 4279027 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28284672 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500279 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1169544 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27769802 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489719 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1141281 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 81269635 # The number of ROB reads -system.cpu0.rob.rob_writes 78536158 # The number of ROB writes -system.cpu0.timesIdled 427323 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27779524 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5160286096 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24198072 # Number of Instructions Simulated -system.cpu0.committedOps 31937735 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24198072 # Number of Instructions Simulated -system.cpu0.cpi 3.034452 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.034452 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.329549 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.329549 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176614966 # number of integer regfile reads -system.cpu0.int_regfile_writes 35097459 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3370 # number of floating regfile reads -system.cpu0.fp_regfile_writes 922 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47564974 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527822 # number of misc regfile writes -system.cpu0.icache.replacements 405114 # number of replacements -system.cpu0.icache.tagsinuse 511.561657 # Cycle average of tags in use -system.cpu0.icache.total_refs 3991755 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 405626 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.840974 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7272099000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.561657 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3991755 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3991755 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3991755 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3991755 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3991755 # number of overall hits -system.cpu0.icache.overall_hits::total 3991755 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 439070 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 439070 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 439070 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 439070 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 439070 # number of overall misses -system.cpu0.icache.overall_misses::total 439070 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7078203996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7078203996 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7078203996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7078203996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7078203996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7078203996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4430825 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4430825 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4430825 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4430825 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4430825 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4430825 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099094 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099094 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099094 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099094 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099094 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099094 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16120.900986 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16120.900986 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16120.900986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16120.900986 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1491997 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77601886 # The number of ROB reads +system.cpu0.rob.rob_writes 77118702 # The number of ROB writes +system.cpu0.timesIdled 360842 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26846603 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 1938505291 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23756480 # Number of Instructions Simulated +system.cpu0.committedOps 31369479 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23756480 # Number of Instructions Simulated +system.cpu0.cpi 2.923596 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.923596 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.342045 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.342045 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 173851540 # number of integer regfile reads +system.cpu0.int_regfile_writes 34503400 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3265 # number of floating regfile reads +system.cpu0.fp_regfile_writes 914 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46745590 # number of misc regfile reads +system.cpu0.misc_regfile_writes 520572 # number of misc regfile writes +system.cpu0.icache.replacements 396597 # number of replacements +system.cpu0.icache.tagsinuse 510.934010 # Cycle average of tags in use +system.cpu0.icache.total_refs 3914161 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 397109 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.856641 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 7097415000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.934010 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.997918 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997918 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3914161 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3914161 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3914161 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3914161 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3914161 # number of overall hits +system.cpu0.icache.overall_hits::total 3914161 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 429060 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 429060 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 429060 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 429060 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 429060 # number of overall misses +system.cpu0.icache.overall_misses::total 429060 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5859924996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5859924996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5859924996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5859924996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5859924996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5859924996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4343221 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4343221 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4343221 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4343221 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4343221 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4343221 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.098788 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.098788 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.098788 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.098788 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.098788 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.098788 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13657.588673 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.588673 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13657.588673 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13657.588673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13657.588673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13657.588673 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2603 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8776.452941 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.133721 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33429 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33429 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33429 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33429 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33429 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33429 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405641 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 405641 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 405641 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 405641 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 405641 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 405641 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5425368997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5425368997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5425368997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5425368997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5425368997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5425368997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8328000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8328000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8328000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8328000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091550 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.091550 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.091550 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13374.804315 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31940 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31940 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31940 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31940 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31940 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31940 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 397120 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 397120 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 397120 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 397120 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 397120 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 397120 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4781055496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4781055496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4781055496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4781055496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4781055496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4781055496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8271000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8271000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8271000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8271000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091434 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.091434 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.091434 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12039.321857 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12039.321857 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12039.321857 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12039.321857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12039.321857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12039.321857 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275935 # number of replacements -system.cpu0.dcache.tagsinuse 476.765535 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9559328 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276447 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.579243 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 51426000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.765535 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.931183 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.931183 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5939119 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5939119 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3227738 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3227738 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174834 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174834 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171593 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171593 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9166857 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9166857 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9166857 # number of overall hits -system.cpu0.dcache.overall_hits::total 9166857 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 401304 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 401304 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1595717 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1595717 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8980 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8980 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7781 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7781 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1997021 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1997021 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1997021 # number of overall misses -system.cpu0.dcache.overall_misses::total 1997021 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7282608500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 7282608500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71716653343 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71716653343 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113510500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 113510500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 89966000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 89966000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 78999261843 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 78999261843 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 78999261843 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 78999261843 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6340423 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6340423 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4823455 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4823455 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183814 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183814 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179374 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179374 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11163878 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11163878 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11163878 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11163878 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063293 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063293 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330824 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330824 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048854 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048854 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043379 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043379 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178882 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178882 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178882 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178882 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18147.360854 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18147.360854 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44943.215710 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44943.215710 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12640.367483 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12640.367483 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11562.267061 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11562.267061 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39558.553387 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39558.553387 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39558.553387 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39558.553387 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7775987 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1662000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1508 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 96 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5156.490053 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 17312.500000 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275715 # number of replacements +system.cpu0.dcache.tagsinuse 460.505640 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9383873 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276227 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.971599 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 50121000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 460.505640 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899425 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899425 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5832717 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5832717 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3162819 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3162819 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174349 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174349 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171411 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171411 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8995536 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8995536 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8995536 # number of overall hits +system.cpu0.dcache.overall_hits::total 8995536 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 389324 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 389324 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1581862 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1581862 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8809 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8809 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1971186 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1971186 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1971186 # number of overall misses +system.cpu0.dcache.overall_misses::total 1971186 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5380617500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5380617500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64543979864 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 64543979864 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88840500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88840500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 65914500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 65914500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 69924597364 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 69924597364 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 69924597364 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 69924597364 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6222041 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6222041 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183158 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183158 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178875 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 178875 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10966722 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10966722 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10966722 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10966722 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062572 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062572 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333397 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333397 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048095 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048095 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.041727 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.041727 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179742 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.179742 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179742 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.179742 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13820.410506 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13820.410506 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40802.535154 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40802.535154 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10085.196958 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10085.196958 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8830.988746 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8830.988746 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35473.363429 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35473.363429 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35473.363429 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35473.363429 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7710 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3643 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 580 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 95 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.293103 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 38.347368 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256111 # number of writebacks -system.cpu0.dcache.writebacks::total 256111 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211639 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 211639 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1464558 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1464558 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 529 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 529 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1676197 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1676197 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1676197 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1676197 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189665 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189665 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131159 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131159 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7774 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7774 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320824 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320824 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320824 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320824 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2812273446 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2812273446 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4676498504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4676498504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79208005 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79208005 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65545528 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65545528 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7488771950 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7488771950 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7488771950 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7488771950 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13454662000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13454662000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1295219899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1295219899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14749881899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14749881899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029914 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029914 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043340 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043340 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028738 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028738 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14827.582559 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14827.582559 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35655.185721 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35655.185721 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9372.619217 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9372.619217 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8431.377412 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8431.377412 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256563 # number of writebacks +system.cpu0.dcache.writebacks::total 256563 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201019 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 201019 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451459 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1451459 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 444 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 444 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1652478 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1652478 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1652478 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1652478 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188305 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188305 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130403 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130403 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8365 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8365 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318708 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318708 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318708 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318708 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2330576500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2330576500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4457768490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4457768490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67402500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67402500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50994500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50994500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6788344990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6788344990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6788344990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6788344990 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13509879500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13509879500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1216585395 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1216585395 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14726464895 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14726464895 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030264 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030264 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027484 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027484 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045671 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045671 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041705 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041705 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029061 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029061 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12376.604445 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12376.604445 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34184.554727 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34184.554727 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8057.680813 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8057.680813 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6835.723861 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6835.723861 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1081,27 +1077,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43437526 # DTB read hits -system.cpu1.dtb.read_misses 44897 # DTB read misses -system.cpu1.dtb.write_hits 7020721 # DTB write hits -system.cpu1.dtb.write_misses 11707 # DTB write misses +system.cpu1.dtb.read_hits 43128318 # DTB read hits +system.cpu1.dtb.read_misses 43709 # DTB read misses +system.cpu1.dtb.write_hits 6848528 # DTB write hits +system.cpu1.dtb.write_misses 11704 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2363 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 4220 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 316 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3032 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 376 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43482423 # DTB read accesses -system.cpu1.dtb.write_accesses 7032428 # DTB write accesses +system.cpu1.dtb.perms_faults 614 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43172027 # DTB read accesses +system.cpu1.dtb.write_accesses 6860232 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50458247 # DTB hits -system.cpu1.dtb.misses 56604 # DTB misses -system.cpu1.dtb.accesses 50514851 # DTB accesses -system.cpu1.itb.inst_hits 9182577 # ITB inst hits -system.cpu1.itb.inst_misses 6227 # ITB inst misses +system.cpu1.dtb.hits 49976846 # DTB hits +system.cpu1.dtb.misses 55413 # DTB misses +system.cpu1.dtb.accesses 50032259 # DTB accesses +system.cpu1.itb.inst_hits 9000425 # ITB inst hits +system.cpu1.itb.inst_misses 6008 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1110,538 +1106,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1553 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1649 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1639 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9188804 # ITB inst accesses -system.cpu1.itb.hits 9182577 # DTB hits -system.cpu1.itb.misses 6227 # DTB misses -system.cpu1.itb.accesses 9188804 # DTB accesses -system.cpu1.numCycles 420121858 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9006433 # ITB inst accesses +system.cpu1.itb.hits 9000425 # DTB hits +system.cpu1.itb.misses 6008 # DTB misses +system.cpu1.itb.accesses 9006433 # DTB accesses +system.cpu1.numCycles 411196854 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9688118 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7965440 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 469703 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6737081 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5659691 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9419862 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7750034 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 456519 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6563236 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5515830 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 834304 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 51249 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22081738 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71759711 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9688118 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6493995 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15294978 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4586075 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 88967 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 80951772 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5897 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 52783 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142728 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9180482 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 856181 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3761 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 121742103 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.711584 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.060066 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 808543 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 49558 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 20407169 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 70137907 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9419862 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6324373 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14954252 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4469714 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69962 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78537497 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4608 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48031 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 137349 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 105 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8998373 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 846947 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3472 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 117207584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.722166 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.072596 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 106455334 87.44% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 840434 0.69% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1014558 0.83% 88.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2075766 1.71% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1622971 1.33% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 608124 0.50% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2270082 1.86% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 458736 0.38% 94.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6396098 5.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 102261187 87.25% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 819653 0.70% 87.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 985556 0.84% 88.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2033886 1.74% 90.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1605966 1.37% 91.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 588504 0.50% 92.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2242580 1.91% 94.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 432923 0.37% 94.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6237329 5.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 121742103 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.023060 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.170807 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23726811 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 80682083 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13746238 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 564864 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3022107 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1180909 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102849 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 80937245 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 340282 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3022107 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25270664 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33976360 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 42200569 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12677087 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4595316 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74576204 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 20275 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 711120 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3286160 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33636 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 79110058 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 343673709 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 343614714 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58995 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50196787 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28913271 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 480316 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 419400 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8402630 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14031046 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8540774 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1078770 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1484758 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 67259946 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1207834 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 91753969 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 112690 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18841154 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53684147 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 287920 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 121742103 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.753675 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.492082 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 117207584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022908 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.170570 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 22086254 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78170196 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13474165 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 527031 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2949938 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1142917 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100567 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 79224649 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 333390 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2949938 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23604711 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32726720 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41122515 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12389079 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4414621 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 72870010 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19270 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 676690 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3162757 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33999 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 77285870 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 335898709 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 335839792 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58917 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49079142 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28206728 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 460869 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 403889 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7994466 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13706939 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8341114 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1036889 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1489334 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 65799753 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1184242 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 90434427 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 105475 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18495331 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52692216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 284904 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 117207584 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.771575 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.509324 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 89993106 73.92% 73.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9114072 7.49% 81.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4553910 3.74% 85.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4000568 3.29% 88.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10707495 8.80% 97.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1970764 1.62% 98.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1044074 0.86% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 282783 0.23% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75331 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86216438 73.56% 73.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8629120 7.36% 80.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4443515 3.79% 84.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3900369 3.33% 88.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10705508 9.13% 97.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1918417 1.64% 98.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1028985 0.88% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 292713 0.25% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 72519 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 121742103 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 117207584 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28572 0.36% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 997 0.01% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7569076 95.94% 96.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 290938 3.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 27077 0.34% 0.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 994 0.01% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551420 96.03% 96.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 284170 3.61% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313802 0.34% 0.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39340328 42.88% 43.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61412 0.07% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1696 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44630775 48.64% 91.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7405942 8.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313737 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 38536009 42.61% 42.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59463 0.07% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 3 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1448 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44313821 49.00% 92.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7209923 7.97% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 91753969 # Type of FU issued -system.cpu1.iq.rate 0.218398 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7889583 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.085986 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 313294010 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 87318397 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55594578 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14739 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6796 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 99322053 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7697 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 360033 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 90434427 # Type of FU issued +system.cpu1.iq.rate 0.219930 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7863661 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.086954 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 306085964 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 85487883 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54343960 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14808 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8052 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6813 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 97976579 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7772 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 344186 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4037305 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4422 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 18147 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1519259 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3955729 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4256 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17131 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1493245 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965400 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1049364 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31918877 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1021818 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3022107 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25590166 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 410250 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68573370 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 132853 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14031046 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8540774 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 897358 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 85617 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 14991 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 18147 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 245880 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 172266 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 418146 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 88914677 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43821187 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2839292 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2949938 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24820563 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 368762 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 67089139 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132396 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13706939 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8341114 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 882128 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65563 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3455 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17131 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 238596 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 168339 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 406935 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87595702 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43496570 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2838725 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105590 # number of nop insts executed -system.cpu1.iew.exec_refs 51148287 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7278596 # Number of branches executed -system.cpu1.iew.exec_stores 7327100 # Number of stores executed -system.cpu1.iew.exec_rate 0.211640 # Inst execution rate -system.cpu1.iew.wb_sent 87750200 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55601374 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30754041 # num instructions producing a value -system.cpu1.iew.wb_consumers 54503523 # num instructions consuming a value +system.cpu1.iew.exec_nop 105144 # number of nop insts executed +system.cpu1.iew.exec_refs 50630638 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7094868 # Number of branches executed +system.cpu1.iew.exec_stores 7134068 # Number of stores executed +system.cpu1.iew.exec_rate 0.213026 # Inst execution rate +system.cpu1.iew.wb_sent 86451134 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54350773 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30183399 # num instructions producing a value +system.cpu1.iew.wb_consumers 53726330 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.132346 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.564258 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.132177 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.561799 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 18816555 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 919914 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 368704 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 118768431 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.415231 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.371949 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 18453809 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899338 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 357846 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 114304625 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.421644 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.382099 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 101503583 85.46% 85.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8523872 7.18% 92.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2201888 1.85% 94.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1303888 1.10% 95.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1288434 1.08% 96.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 587085 0.49% 97.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 997227 0.84% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 495127 0.42% 98.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1867327 1.57% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97479553 85.28% 85.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8276936 7.24% 92.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2163829 1.89% 94.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1249082 1.09% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1246649 1.09% 96.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 573488 0.50% 97.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1001794 0.88% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 527131 0.46% 98.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1786163 1.56% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 118768431 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38949066 # Number of instructions committed -system.cpu1.commit.committedOps 49316340 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 114304625 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38098697 # Number of instructions committed +system.cpu1.commit.committedOps 48195861 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17015256 # Number of memory references committed -system.cpu1.commit.loads 9993741 # Number of loads committed -system.cpu1.commit.membars 202364 # Number of memory barriers committed -system.cpu1.commit.branches 6138465 # Number of branches committed +system.cpu1.commit.refs 16599079 # Number of memory references committed +system.cpu1.commit.loads 9751210 # Number of loads committed +system.cpu1.commit.membars 196398 # Number of memory barriers committed +system.cpu1.commit.branches 5978782 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43706861 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556456 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1867327 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42713997 # Number of committed integer instructions. +system.cpu1.commit.function_calls 536442 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1786163 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 183919327 # The number of ROB reads -system.cpu1.rob.rob_writes 139377269 # The number of ROB writes -system.cpu1.timesIdled 1519096 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 298379755 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4813097636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38879427 # Number of Instructions Simulated -system.cpu1.committedOps 49246701 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38879427 # Number of Instructions Simulated -system.cpu1.cpi 10.805763 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.805763 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092543 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092543 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 397952991 # number of integer regfile reads -system.cpu1.int_regfile_writes 58412580 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4851 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2298 # number of floating regfile writes -system.cpu1.misc_regfile_reads 91535746 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429838 # number of misc regfile writes -system.cpu1.icache.replacements 621848 # number of replacements -system.cpu1.icache.tagsinuse 498.728003 # Cycle average of tags in use -system.cpu1.icache.total_refs 8507924 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 622360 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.670422 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 75775782000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.728003 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974078 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974078 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8507924 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8507924 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8507924 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8507924 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8507924 # number of overall hits -system.cpu1.icache.overall_hits::total 8507924 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 672506 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 672506 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 672506 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 672506 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 672506 # number of overall misses -system.cpu1.icache.overall_misses::total 672506 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10595189995 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10595189995 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10595189995 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10595189995 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10595189995 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10595189995 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9180430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9180430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9180430 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9180430 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9180430 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9180430 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073254 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073254 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073254 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073254 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073254 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073254 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15754.788797 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15754.788797 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15754.788797 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15754.788797 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15754.788797 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15754.788797 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1171995 # number of cycles access was blocked +system.cpu1.rob.rob_reads 178079063 # The number of ROB reads +system.cpu1.rob.rob_writes 136331127 # The number of ROB writes +system.cpu1.timesIdled 1409981 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 293989270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1596154251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38029058 # Number of Instructions Simulated +system.cpu1.committedOps 48126222 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38029058 # Number of Instructions Simulated +system.cpu1.cpi 10.812702 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.812702 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092484 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092484 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391789649 # number of integer regfile reads +system.cpu1.int_regfile_writes 57184516 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4895 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes +system.cpu1.misc_regfile_reads 89371872 # number of misc regfile reads +system.cpu1.misc_regfile_writes 414539 # number of misc regfile writes +system.cpu1.icache.replacements 604043 # number of replacements +system.cpu1.icache.tagsinuse 477.396851 # Cycle average of tags in use +system.cpu1.icache.total_refs 8346622 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 604555 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.806224 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74944474500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 477.396851 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.932416 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.932416 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8346622 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8346622 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8346622 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8346622 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8346622 # number of overall hits +system.cpu1.icache.overall_hits::total 8346622 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 651698 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 651698 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 651698 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 651698 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 651698 # number of overall misses +system.cpu1.icache.overall_misses::total 651698 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8706583495 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8706583495 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8706583495 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8706583495 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8706583495 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8706583495 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8998320 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8998320 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8998320 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8998320 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8998320 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8998320 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072424 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.072424 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072424 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.072424 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072424 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.072424 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13359.843816 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13359.843816 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13359.843816 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13359.843816 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13359.843816 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13359.843816 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1860 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 180 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 164 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6511.083333 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.341463 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50115 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 50115 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 50115 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 50115 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 50115 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 50115 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622391 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 622391 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 622391 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 622391 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 622391 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 622391 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8107387995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8107387995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8107387995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8107387995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8107387995 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8107387995 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3209000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3209000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3209000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3209000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067795 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067795 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067795 # 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mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.067188 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.067188 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11772.764557 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11772.764557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11772.764557 # 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Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.304887 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951767 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951767 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8608527 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8608527 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4253626 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4253626 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105088 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105088 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100770 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100770 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12862153 # 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miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097730 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135218 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135218 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135218 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135218 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19855.530512 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19855.530512 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41412.782733 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41412.782733 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11672.799776 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11672.799776 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8714.567109 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8714.567109 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 36980.444290 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 36980.444290 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29857004 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5566500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6768 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4411.495863 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 33133.928571 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360631 # number of replacements +system.cpu1.dcache.tagsinuse 472.241123 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12789913 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 361011 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.428042 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 71012585000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 472.241123 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.922346 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.922346 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8401496 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8401496 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4150430 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4150430 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 102060 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 102060 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 98301 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 98301 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12551926 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12551926 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12551926 # number of overall hits +system.cpu1.dcache.overall_hits::total 12551926 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 394540 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 394540 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1551061 # 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number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5701491 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5701491 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116114 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 116114 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108883 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 108883 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14497527 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14497527 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14497527 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14497527 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044854 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044854 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272045 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.272045 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121036 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121036 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097187 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097187 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134202 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134202 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134202 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134202 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.839154 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.839154 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36325.904025 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 36325.904025 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9186.566102 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9186.566102 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6140.568891 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6140.568891 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31955.454136 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 31955.454136 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31955.454136 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 31955.454136 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 23777 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 10847 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3216 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.393346 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 66.956790 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328923 # number of writebacks -system.cpu1.dcache.writebacks::total 328923 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180962 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 180962 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1434656 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1434656 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1453 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1615618 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1615618 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1615618 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1615618 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 232544 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 232544 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162978 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162978 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12841 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12841 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 395522 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 395522 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 395522 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 395522 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3583215887 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3583215887 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5542320073 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5542320073 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104521007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104521007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61064509 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61064509 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9125535960 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9125535960 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9125535960 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9125535960 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169307109000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169307109000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40930247169 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40930247169 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210237356169 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210237356169 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025775 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025775 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107562 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107562 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097677 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097677 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026593 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026593 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15408.765167 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15408.765167 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34006.553480 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34006.553480 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8139.631415 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8139.631415 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5597.626639 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5597.626639 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 325044 # number of writebacks +system.cpu1.dcache.writebacks::total 325044 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 165979 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 165979 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1389692 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1389692 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1430 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1430 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1555671 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1555671 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1555671 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1555671 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228561 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228561 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161369 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161369 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12624 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12624 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10579 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10579 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389930 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389930 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389930 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389930 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2788566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2788566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5142243728 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5142243728 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88146000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88146000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43823500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43823500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7930810228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7930810228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7930810228 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7930810228 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168983572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168983572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40847570579 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40847570579 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 209831143079 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209831143079 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025985 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025985 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028303 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028303 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108721 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108721 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026896 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026896 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12200.535087 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12200.535087 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31866.366700 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31866.366700 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6982.414449 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6982.414449 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4142.499291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4142.499291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1663,18 +1663,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1322950372611 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1322950372611 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479854932995 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 479854932995 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479854932995 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 479854932995 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43807 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43104 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53930 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 52217 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 2d955a00e..9bc6eb181 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534231 # Number of seconds simulated -sim_ticks 2534231333000 # Number of ticks simulated -final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534230 # Number of seconds simulated +sim_ticks 2534229746000 # Number of ticks simulated +final_tick 2534229746000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58448 # Simulator instruction rate (inst/s) -host_op_rate 75181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2444289303 # Simulator tick rate (ticks/s) -host_mem_usage 386996 # Number of bytes of host memory used -host_seconds 1036.80 # Real time elapsed on the host -sim_insts 60598653 # Number of instructions simulated -sim_ops 77947265 # Number of ops (including micro ops) simulated +host_inst_rate 72788 # Simulator instruction rate (inst/s) +host_op_rate 93626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3043970352 # Simulator tick rate (ticks/s) +host_mem_usage 380668 # Number of bytes of host memory used +host_seconds 832.54 # Real time elapsed on the host +sim_insts 60598794 # Number of instructions simulated +sim_ops 77947430 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory -system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095568 # Number of bytes read from this memory +system.physmem.bytes_read::total 129434640 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784256 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 142152 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47169229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1313 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51074548 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47169229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1313 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4779219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53758065 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -69,27 +69,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51729232 # DTB read hits -system.cpu.dtb.read_misses 76957 # DTB read misses -system.cpu.dtb.write_hits 11808980 # DTB write hits -system.cpu.dtb.write_misses 17307 # DTB write misses +system.cpu.dtb.read_hits 51729015 # DTB read hits +system.cpu.dtb.read_misses 77642 # DTB read misses +system.cpu.dtb.write_hits 11810988 # DTB write hits +system.cpu.dtb.write_misses 17459 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4248 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2642 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51806189 # DTB read accesses -system.cpu.dtb.write_accesses 11826287 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51806657 # DTB read accesses +system.cpu.dtb.write_accesses 11828447 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63538212 # DTB hits -system.cpu.dtb.misses 94264 # DTB misses -system.cpu.dtb.accesses 63632476 # DTB accesses -system.cpu.itb.inst_hits 13079160 # ITB inst hits -system.cpu.itb.inst_misses 12175 # ITB inst misses +system.cpu.dtb.hits 63540003 # DTB hits +system.cpu.dtb.misses 95101 # DTB misses +system.cpu.dtb.accesses 63635104 # DTB accesses +system.cpu.itb.inst_hits 13083995 # ITB inst hits +system.cpu.itb.inst_misses 12083 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -98,121 +98,121 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2600 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2591 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3112 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13091335 # ITB inst accesses -system.cpu.itb.hits 13079160 # DTB hits -system.cpu.itb.misses 12175 # DTB misses -system.cpu.itb.accesses 13091335 # DTB accesses -system.cpu.numCycles 475963827 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13096078 # ITB inst accesses +system.cpu.itb.hits 13083995 # DTB hits +system.cpu.itb.misses 12083 # DTB misses +system.cpu.itb.accesses 13096078 # DTB accesses +system.cpu.numCycles 475967538 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits +system.cpu.BPredUnit.lookups 15172784 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12163693 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783478 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10392072 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8320250 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454874 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82640 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31374160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100930999 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15172784 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9775124 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22189039 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5936170 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131560 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97680943 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 99805 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208737 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 364 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13080141 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1016234 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6355 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155765235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799529 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166844 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 784165 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155765235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031878 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.212054 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33515539 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97301422 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20013824 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1028268 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3906182 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022458 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174763 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117645711 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 578390 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3906182 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35614317 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37590587 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53594123 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18875472 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6184554 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110140296 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21341 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4143290 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32170 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114983026 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504387694 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504296628 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91066 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78733405 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36249620 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891466 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797109 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12509806 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21006076 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13841580 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1961226 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2453000 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100941360 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057614 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126221061 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189445 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24437015 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65086313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513058 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155765235 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110569920 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13988875 8.98% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7307591 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6076063 3.90% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12752921 8.19% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2780626 1.79% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1679008 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 481895 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128336 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155765235 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57759 0.65% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available @@ -241,13 +241,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370724 94.64% 95.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416242 4.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59912166 47.47% 47.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95497 0.08% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued @@ -260,10 +260,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued @@ -271,365 +271,365 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53392141 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12455427 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued -system.cpu.iq.rate 0.265193 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126221061 # Type of FU issued +system.cpu.iq.rate 0.265188 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844727 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070073 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417312910 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127452442 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87180232 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23310 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12552 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134689743 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12379 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 626582 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5289586 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7312 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30140 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2042757 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106883 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1034668 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3906182 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28670725 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 450645 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103223935 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233802 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21006076 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13841580 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466072 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114504 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3680 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30140 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409816 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293009 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 702825 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122971529 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52416599 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3249532 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 225525 # number of nop insts executed -system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed -system.cpu.iew.exec_branches 11734992 # Number of branches executed -system.cpu.iew.exec_stores 12321310 # Number of stores executed -system.cpu.iew.exec_rate 0.258373 # Inst execution rate -system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47712496 # num instructions producing a value -system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value +system.cpu.iew.exec_nop 224961 # number of nop insts executed +system.cpu.iew.exec_refs 64739842 # number of memory reference insts executed +system.cpu.iew.exec_branches 11733959 # Number of branches executed +system.cpu.iew.exec_stores 12323243 # Number of stores executed +system.cpu.iew.exec_rate 0.258361 # Inst execution rate +system.cpu.iew.wb_sent 121621677 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87190526 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47712664 # num instructions producing a value +system.cpu.iew.wb_consumers 88871095 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183186 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536875 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24296365 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544556 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 611758 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151941485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.495079 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124150656 81.71% 81.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13572481 8.93% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3978264 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132059 1.40% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949397 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 999089 0.66% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1584839 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727042 0.48% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2847658 1.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60749034 # Number of instructions committed -system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151941485 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749175 # Number of instructions committed +system.cpu.commit.committedOps 78097811 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27515291 # Number of memory references committed -system.cpu.commit.loads 15716471 # Number of loads committed +system.cpu.commit.refs 27515313 # Number of memory references committed +system.cpu.commit.loads 15716490 # Number of loads committed system.cpu.commit.membars 413125 # Number of memory barriers committed -system.cpu.commit.branches 10023270 # Number of branches committed +system.cpu.commit.branches 10023277 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69135938 # Number of committed integer instructions. +system.cpu.commit.int_insts 69136099 # Number of committed integer instructions. system.cpu.commit.function_calls 996018 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2849213 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2847658 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249559242 # The number of ROB reads -system.cpu.rob.rob_writes 208759201 # The number of ROB writes -system.cpu.timesIdled 1773088 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320203271 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592410806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60598653 # Number of Instructions Simulated -system.cpu.committedOps 77947265 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60598653 # Number of Instructions Simulated -system.cpu.cpi 7.854363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.854363 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127318 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127318 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556742712 # number of integer regfile reads -system.cpu.int_regfile_writes 89972066 # number of integer regfile writes +system.cpu.rob.rob_reads 249572720 # The number of ROB reads +system.cpu.rob.rob_writes 208783952 # The number of ROB writes +system.cpu.timesIdled 1774345 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320202303 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592403923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60598794 # Number of Instructions Simulated +system.cpu.committedOps 77947430 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60598794 # Number of Instructions Simulated +system.cpu.cpi 7.854406 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.854406 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556725625 # number of integer regfile reads +system.cpu.int_regfile_writes 89967060 # number of integer regfile writes system.cpu.fp_regfile_reads 8371 # number of floating regfile reads -system.cpu.fp_regfile_writes 2922 # number of floating regfile writes -system.cpu.misc_regfile_reads 133101437 # number of misc regfile reads -system.cpu.misc_regfile_writes 912914 # number of misc regfile writes -system.cpu.icache.replacements 989669 # number of replacements -system.cpu.icache.tagsinuse 511.593818 # Cycle average of tags in use -system.cpu.icache.total_refs 12001618 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990181 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.120630 # Average number of references to valid blocks. +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 133111894 # number of misc regfile reads +system.cpu.misc_regfile_writes 912902 # number of misc regfile writes +system.cpu.icache.replacements 989535 # number of replacements +system.cpu.icache.tagsinuse 511.594104 # Cycle average of tags in use +system.cpu.icache.total_refs 12006884 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990047 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.127590 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.593818 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.594104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12001618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12001618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12001618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12001618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12001618 # number of overall hits -system.cpu.icache.overall_hits::total 12001618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1073577 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1073577 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1073577 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1073577 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1073577 # number of overall misses -system.cpu.icache.overall_misses::total 1073577 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14108104991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14108104991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14108104991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14108104991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14108104991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14108104991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13075195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13075195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13075195 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13075195 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13075195 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13075195 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082108 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082108 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082108 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082108 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082108 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082108 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13141.213896 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13141.213896 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13141.213896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13141.213896 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13142.418162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13142.418162 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7993.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.244068 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 83043 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 83043 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990082 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 990082 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 990082 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 990082 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 990082 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 990082 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11447874492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11447874492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11447874492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11447874492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11447874492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11447874492 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075733 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075733 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075733 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.113822 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.113822 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.113822 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.113822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.113822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.113822 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075694 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075694 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075694 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.551882 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.551882 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645165 # number of replacements +system.cpu.dcache.replacements 645234 # number of replacements system.cpu.dcache.tagsinuse 511.991712 # Cycle average of tags in use -system.cpu.dcache.total_refs 21796404 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645677 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.757442 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21791132 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645746 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.745671 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13934718 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13934718 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7288473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7288473 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 284342 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 284342 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285730 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285730 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21223191 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21223191 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21223191 # number of overall hits -system.cpu.dcache.overall_hits::total 21223191 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 726725 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 726725 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962478 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962478 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13561 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13561 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 370500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 370500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113614881737 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113614881737 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113614881737 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113614881737 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14661443 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14661443 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297903 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297903 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24912394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24912394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24912394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24912394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049567 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049567 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288995 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288995 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148087 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148087 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148087 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148087 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12985.481441 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12985.481441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35165.833379 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35165.833379 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13320.551582 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13320.551582 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30796.592580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30796.592580 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12775922 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7850000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2526 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5057.768013 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27738.515901 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13929737 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13929737 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7288383 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7288383 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284164 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284164 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21218120 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21218120 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21218120 # number of overall hits +system.cpu.dcache.overall_hits::total 21218120 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 727325 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 727325 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962578 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13599 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3689903 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3689903 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3689903 # number of overall misses +system.cpu.dcache.overall_misses::total 3689903 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441506500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9441506500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104195765238 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104195765238 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181224000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181224000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 305500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113637271738 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113637271738 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113637271738 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113637271738 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14657062 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14657062 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250961 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250961 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297763 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297763 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285742 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285742 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24908023 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24908023 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24908023 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24908023 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049623 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049623 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289005 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289005 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045671 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045671 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000049 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000049 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148141 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148141 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12981.138418 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12981.138418 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35170.640313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35170.640313 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.273991 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.273991 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21821.428571 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21821.428571 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30796.818165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30796.818165 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25623 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15683 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2532 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.119668 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.211470 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609206 # number of writebacks -system.cpu.dcache.writebacks::total 609206 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339325 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 339325 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713436 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713436 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1355 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1355 # 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number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636442 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636442 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636442 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636442 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4757620458 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4757620458 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8541364957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8541364957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141415500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141415500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 332500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 332500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13298985415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13298985415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13298985415 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13298985415 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407548000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407548000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41944273253 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41944273253 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224351821253 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224351821253 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026423 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026423 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040973 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040973 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025547 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12280.899479 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12280.899479 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.885493 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34296.885493 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11585.736523 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11585.736523 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609265 # number of writebacks +system.cpu.dcache.writebacks::total 609265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339927 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 339927 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713517 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713517 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1356 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1356 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3053444 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3053444 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3053444 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3053444 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387398 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387398 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249061 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249061 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12243 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12243 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636459 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636459 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636459 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636459 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4758834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4758834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8540298916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8540298916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141913000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141913000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13299132916 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13299132916 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13299132916 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13299132916 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407357500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407357500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42045203371 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42045203371 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224452560871 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224452560871 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024296 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024296 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000049 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000049 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025552 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025552 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12284.095426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12284.095426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.988862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.988862 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11591.358327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11591.358327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19821.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19821.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -637,149 +637,149 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64397 # number of replacements -system.cpu.l2cache.tagsinuse 51351.941492 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1929097 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129792 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.862988 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2499029961500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36885.832563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 46.221263 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64402 # number of replacements +system.cpu.l2cache.tagsinuse 51349.814622 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1928941 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129796 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.861329 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2499028808000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36883.442332 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 42.609278 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5793337496 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6302064496 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730274500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735566500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32529244761 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730210500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735502500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32612370999 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32612370999 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199259519261 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199264811261 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026667 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985863 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985863 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541185 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541185 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090356 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090356 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199342581499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199347873499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015539 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986806 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986806 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541036 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541036 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090316 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090316 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41054.524670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40455.603435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40776.100499 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.926255 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.817791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40457.094439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40770.241468 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.942407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.942407 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40256.545723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40256.545723 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40255.737727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40255.737727 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -914,16 +914,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307054297856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307054297856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307562103462 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307562103462 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88032 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 978d3ed52..908c82993 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125295 # Number of seconds simulated -sim_ticks 5125295451000 # Number of ticks simulated -final_tick 5125295451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133289 # Number of seconds simulated +sim_ticks 5133289198000 # Number of ticks simulated +final_tick 5133289198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133696 # Simulator instruction rate (inst/s) -host_op_rate 264282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1679641336 # Simulator tick rate (ticks/s) -host_mem_usage 368820 # Number of bytes of host memory used -host_seconds 3051.42 # Real time elapsed on the host -sim_insts 407963822 # Number of instructions simulated -sim_ops 806434654 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2463488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory +host_inst_rate 170996 # Simulator instruction rate (inst/s) +host_op_rate 338013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2151657827 # Simulator tick rate (ticks/s) +host_mem_usage 361992 # Number of bytes of host memory used +host_seconds 2385.74 # Real time elapsed on the host +sim_insts 407952579 # Number of instructions simulated +sim_ops 806410876 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2466560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1076608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10836416 # Number of bytes read from this memory -system.physmem.bytes_read::total 14379776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1076608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1076608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9553280 # Number of bytes written to this memory -system.physmem.bytes_written::total 9553280 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1078720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10839424 # Number of bytes read from this memory +system.physmem.bytes_read::total 14387648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1078720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1078720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9551232 # Number of bytes written to this memory +system.physmem.bytes_written::total 9551232 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38540 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 39 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16822 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169319 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224684 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149270 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149270 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 480653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 549 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169366 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224807 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149238 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149238 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 480503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 486 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2114301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2805648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1863947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1863947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1863947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 480653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2111594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2802813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210142 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210142 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1860646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1860646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1860646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 480503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2114301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4669595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 210142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2111594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4663458 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 47577 # number of replacements -system.iocache.tagsinuse 0.091712 # Cycle average of tags in use +system.iocache.tagsinuse 0.116486 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.091712 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.005732 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.005732 # Average percentage of cache occupancy +system.iocache.occ_blocks::pc.south_bridge.ide 0.116486 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007280 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007280 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -63,14 +63,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47632 system.iocache.demand_misses::total 47632 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses system.iocache.overall_misses::total 47632 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138301932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 138301932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9924152160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9924152160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10062454092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10062454092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10062454092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10062454092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138482932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 138482932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9931610160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9931610160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10070093092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10070093092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10070093092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10070093092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -87,19 +87,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151646.855263 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 151646.855263 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212417.640411 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 212417.640411 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 211254.074824 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 211254.074824 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 71289012 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151845.320175 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 151845.320175 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212577.272260 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 212577.272260 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 211414.450202 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 211414.450202 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 71516 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8825 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8861 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8078.075014 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.070872 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -113,14 +113,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90847000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90847000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7494384978 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7494384978 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7585231978 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7585231978 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91058932 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 91058932 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7502170160 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7502170160 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7593229092 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7593229092 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -129,14 +129,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99612.938596 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 99612.938596 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160410.637372 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 160410.637372 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99845.320175 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 99845.320175 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160577.272260 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 160577.272260 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -150,141 +150,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 448616710 # number of cpu cycles simulated +system.cpu.numCycles 448600431 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86513922 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86513922 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1185612 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81821696 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79447101 # Number of BTB hits +system.cpu.BPredUnit.lookups 86509944 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86509944 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1185802 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81830934 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79445705 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27982708 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427301680 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86513922 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79447101 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164025545 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5056665 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 120243 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63002299 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 57009 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9269960 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 518545 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3708 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 259058563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.256074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.417846 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27983612 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427293864 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86509944 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79445705 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164022517 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5056605 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 118707 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62987614 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36438 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 56602 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9268852 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 518204 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3676 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 259039385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.256241 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.417856 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95463641 36.85% 36.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1593246 0.62% 37.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71955070 27.78% 65.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 970468 0.37% 65.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1621274 0.63% 66.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2451045 0.95% 67.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1124441 0.43% 67.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1422902 0.55% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82456476 31.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95447322 36.85% 36.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1594478 0.62% 37.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71953209 27.78% 65.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 971457 0.38% 65.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1620147 0.63% 66.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2451072 0.95% 67.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1123457 0.43% 67.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1423255 0.55% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82454988 31.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 259058563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192846 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952487 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31703593 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60473195 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159750936 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3297057 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3833782 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840221922 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1208 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3833782 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34472569 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37379630 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10860587 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159949927 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12562068 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836350803 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21427 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5922094 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4820401 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7659 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998159477 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816297556 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816296596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 960 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964421570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33737900 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 466538 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473424 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28941579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17313500 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10257423 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1154419 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 952791 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829902104 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256068 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824407567 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167070 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23703242 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36101298 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203347 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 259058563 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.182321 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.385461 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 259039385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192844 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.952504 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31701157 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60460157 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159747770 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3296725 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3833576 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840199157 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1214 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3833576 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34469655 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37373675 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10858241 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159947646 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12556592 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836331491 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21404 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5918645 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4820353 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7887 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998118157 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816257155 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816256355 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 800 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964383755 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33734395 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 466799 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 473697 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28937943 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17313250 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10261817 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1158356 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 954062 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829878064 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1256439 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824382236 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167222 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23705426 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36106397 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 203573 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 259039385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.182459 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.385421 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72075437 27.82% 27.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15729256 6.07% 33.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10360511 4.00% 37.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7565386 2.92% 40.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75947592 29.32% 70.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3904357 1.51% 71.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72537575 28.00% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 784064 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 154385 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72064876 27.82% 27.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15723846 6.07% 33.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10360482 4.00% 37.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7566572 2.92% 40.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75946167 29.32% 70.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3904049 1.51% 71.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72535410 28.00% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 783527 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 154456 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 259058563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 259039385 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 356821 33.57% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553408 52.07% 85.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152587 14.36% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 355366 33.47% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553588 52.14% 85.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152800 14.39% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 305253 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796599749 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 305432 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796570576 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -313,246 +313,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18032887 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9469678 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18033245 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9472983 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824407567 # Type of FU issued -system.cpu.iq.rate 1.837666 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1062816 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001289 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1909237330 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854871180 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819733271 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 242 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 64 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825165021 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1650397 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824382236 # Type of FU issued +system.cpu.iq.rate 1.837676 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1061754 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001288 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1909166354 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854849744 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819707401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 374 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 65 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825138441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1650685 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3332196 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26785 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11385 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1841480 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3332850 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26850 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11358 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1844760 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932351 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11661 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932315 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11695 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3833782 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26055488 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2116129 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831158172 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342184 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17313500 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10257423 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725671 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1616608 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15691 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11385 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 710592 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 622404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1332996 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822394271 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17607905 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2013295 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3833576 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26046353 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2116686 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831134503 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342849 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17313250 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10261817 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 725973 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1616805 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16237 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11358 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 710415 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 622755 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1333170 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822369106 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17608498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2013129 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26830923 # number of memory reference insts executed -system.cpu.iew.exec_branches 83287562 # Number of branches executed -system.cpu.iew.exec_stores 9223018 # Number of stores executed -system.cpu.iew.exec_rate 1.833178 # Inst execution rate -system.cpu.iew.wb_sent 821886032 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819733335 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640537929 # num instructions producing a value -system.cpu.iew.wb_consumers 1046481965 # num instructions consuming a value +system.cpu.iew.exec_refs 26834247 # number of memory reference insts executed +system.cpu.iew.exec_branches 83283502 # Number of branches executed +system.cpu.iew.exec_stores 9225749 # Number of stores executed +system.cpu.iew.exec_rate 1.833188 # Inst execution rate +system.cpu.iew.wb_sent 821860005 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819707466 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640500741 # num instructions producing a value +system.cpu.iew.wb_consumers 1046431080 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.827247 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612087 # average fanout of values written-back +system.cpu.iew.wb_rate 1.827255 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612081 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24617298 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052719 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1189640 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255240182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.159513 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.852385 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24617133 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052864 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1189777 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255221218 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.159655 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.852368 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83212701 32.60% 32.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11927297 4.67% 37.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4018442 1.57% 38.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74971615 29.37% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2476707 0.97% 69.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1494205 0.59% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1000959 0.39% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70934027 27.79% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5204229 2.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83203030 32.60% 32.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11920052 4.67% 37.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4017826 1.57% 38.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74972744 29.38% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2476508 0.97% 69.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1494072 0.59% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1000652 0.39% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70934036 27.79% 97.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5202298 2.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255240182 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407963822 # Number of instructions committed -system.cpu.commit.committedOps 806434654 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255221218 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407952579 # Number of instructions committed +system.cpu.commit.committedOps 806410876 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22397244 # Number of memory references committed -system.cpu.commit.loads 13981301 # Number of loads committed -system.cpu.commit.membars 473469 # Number of memory barriers committed -system.cpu.commit.branches 82197284 # Number of branches committed +system.cpu.commit.refs 22397454 # Number of memory references committed +system.cpu.commit.loads 13980397 # Number of loads committed +system.cpu.commit.membars 473477 # Number of memory barriers committed +system.cpu.commit.branches 82193415 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735369790 # Number of committed integer instructions. +system.cpu.commit.int_insts 735346024 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5204229 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5202298 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1081009655 # The number of ROB reads -system.cpu.rob.rob_writes 1665958243 # The number of ROB writes -system.cpu.timesIdled 1218536 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 189558147 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9801971615 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407963822 # Number of Instructions Simulated -system.cpu.committedOps 806434654 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407963822 # Number of Instructions Simulated -system.cpu.cpi 1.099648 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.099648 # CPI: Total CPI of All Threads -system.cpu.ipc 0.909382 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.909382 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508373932 # number of integer regfile reads -system.cpu.int_regfile_writes 977906784 # number of integer regfile writes -system.cpu.fp_regfile_reads 64 # number of floating regfile reads -system.cpu.misc_regfile_reads 265175533 # number of misc regfile reads -system.cpu.misc_regfile_writes 402332 # number of misc regfile writes -system.cpu.icache.replacements 1068558 # number of replacements -system.cpu.icache.tagsinuse 510.894483 # Cycle average of tags in use -system.cpu.icache.total_refs 8130546 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1069070 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.605251 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1080968615 # The number of ROB reads +system.cpu.rob.rob_writes 1665910047 # The number of ROB writes +system.cpu.timesIdled 1218526 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189561046 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9817975385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407952579 # Number of Instructions Simulated +system.cpu.committedOps 806410876 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407952579 # Number of Instructions Simulated +system.cpu.cpi 1.099639 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.099639 # CPI: Total CPI of All Threads +system.cpu.ipc 0.909390 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.909390 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508324148 # number of integer regfile reads +system.cpu.int_regfile_writes 977861305 # number of integer regfile writes +system.cpu.fp_regfile_reads 65 # number of floating regfile reads +system.cpu.misc_regfile_reads 265169626 # number of misc regfile reads +system.cpu.misc_regfile_writes 402500 # number of misc regfile writes +system.cpu.icache.replacements 1068646 # number of replacements +system.cpu.icache.tagsinuse 510.896112 # Cycle average of tags in use +system.cpu.icache.total_refs 8129454 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1069158 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.603604 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.894483 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997841 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997841 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8130546 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8130546 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8130546 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8130546 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8130546 # number of overall hits -system.cpu.icache.overall_hits::total 8130546 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1139410 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1139410 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1139410 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1139410 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1139410 # number of overall misses -system.cpu.icache.overall_misses::total 1139410 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15243937992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15243937992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15243937992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15243937992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15243937992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15243937992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9269956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9269956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9269956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9269956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9269956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9269956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13378.799547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13378.799547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13378.799547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13378.799547 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2477494 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.896112 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997844 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997844 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8129454 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8129454 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8129454 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8129454 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8129454 # number of overall hits +system.cpu.icache.overall_hits::total 8129454 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1139394 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1139394 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1139394 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1139394 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1139394 # number of overall misses +system.cpu.icache.overall_misses::total 1139394 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15246811490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15246811490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15246811490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15246811490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15246811490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15246811490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9268848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9268848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9268848 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9268848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9268848 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9268848 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122927 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122927 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122927 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122927 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122927 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122927 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13381.509373 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13381.509373 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13381.509373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13381.509373 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5114 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9753.913386 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.519084 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68152 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68152 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68152 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68152 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68152 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68152 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071258 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1071258 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1071258 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1071258 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1071258 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1071258 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12539776496 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12539776496 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12539776496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12539776496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12539776496 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12539776496 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115562 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115562 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115562 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11705.654937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11705.654937 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68044 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68044 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68044 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68044 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68044 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68044 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071350 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1071350 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1071350 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1071350 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1071350 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1071350 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12542463990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12542463990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12542463990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12542463990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12542463990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12542463990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115586 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115586 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115586 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11707.158249 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11707.158249 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9803 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.028064 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 28000 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9816 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.852486 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5098956249000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028064 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376754 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376754 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28010 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 28010 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9707 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.043772 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 27693 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9719 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.849367 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5100157918000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.043772 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377736 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.377736 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27843 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 27843 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28013 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 28013 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28013 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 28013 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10692 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10692 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10692 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10692 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10692 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10692 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117857500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117857500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117857500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 117857500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117857500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 117857500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38702 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38702 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27846 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 27846 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27846 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 27846 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10592 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10592 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10592 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10592 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10592 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10592 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116124000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116124000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116124000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 116124000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116124000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 116124000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38435 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38435 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38705 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 38705 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38705 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 38705 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.276265 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.276265 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.276243 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.276243 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.276243 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.276243 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11022.961092 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11022.961092 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11022.961092 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38438 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38438 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38438 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38438 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275582 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275582 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275561 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.275561 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275561 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.275561 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10963.368580 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10963.368580 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10963.368580 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10963.368580 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,78 +561,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1616 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1616 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10692 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10692 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10692 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10692 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10692 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10692 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96471005 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96471005 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96471005 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96471005 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96471005 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96471005 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.276265 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.276265 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.276243 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.276243 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9022.727740 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1540 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1540 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10592 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10592 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10592 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10592 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10592 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10592 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94940000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94940000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94940000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94940000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94940000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94940000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275582 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275582 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275561 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275561 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8963.368580 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109091 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 11.986906 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 138731 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109107 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.271513 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.replacements 107637 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 11.991971 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 139374 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 107653 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.294660 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.986906 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749182 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.749182 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138731 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 138731 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138731 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 138731 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138731 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 138731 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110113 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110113 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110113 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110113 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110113 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110113 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1378090500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1378090500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1378090500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1378090500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1378090500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1378090500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248844 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 248844 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248844 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 248844 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248844 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 248844 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442498 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442498 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442498 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442498 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442498 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442498 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12515.238891 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12515.238891 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12515.238891 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.991971 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749498 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.749498 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139374 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 139374 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139374 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 139374 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139374 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 139374 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108671 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 108671 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108671 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 108671 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108671 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 108671 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1362724500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1362724500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1362724500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1362724500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1362724500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1362724500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248045 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 248045 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248045 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 248045 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248045 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 248045 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.438110 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.438110 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.438110 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.438110 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.438110 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.438110 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12539.909451 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12539.909451 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12539.909451 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12539.909451 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,146 +641,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 32856 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 32856 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110113 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110113 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110113 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110113 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110113 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110113 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1157860508 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1157860508 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1157860508 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442498 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442498 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442498 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.202637 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 32720 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 32720 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108671 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108671 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108671 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 108671 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108671 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 108671 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1145382500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1145382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1145382500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.438110 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.438110 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.438110 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10539.909451 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673200 # number of replacements -system.cpu.dcache.tagsinuse 511.995281 # Cycle average of tags in use -system.cpu.dcache.total_refs 19218602 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673712 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.482622 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1673658 # number of replacements +system.cpu.dcache.tagsinuse 511.992942 # Cycle average of tags in use +system.cpu.dcache.total_refs 19220297 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1674170 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.480493 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 32836000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995281 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11125713 # 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number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2589199 # number of overall misses -system.cpu.dcache.overall_misses::total 2589199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31735107000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31735107000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9818389991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9818389991 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41553496991 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41553496991 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41553496991 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41553496991 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13395986 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13395986 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8406710 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8406710 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21802696 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21802696 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21802696 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21802696 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169474 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037937 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037937 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118756 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118756 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118756 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118756 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13978.542228 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13978.542228 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30785.793541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30785.793541 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16048.784582 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16048.784582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16048.784582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16048.784582 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 182917491 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.992942 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11126575 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11126575 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8088656 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8088656 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19215231 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19215231 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19215231 # number of overall hits +system.cpu.dcache.overall_hits::total 19215231 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2269640 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2269640 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 319173 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 319173 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2588813 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2588813 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2588813 # number of overall misses +system.cpu.dcache.overall_misses::total 2588813 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31726602500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31726602500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9823121491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9823121491 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41549723991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41549723991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41549723991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41549723991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13396215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13396215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8407829 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8407829 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21804044 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21804044 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21804044 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21804044 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169424 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169424 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037961 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037961 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13978.693758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13978.693758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30776.793435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30776.793435 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16049.720081 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16049.720081 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 366322 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42914 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42954 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4262.419979 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.528240 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1573634 # number of writebacks -system.cpu.dcache.writebacks::total 1573634 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885029 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 885029 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26052 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 26052 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 911081 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 911081 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 911081 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 911081 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1385244 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1385244 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292874 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 292874 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1678118 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1678118 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1678118 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1678118 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17081753038 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17081753038 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8984344493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8984344493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26066097531 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26066097531 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26066097531 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26066097531 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296526000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296526000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469883000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469883000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766409000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766409000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034838 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034838 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076968 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076968 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076968 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076968 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12331.223263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12331.223263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30676.483720 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30676.483720 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15532.934830 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15532.934830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15532.934830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15532.934830 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1573837 # number of writebacks +system.cpu.dcache.writebacks::total 1573837 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 884183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26057 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26057 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 910240 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 910240 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 910240 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 910240 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1385457 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1385457 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293116 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 293116 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1678573 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1678573 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1678573 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1678573 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17084942000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17084942000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8988357491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8988357491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26073299491 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26073299491 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26073299491 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26073299491 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296962500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296962500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470375500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470375500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767338000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767338000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103422 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103422 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034862 # 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average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -788,141 +788,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915453 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000429 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015736 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16855 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 170305 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 187206 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1582000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 689639500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1541128498 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2232636998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 144031499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 144031499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5333340000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5333340000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1582000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689639500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6874468498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7565976998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1582000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689639500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6874468498 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7565976998 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185727000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185727000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304773500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304773500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91490500500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91490500500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026838 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021090 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916284 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916284 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.065591 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000429 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015736 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.065631 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.065591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40908.274819 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41477.165630 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41298.990909 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40126.674107 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40126.674107 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40055.554304 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40055.554304 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40908.274819 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40365.637059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40414.434725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40908.274819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40365.637059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40414.434725 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.065631 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40916.018985 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41479.477257 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41303.061659 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40120.194708 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40120.194708 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40054.824973 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40054.824973 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 80abd3d9c..e69de29bb 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,133 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.116889 # Number of seconds simulated -sim_ticks 2233777512 # Number of ticks simulated -final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 3140005 # Simulator instruction rate (inst/s) -host_op_rate 3141240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3147745 # Simulator tick rate (ticks/s) -host_mem_usage 511524 # Number of bytes of host memory used -host_seconds 709.64 # Real time elapsed on the host -sim_insts 2228284650 # Number of instructions simulated -sim_ops 2229160714 # Number of ops (including micro ops) simulated -system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory -system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory -system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s) -system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory -system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory -system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory -system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory -system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s) -system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory -system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory -system.rom.bytes_read::total 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory -system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory -system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory -system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory -system.rom.num_reads::total 195123 # Number of read requests responded to by this memory -system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory -system.nvram.bytes_read::total 284 # Number of bytes read from this memory -system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory -system.nvram.bytes_written::total 92 # Number of bytes written to this memory -system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory -system.nvram.num_reads::total 284 # Number of read requests responded to by this memory -system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory -system.nvram.num_writes::total 92 # Number of write requests responded to by this memory -system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory -system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory -system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory -system.physmem.num_other::total 14 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory -system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory -system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory -system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory -system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory -system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory -system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory -system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory -system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory -system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory -system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory -system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory -system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s) -system.cpu.numCycles 2233777513 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2228284650 # Number of instructions committed -system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses -system.cpu.num_func_calls 44037246 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls -system.cpu.num_int_insts 1839325658 # number of integer instructions -system.cpu.num_fp_insts 14608322 # number of float instructions -system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read -system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read -system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written -system.cpu.num_mem_refs 547951940 # number of memory refs -system.cpu.num_load_insts 349807670 # Number of load instructions -system.cpu.num_store_insts 198144270 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2233777513 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- |