diff options
Diffstat (limited to 'tests/long/fs')
23 files changed, 6365 insertions, 6389 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index bf1bde417..1c28eff64 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -941,7 +941,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.tsunami.pciconfig.pio master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma @@ -1003,7 +1003,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port[0] slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -1060,7 +1060,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 94dc81bdc..11f244941 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:47:55 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 11:07:21 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 106801000 -Exiting @ tick 1896395899500 because m5_exit instruction encountered +info: Launching CPU 1 @ 112168000 +Exiting @ tick 1900530800500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 0c462a770..3f76d2026 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.896396 # Number of seconds simulated -sim_ticks 1896395899500 # Number of ticks simulated -final_tick 1896395899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.900531 # Number of seconds simulated +sim_ticks 1900530800500 # Number of ticks simulated +final_tick 1900530800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196112 # Simulator instruction rate (inst/s) -host_op_rate 196112 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6628227410 # Simulator tick rate (ticks/s) -host_mem_usage 302056 # Number of bytes of host memory used -host_seconds 286.11 # Real time elapsed on the host -sim_insts 56109524 # Number of instructions simulated -sim_ops 56109524 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 881728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24808704 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 99648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 472640 # Number of bytes read from this memory -system.physmem.bytes_read::total 28913408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 881728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 99648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7865856 # Number of bytes written to this memory -system.physmem.bytes_written::total 7865856 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387636 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7385 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451772 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122904 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122904 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 464949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13082028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1397750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 249231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15246504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 464949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4147792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4147792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4147792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 464949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13082028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 249231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19394296 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 344859 # number of replacements -system.l2c.tagsinuse 65321.127934 # Cycle average of tags in use -system.l2c.total_refs 2609636 # Total number of references to valid blocks. -system.l2c.sampled_refs 410035 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.364423 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6312493000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53767.491128 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5338.607060 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6047.920982 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 140.590955 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 26.517809 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820427 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.081461 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.092284 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002145 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000405 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996721 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 978177 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 784326 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 102747 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 33274 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1898524 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 832872 # number of Writeback hits -system.l2c.Writeback_hits::total 832872 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 159 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 200 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 175658 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 7994 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183652 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 978177 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 959984 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 102747 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 41268 # number of demand (read+write) hits -system.l2c.demand_hits::total 2082176 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 978177 # number of overall hits -system.l2c.overall_hits::cpu0.data 959984 # number of overall hits -system.l2c.overall_hits::cpu1.inst 102747 # number of overall hits -system.l2c.overall_hits::cpu1.data 41268 # number of overall hits -system.l2c.overall_hits::total 2082176 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13779 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273160 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1574 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 765 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289278 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2448 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 557 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3005 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 42 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 122 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114897 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6716 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121613 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13779 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 388057 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1574 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 7481 # number of demand (read+write) misses -system.l2c.demand_misses::total 410891 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13779 # number of overall misses -system.l2c.overall_misses::cpu0.data 388057 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1574 # number of overall misses -system.l2c.overall_misses::cpu1.data 7481 # number of overall misses -system.l2c.overall_misses::total 410891 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 720793500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14208419500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 82364000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 41213000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15052790000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2256000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1409000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 3665000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 419000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 157000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 576000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6027292500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 352112000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6379404500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 720793500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20235712000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 82364000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 393325000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21432194500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 720793500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20235712000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 82364000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 393325000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21432194500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 991956 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1057486 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 104321 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 34039 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2187802 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 832872 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832872 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2607 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 598 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3205 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 71 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 102 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 173 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 290555 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 14710 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305265 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 991956 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1348041 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 104321 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 48749 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2493067 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 991956 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1348041 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 104321 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 48749 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2493067 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013891 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.258311 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015088 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.022474 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.132223 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.939010 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.931438 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.937598 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.591549 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.784314 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.705202 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.395440 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.456560 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.398385 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013891 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.287867 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015088 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.153460 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.164813 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013891 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.287867 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015088 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.153460 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.164813 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52311.016765 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52015.007688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52327.827192 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53873.202614 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52035.723422 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 921.568627 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2529.622980 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1219.633943 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9976.190476 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1962.500000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4721.311475 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52458.223452 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52428.826683 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52456.600035 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52311.016765 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52146.236249 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52327.827192 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52576.527202 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52160.291902 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52311.016765 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52146.236249 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52327.827192 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52576.527202 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52160.291902 # average overall miss latency +host_inst_rate 119697 # Simulator instruction rate (inst/s) +host_op_rate 119697 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3968630665 # Simulator tick rate (ticks/s) +host_mem_usage 303044 # Number of bytes of host memory used +host_seconds 478.89 # Real time elapsed on the host +sim_insts 57321719 # Number of instructions simulated +sim_ops 57321719 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 875648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24657536 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 107456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 693056 # Number of bytes read from this memory +system.physmem.bytes_read::total 28984512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 875648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 107456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 983104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7921792 # Number of bytes written to this memory +system.physmem.bytes_written::total 7921792 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385274 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10829 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452883 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123778 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123778 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 460739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12974026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1394777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 364664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15250746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 460739 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56540 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4168200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4168200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4168200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 460739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12974026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1394777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 364664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19418945 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 345959 # number of replacements +system.l2c.tagsinuse 65264.030293 # Cycle average of tags in use +system.l2c.total_refs 2564962 # Total number of references to valid blocks. +system.l2c.sampled_refs 411131 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.238795 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6370050000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53566.099176 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5313.179425 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6099.564968 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 209.813021 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 75.373703 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.817354 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.081073 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.093072 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.003201 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001150 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.995850 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 777532 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 689515 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 314287 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 100987 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1882321 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 806312 # number of Writeback hits +system.l2c.Writeback_hits::total 806312 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 440 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 616 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 81 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 128023 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 44351 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172374 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 777532 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 817538 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 314287 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 145338 # number of demand (read+write) hits +system.l2c.demand_hits::total 2054695 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 777532 # number of overall hits +system.l2c.overall_hits::cpu0.data 817538 # number of overall hits +system.l2c.overall_hits::cpu1.inst 314287 # number of overall hits +system.l2c.overall_hits::cpu1.data 145338 # number of overall hits +system.l2c.overall_hits::total 2054695 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13684 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272967 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1696 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 861 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289208 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2867 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1568 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4435 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 726 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 747 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1473 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113091 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 10063 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 123154 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13684 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 386058 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1696 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10924 # number of demand (read+write) misses +system.l2c.demand_misses::total 412362 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13684 # number of overall misses +system.l2c.overall_misses::cpu0.data 386058 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1696 # number of overall misses +system.l2c.overall_misses::cpu1.data 10924 # number of overall misses +system.l2c.overall_misses::total 412362 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 728665998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14214168999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 90803000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 47077499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15080715496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 19661414 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 22245414 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2793000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3107000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6061091997 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 549004499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6610096496 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 728665998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20275260996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 90803000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 596081998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21690811992 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 728665998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20275260996 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 90803000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 596081998 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21690811992 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 791216 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 962482 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 315983 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 101848 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2171529 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 806312 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 806312 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3043 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2008 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5051 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 777 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 777 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1554 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 241114 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 54414 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295528 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 791216 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1203596 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 315983 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 156262 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2467057 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 791216 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1203596 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 315983 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 156262 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2467057 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.017295 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.283607 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.005367 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.008454 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.133182 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942162 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780876 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.878044 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934363 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.961390 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.947876 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469035 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.184934 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.416725 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.017295 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.320754 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005367 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.069908 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.167147 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.017295 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.320754 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005367 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.069908 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.167147 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53249.488308 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.847630 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53539.504717 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 54677.699187 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52144.876684 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 901.290548 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12539.167092 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5015.876888 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3847.107438 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 420.348059 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2109.300747 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.821843 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54556.742423 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53673.421050 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52601.384201 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52601.384201 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,8 +221,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81384 # number of writebacks -system.l2c.writebacks::total 81384 # number of writebacks +system.l2c.writebacks::writebacks 82258 # number of writebacks +system.l2c.writebacks::total 82258 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits @@ -232,111 +232,111 @@ system.l2c.demand_mshr_hits::total 18 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13778 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273160 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1557 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 765 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289260 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2448 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 557 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3005 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 42 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 80 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 122 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114897 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6716 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121613 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13778 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 388057 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1557 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 7481 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 410873 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13778 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 388057 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1557 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 7481 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 410873 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 552060500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10929358000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 62432500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 31914000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11575765000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97983500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22281000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 120264500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1681500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 4881500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4629799500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 270393000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4900192500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 552060500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15559157500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 62432500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 302307000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16475957500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 552060500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15559157500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 62432500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 302307000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16475957500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 821481000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16663000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 838144000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1131946998 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 287746500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1419693498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1953427998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 304409500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 2257837498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013890 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.258311 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014925 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022474 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.132215 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.939010 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.931438 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.937598 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.591549 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784314 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.705202 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.395440 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.456560 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.398385 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013890 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.287867 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014925 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.153460 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.164806 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013890 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.287867 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014925 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.153460 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.164806 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40068.260996 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40010.828818 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40097.944766 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41717.647059 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.547328 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40025.939542 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.795332 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40021.464226 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.714286 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13683 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272967 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1679 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 861 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289190 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2867 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1568 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4435 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 726 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 747 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1473 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 113091 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 10063 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 123154 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13683 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 386058 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1679 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10924 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 412344 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13683 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 386058 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1679 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10924 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 412344 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561385998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10939069000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69521500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 36634000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11606610498 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 114796000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 62749500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 177545500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29087500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 29880000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 58967500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4695316997 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 427005999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5122322996 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 561385998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15634385997 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 69521500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 463639999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16728933494 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 561385998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15634385997 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 69521500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 463639999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16728933494 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 820941530 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16650000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 837591530 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1194248500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 359420000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1553668500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2015190030 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 376070000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 2391260030 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.283607 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008454 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133173 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942162 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780876 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.878044 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934363 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961390 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.947876 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.469035 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.184934 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.416725 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.167140 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.167140 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.694011 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42548.199768 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40134.895736 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.460412 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.813776 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.807215 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.426997 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40012.295082 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40295.216585 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40261.018463 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.328016 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40068.260996 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40095.031142 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40097.944766 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40409.971929 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40099.878795 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40068.260996 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40095.031142 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40097.944766 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40409.971929 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40099.878795 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.247115 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.042965 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42433.270297 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41592.826835 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -347,39 +347,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.462803 # Cycle average of tags in use +system.iocache.replacements 41698 # number of replacements +system.iocache.tagsinuse 0.465240 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708345741000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.462803 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.028925 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.028925 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses -system.iocache.ReadReq_misses::total 177 # number of ReadReq misses +system.iocache.warmup_cycle 1711281170000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.465240 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.029077 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses -system.iocache.demand_misses::total 41729 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses -system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20390998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20390998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5719191806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5719191806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5739582804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5739582804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5739582804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5739582804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21238998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21238998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7637775806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7637775806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7659014804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7659014804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7659014804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7659014804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115203.378531 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115203.378531 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137639.386937 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137639.386937 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137544.221141 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137544.221141 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64663068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119320.213483 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183812.471265 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183812.471265 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183537.378481 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183537.378481 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7710000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7151 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6183.711198 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1078.170885 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11186998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11186998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3558333000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3558333000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3569519998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3569519998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3569519998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3569519998 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11982000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11982000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476916000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5476916000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5488898000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5488898000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5488898000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5488898000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63203.378531 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63203.378531 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85635.661340 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85635.661340 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9453856 # DTB read hits -system.cpu0.dtb.read_misses 36184 # DTB read misses -system.cpu0.dtb.read_acv 571 # DTB read access violations -system.cpu0.dtb.read_accesses 675976 # DTB read accesses -system.cpu0.dtb.write_hits 6300368 # DTB write hits -system.cpu0.dtb.write_misses 8347 # DTB write misses -system.cpu0.dtb.write_acv 346 # DTB write access violations -system.cpu0.dtb.write_accesses 234133 # DTB write accesses -system.cpu0.dtb.data_hits 15754224 # DTB hits -system.cpu0.dtb.data_misses 44531 # DTB misses -system.cpu0.dtb.data_acv 917 # DTB access violations -system.cpu0.dtb.data_accesses 910109 # DTB accesses -system.cpu0.itb.fetch_hits 1108660 # ITB hits -system.cpu0.itb.fetch_misses 28136 # ITB misses -system.cpu0.itb.fetch_acv 1047 # ITB acv -system.cpu0.itb.fetch_accesses 1136796 # ITB accesses +system.cpu0.dtb.read_hits 8334313 # DTB read hits +system.cpu0.dtb.read_misses 29661 # DTB read misses +system.cpu0.dtb.read_acv 416 # DTB read access violations +system.cpu0.dtb.read_accesses 650050 # DTB read accesses +system.cpu0.dtb.write_hits 5360515 # DTB write hits +system.cpu0.dtb.write_misses 6017 # DTB write misses +system.cpu0.dtb.write_acv 275 # DTB write access violations +system.cpu0.dtb.write_accesses 211537 # DTB write accesses +system.cpu0.dtb.data_hits 13694828 # DTB hits +system.cpu0.dtb.data_misses 35678 # DTB misses +system.cpu0.dtb.data_acv 691 # DTB access violations +system.cpu0.dtb.data_accesses 861587 # DTB accesses +system.cpu0.itb.fetch_hits 972456 # ITB hits +system.cpu0.itb.fetch_misses 29747 # ITB misses +system.cpu0.itb.fetch_acv 802 # ITB acv +system.cpu0.itb.fetch_accesses 1002203 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,279 +483,279 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 111705884 # number of cpu cycles simulated +system.cpu0.numCycles 107494535 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13423445 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11229595 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 405618 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9732141 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5644182 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11769770 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9862090 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 345528 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8388023 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5075121 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 889528 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 35792 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28347650 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 67883922 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13423445 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6533710 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12779049 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1882893 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34959873 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 30735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 200156 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 304542 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 145 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8317299 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 264993 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 77847394 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.872013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.211541 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 768289 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 29261 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 25151812 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60423976 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11769770 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5843410 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11477495 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1678868 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36441754 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 35468 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 189532 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 310248 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 196 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7504127 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 232204 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 74712100 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.808758 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.135218 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 65068345 83.58% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 840291 1.08% 84.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1663244 2.14% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 773630 0.99% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2654406 3.41% 91.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 587924 0.76% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 633021 0.81% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 971381 1.25% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4655152 5.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63234605 84.64% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 741221 0.99% 85.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1559530 2.09% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686170 0.92% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2492076 3.34% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 531561 0.71% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 568906 0.76% 93.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 718608 0.96% 94.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4179423 5.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77847394 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.120168 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.607702 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29292805 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34750406 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11695757 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 922620 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1185805 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 575553 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 39816 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 66717094 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 118720 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1185805 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30365496 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12492089 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18756431 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10933791 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4113780 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 63191653 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6630 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 474971 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1473898 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 42180100 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 76536527 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 76096983 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 439544 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36808161 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5371931 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1596682 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238140 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11595704 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9967009 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6589337 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1245862 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 818929 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55970736 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2008418 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54697537 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 108647 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6579388 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3235320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1364468 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77847394 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.702625 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.358580 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 74712100 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109492 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.562112 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26235752 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36073897 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10433111 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 896014 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1073325 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 504398 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32602 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 59387121 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 93497 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1073325 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27172169 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15317742 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17291837 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9793019 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4064006 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56407383 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7139 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 656540 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1492805 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 37953017 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 68861567 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 68508934 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 352633 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33050954 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4902063 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1333181 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 200244 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10589201 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8773580 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5638577 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132250 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 738910 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50116652 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1669804 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 48856794 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 108488 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5944129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3041029 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1132337 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 74712100 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.653934 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.297915 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53933184 69.28% 69.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10617760 13.64% 82.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4942911 6.35% 89.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3320001 4.26% 93.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2532609 3.25% 96.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1408678 1.81% 98.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 686959 0.88% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 303964 0.39% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 101328 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52667189 70.49% 70.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10185163 13.63% 84.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4563652 6.11% 90.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2983683 3.99% 94.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2257783 3.02% 97.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1142078 1.53% 98.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 582516 0.78% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 283628 0.38% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 46408 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77847394 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74712100 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 87681 11.80% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 349168 46.97% 58.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 306477 41.23% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 73121 11.93% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 287582 46.92% 58.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 252262 41.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3778 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37484034 68.53% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60241 0.11% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 16826 0.03% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9867065 18.04% 86.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6373328 11.65% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 890382 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 4467 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 33934109 69.46% 69.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 53582 0.11% 69.58% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.58% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16546 0.03% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8675974 17.76% 87.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5426955 11.11% 98.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 742930 1.52% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54697537 # Type of FU issued -system.cpu0.iq.rate 0.489657 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 743326 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013590 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 187461216 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 64264846 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53535096 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 633224 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 306465 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 298013 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55105300 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 331785 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 567631 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 48856794 # Type of FU issued +system.cpu0.iq.rate 0.454505 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 612965 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012546 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 172645923 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57499135 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 47860626 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 501218 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 243758 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 236014 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 49202996 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 262296 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 518056 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1269870 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3726 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13071 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 496722 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1116510 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2510 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12661 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 476371 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18808 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 143577 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18849 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 94368 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1185805 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8725439 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 608869 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61441844 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 619329 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9967009 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6589337 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1767664 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 482033 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 12133 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13071 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 215254 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 393579 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 608833 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54218225 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9516523 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 479311 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1073325 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10798667 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 779958 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 54837290 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 559703 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8773580 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5638577 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1469305 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 544312 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 8344 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12661 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186183 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 327984 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 514167 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 48431427 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8385093 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 425367 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3462690 # number of nop insts executed -system.cpu0.iew.exec_refs 15839640 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8639850 # Number of branches executed -system.cpu0.iew.exec_stores 6323117 # Number of stores executed -system.cpu0.iew.exec_rate 0.485366 # Inst execution rate -system.cpu0.iew.wb_sent 53937806 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53833109 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26624302 # num instructions producing a value -system.cpu0.iew.wb_consumers 35973761 # num instructions consuming a value +system.cpu0.iew.exec_nop 3050834 # number of nop insts executed +system.cpu0.iew.exec_refs 13764236 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7758760 # Number of branches executed +system.cpu0.iew.exec_stores 5379143 # Number of stores executed +system.cpu0.iew.exec_rate 0.450548 # Inst execution rate +system.cpu0.iew.wb_sent 48183951 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48096640 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24100280 # num instructions producing a value +system.cpu0.iew.wb_consumers 32401803 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.481918 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.740103 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.447433 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743794 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 54183968 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 54183968 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 7167159 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 643950 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 567683 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76661589 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.706794 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.627118 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 48294177 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 48294177 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6449436 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 537467 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 480768 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 73638775 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.655825 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560295 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56437400 73.62% 73.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8432395 11.00% 84.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4492859 5.86% 90.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2495159 3.25% 93.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1450592 1.89% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 646072 0.84% 96.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 460772 0.60% 97.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 487702 0.64% 97.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1758638 2.29% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55222738 74.99% 74.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7735232 10.50% 85.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4278280 5.81% 91.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2283958 3.10% 94.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1242509 1.69% 96.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 524248 0.71% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 435052 0.59% 97.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 385141 0.52% 97.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1531617 2.08% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76661589 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 54183968 # Number of instructions committed -system.cpu0.commit.committedOps 54183968 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 73638775 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48294177 # Number of instructions committed +system.cpu0.commit.committedOps 48294177 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14789754 # Number of memory references committed -system.cpu0.commit.loads 8697139 # Number of loads committed -system.cpu0.commit.membars 219715 # Number of memory barriers committed -system.cpu0.commit.branches 8176675 # Number of branches committed -system.cpu0.commit.fp_insts 295518 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 50137398 # Number of committed integer instructions. -system.cpu0.commit.function_calls 709743 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1758638 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12819276 # Number of memory references committed +system.cpu0.commit.loads 7657070 # Number of loads committed +system.cpu0.commit.membars 181890 # Number of memory barriers committed +system.cpu0.commit.branches 7325526 # Number of branches committed +system.cpu0.commit.fp_insts 233448 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 44748110 # Number of committed integer instructions. +system.cpu0.commit.function_calls 610965 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1531617 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 136054419 # The number of ROB reads -system.cpu0.rob.rob_writes 123888625 # The number of ROB writes -system.cpu0.timesIdled 1249831 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33858490 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3681079567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 51051860 # Number of Instructions Simulated -system.cpu0.committedOps 51051860 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 51051860 # Number of Instructions Simulated -system.cpu0.cpi 2.188086 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.188086 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.457020 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.457020 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71111535 # number of integer regfile reads -system.cpu0.int_regfile_writes 38857328 # number of integer regfile writes -system.cpu0.fp_regfile_reads 146185 # number of floating regfile reads -system.cpu0.fp_regfile_writes 148692 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1886112 # number of misc regfile reads -system.cpu0.misc_regfile_writes 899559 # number of misc regfile writes +system.cpu0.rob.rob_reads 126666255 # The number of ROB reads +system.cpu0.rob.rob_writes 110560293 # The number of ROB writes +system.cpu0.timesIdled 1221795 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32782435 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693291566 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 45532520 # Number of Instructions Simulated +system.cpu0.committedOps 45532520 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 45532520 # Number of Instructions Simulated +system.cpu0.cpi 2.360830 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.360830 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.423580 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.423580 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 63860317 # number of integer regfile reads +system.cpu0.int_regfile_writes 34945795 # number of integer regfile writes +system.cpu0.fp_regfile_reads 117013 # number of floating regfile reads +system.cpu0.fp_regfile_writes 117648 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1550179 # number of misc regfile reads +system.cpu0.misc_regfile_writes 750147 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -787,247 +787,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 991395 # number of replacements -system.cpu0.icache.tagsinuse 510.024196 # Cycle average of tags in use -system.cpu0.icache.total_refs 7272203 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 991905 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.331552 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23165696000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.024196 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996141 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996141 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7272203 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7272203 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7272203 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7272203 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7272203 # number of overall hits -system.cpu0.icache.overall_hits::total 7272203 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1045096 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1045096 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1045096 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1045096 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1045096 # number of overall misses -system.cpu0.icache.overall_misses::total 1045096 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15554108994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 15554108994 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 15554108994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 15554108994 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 15554108994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 15554108994 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8317299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8317299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8317299 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8317299 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8317299 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8317299 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125653 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125653 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125653 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125653 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125653 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125653 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14882.947590 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14882.947590 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14882.947590 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14882.947590 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1419995 # number of cycles access was blocked +system.cpu0.icache.replacements 790628 # number of replacements +system.cpu0.icache.tagsinuse 510.000717 # Cycle average of tags in use +system.cpu0.icache.total_refs 6669453 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 791140 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.430180 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23654486000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.000717 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996095 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996095 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6669453 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6669453 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6669453 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6669453 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6669453 # number of overall hits +system.cpu0.icache.overall_hits::total 6669453 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 834673 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 834673 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 834673 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 834673 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 834673 # number of overall misses +system.cpu0.icache.overall_misses::total 834673 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13767352493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13767352493 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13767352493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13767352493 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13767352493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13767352493 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7504126 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7504126 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7504126 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7504126 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7504126 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7504126 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111229 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111229 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111229 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111229 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111229 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111229 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16494.306744 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16494.306744 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1480996 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11007.713178 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 9141.950617 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 253 # number of writebacks -system.cpu0.icache.writebacks::total 253 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53062 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 53062 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 53062 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 53062 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 53062 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 53062 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 992034 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 992034 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 992034 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 992034 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 992034 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 992034 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11805368995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11805368995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11805368995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11805368995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11805368995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11805368995 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119274 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.119274 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.119274 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11900.165715 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 247 # number of writebacks +system.cpu0.icache.writebacks::total 247 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43336 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43336 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43336 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43336 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43336 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43336 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791337 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 791337 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 791337 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 791337 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 791337 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 791337 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10689365997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10689365997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10689365997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10689365997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10689365997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10689365997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105454 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105454 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1352160 # number of replacements -system.cpu0.dcache.tagsinuse 506.886378 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11309312 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1352672 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.360720 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 19277000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.886378 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.990012 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.990012 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6911324 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6911324 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3997215 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3997215 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 183850 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 183850 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 210761 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 210761 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10908539 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10908539 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10908539 # number of overall hits -system.cpu0.dcache.overall_hits::total 10908539 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1709932 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1709932 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1869031 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1869031 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22271 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22271 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 641 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 641 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3578963 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3578963 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3578963 # number of overall misses -system.cpu0.dcache.overall_misses::total 3578963 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36329127500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36329127500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 56639435392 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 56639435392 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326225500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 326225500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5918000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5918000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 92968562892 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 92968562892 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 92968562892 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 92968562892 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8621256 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8621256 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5866246 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5866246 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 206121 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 206121 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211402 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 211402 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14487502 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14487502 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14487502 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14487502 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198339 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.198339 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318608 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.318608 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.108048 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.108048 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003032 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003032 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247038 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.247038 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247038 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.247038 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21245.948669 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21245.948669 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30304.171195 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30304.171195 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.995151 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.995151 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9232.449298 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9232.449298 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25976.396764 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25976.396764 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 790531306 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 99401 # number of cycles access was blocked +system.cpu0.dcache.replacements 1206208 # number of replacements +system.cpu0.dcache.tagsinuse 505.878050 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9822290 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1206649 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.140139 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 19675000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.878050 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.988043 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.988043 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6113680 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6113680 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3377171 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3377171 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150549 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 150549 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171656 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171656 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9490851 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9490851 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9490851 # number of overall hits +system.cpu0.dcache.overall_hits::total 9490851 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1478314 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1478314 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1593619 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1593619 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18637 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18637 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4699 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4699 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3071933 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3071933 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3071933 # number of overall misses +system.cpu0.dcache.overall_misses::total 3071933 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41272950000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41272950000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65317405497 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 65317405497 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315155000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 315155000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68652000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 68652000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 106590355497 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 106590355497 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 106590355497 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 106590355497 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591994 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7591994 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970790 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4970790 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169186 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 169186 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176355 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 176355 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12562784 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12562784 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12562784 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12562784 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194720 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.194720 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320597 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.320597 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110157 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110157 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026645 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026645 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244526 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.244526 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244526 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.244526 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.933325 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.933325 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40986.839073 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40986.839073 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16910.178677 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16910.178677 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14609.917004 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14609.917004 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34698.138109 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34698.138109 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 716537144 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 65430 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7952.951238 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10951.201956 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 805259 # number of writebacks -system.cpu0.dcache.writebacks::total 805259 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 661851 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 661851 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1575507 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1575507 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5029 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5029 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2237358 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2237358 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2237358 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2237358 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1048081 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1048081 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 293524 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 293524 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17242 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17242 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1341605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1341605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1341605 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1341605 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23566810500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23566810500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8456840306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8456840306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195574000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195574000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3991500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3991500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32023650806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 32023650806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32023650806 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 32023650806 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 917307000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 917307000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253595498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253595498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2170902498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2170902498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121569 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121569 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050036 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050036 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083650 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083650 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092604 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092604 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22485.676680 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22485.676680 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28811.409990 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28811.409990 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11342.883656 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.883656 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6236.718750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6236.718750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 693284 # number of writebacks +system.cpu0.dcache.writebacks::total 693284 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515563 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 515563 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344321 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1344321 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3732 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3732 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1859884 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1859884 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1859884 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1859884 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962751 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 962751 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249298 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249298 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14905 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14905 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4699 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4699 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212049 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1212049 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212049 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1212049 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25942792600 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25942792600 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8699231964 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8699231964 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186934001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186934001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 54037501 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 54037501 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34642024564 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34642024564 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34642024564 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34642024564 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918343000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918343000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327727998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327727998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246070998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246070998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126811 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126811 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050153 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050153 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088098 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088098 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026645 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026645 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096479 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096479 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34894.912771 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.697484 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.697484 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11499.787402 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11499.787402 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1039,22 +1039,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1211336 # DTB read hits -system.cpu1.dtb.read_misses 9865 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 283619 # DTB read accesses -system.cpu1.dtb.write_hits 674221 # DTB write hits -system.cpu1.dtb.write_misses 1908 # DTB write misses -system.cpu1.dtb.write_acv 40 # DTB write access violations -system.cpu1.dtb.write_accesses 107232 # DTB write accesses -system.cpu1.dtb.data_hits 1885557 # DTB hits -system.cpu1.dtb.data_misses 11773 # DTB misses -system.cpu1.dtb.data_acv 46 # DTB access violations -system.cpu1.dtb.data_accesses 390851 # DTB accesses -system.cpu1.itb.fetch_hits 332989 # ITB hits -system.cpu1.itb.fetch_misses 6158 # ITB misses -system.cpu1.itb.fetch_acv 143 # ITB acv -system.cpu1.itb.fetch_accesses 339147 # ITB accesses +system.cpu1.dtb.read_hits 2499316 # DTB read hits +system.cpu1.dtb.read_misses 12569 # DTB read misses +system.cpu1.dtb.read_acv 105 # DTB read access violations +system.cpu1.dtb.read_accesses 313735 # DTB read accesses +system.cpu1.dtb.write_hits 1734639 # DTB write hits +system.cpu1.dtb.write_misses 3525 # DTB write misses +system.cpu1.dtb.write_acv 140 # DTB write access violations +system.cpu1.dtb.write_accesses 132367 # DTB write accesses +system.cpu1.dtb.data_hits 4233955 # DTB hits +system.cpu1.dtb.data_misses 16094 # DTB misses +system.cpu1.dtb.data_acv 245 # DTB access violations +system.cpu1.dtb.data_accesses 446102 # DTB accesses +system.cpu1.itb.fetch_hits 489806 # ITB hits +system.cpu1.itb.fetch_misses 8851 # ITB misses +system.cpu1.itb.fetch_acv 360 # ITB acv +system.cpu1.itb.fetch_accesses 498657 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1067,520 +1067,520 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 8872891 # number of cpu cycles simulated +system.cpu1.numCycles 22717311 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1582523 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1301899 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 53959 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 749480 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 495600 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3442703 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2849702 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 108899 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2361843 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1192387 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 108561 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5012 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3100077 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 7469135 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1582523 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 604161 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1348473 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 293042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3524434 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 23987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 56676 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47433 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 951392 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 34043 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 8293149 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.900639 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.276932 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 236332 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 10679 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 9037199 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 16321027 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3442703 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1428719 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2924126 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 526603 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 8306285 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 28121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 87140 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 64229 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1963514 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 75345 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 20778311 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.785484 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.154367 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 6944676 83.74% 83.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 71085 0.86% 84.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 161786 1.95% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 117935 1.42% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 195029 2.35% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 79896 0.96% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 91030 1.10% 92.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 58799 0.71% 93.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 572913 6.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 17854185 85.93% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 203613 0.98% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 301133 1.45% 88.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 225724 1.09% 89.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 404540 1.95% 91.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151692 0.73% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 164507 0.79% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 309022 1.49% 94.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1163895 5.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 8293149 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.178355 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.841793 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3156648 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 3626684 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1266182 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 55854 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 187780 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 69682 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4376 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 7275177 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13096 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 187780 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3279437 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 303001 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 2955129 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1188563 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 379237 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 6712088 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 36332 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 73621 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 4503320 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 8147567 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 8100022 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 47545 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3660294 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 843026 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 283944 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 19782 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1166048 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1294582 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 736122 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 125256 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 86989 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 5902743 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 293921 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 5640439 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22605 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1087589 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 606184 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 224688 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 8293149 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.680132 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.353961 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 20778311 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.151545 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.718440 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8812255 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8762880 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2709089 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 172906 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 321180 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 151088 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 10133 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 16020033 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 29351 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 321180 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 9094333 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 882455 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6951469 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2594850 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 934022 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 14843152 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 114 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 83650 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 279958 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 9660007 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 17630674 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 17422680 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 207994 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 8331005 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1328994 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 594043 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 64597 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2775458 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2641121 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1825529 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 246953 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 159017 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12975245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 664400 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 12700763 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 35708 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1746535 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 829425 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 468662 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 20778311 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.611251 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.284414 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 5841725 70.44% 70.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1091278 13.16% 83.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 496152 5.98% 89.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 349787 4.22% 93.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 258149 3.11% 96.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 126242 1.52% 98.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 71640 0.86% 99.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 51558 0.62% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 6618 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15115816 72.75% 72.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2653114 12.77% 85.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1112593 5.35% 90.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 724594 3.49% 94.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 603153 2.90% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 287847 1.39% 98.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 182303 0.88% 99.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 88112 0.42% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10779 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 8293149 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 20778311 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3067 2.40% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 73236 57.36% 59.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 51382 40.24% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3869 1.53% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 134765 53.16% 54.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 114892 45.32% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3484656 61.78% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10025 0.18% 62.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8917 0.16% 62.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1261676 22.37% 84.58% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 692210 12.27% 96.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 177678 3.15% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2823 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7927502 62.42% 62.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 20764 0.16% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10543 0.08% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2623377 20.66% 83.35% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1764952 13.90% 97.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 349391 2.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 5640439 # Type of FU issued -system.cpu1.iq.rate 0.635693 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 127685 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.022637 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 19654183 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 7250568 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 5466934 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 70134 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 35039 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 33778 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 5728452 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 36154 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 64737 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 12700763 # Type of FU issued +system.cpu1.iq.rate 0.559079 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 253526 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 46169663 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15243166 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 12341001 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 299407 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 145151 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 140846 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12794667 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 156799 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 115193 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 237812 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 428 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1426 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 105246 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 347930 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 808 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2222 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 153073 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 373 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 23964 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 370 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 11635 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 187780 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 210633 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 9248 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 6437285 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 88203 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1294582 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 736122 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 274301 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 3887 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1426 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 25150 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 66283 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 91433 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 5579037 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1224301 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 61402 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 321180 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 537224 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 73444 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 14366092 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 206312 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2641121 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1825529 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 596088 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 55197 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6016 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2222 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 53937 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 130013 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 183950 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 12579473 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2523314 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 121289 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 240621 # number of nop insts executed -system.cpu1.iew.exec_refs 1903575 # number of memory reference insts executed -system.cpu1.iew.exec_branches 816845 # Number of branches executed -system.cpu1.iew.exec_stores 679274 # Number of stores executed -system.cpu1.iew.exec_rate 0.628773 # Inst execution rate -system.cpu1.iew.wb_sent 5526738 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 5500712 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2655801 # num instructions producing a value -system.cpu1.iew.wb_consumers 3693565 # num instructions consuming a value +system.cpu1.iew.exec_nop 726447 # number of nop insts executed +system.cpu1.iew.exec_refs 4269906 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1887172 # Number of branches executed +system.cpu1.iew.exec_stores 1746592 # Number of stores executed +system.cpu1.iew.exec_rate 0.553740 # Inst execution rate +system.cpu1.iew.wb_sent 12515990 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 12481847 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5700900 # num instructions producing a value +system.cpu1.iew.wb_consumers 8040202 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.619946 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.719035 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.549442 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709049 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5260797 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 5260797 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1110508 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 69233 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 85933 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 8105369 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.649051 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577854 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 12433159 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 12433159 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1857667 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 195738 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 173364 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 20457131 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.607767 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.554530 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6083727 75.06% 75.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 977563 12.06% 87.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 351716 4.34% 91.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 209459 2.58% 94.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 128681 1.59% 95.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 67803 0.84% 96.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 72265 0.89% 97.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 49144 0.61% 97.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 165011 2.04% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 15844350 77.45% 77.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2122437 10.38% 87.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 810532 3.96% 91.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 497134 2.43% 94.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 362445 1.77% 95.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 133722 0.65% 96.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 129038 0.63% 97.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 154146 0.75% 98.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 403327 1.97% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 8105369 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5260797 # Number of instructions committed -system.cpu1.commit.committedOps 5260797 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 20457131 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 12433159 # Number of instructions committed +system.cpu1.commit.committedOps 12433159 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1687646 # Number of memory references committed -system.cpu1.commit.loads 1056770 # Number of loads committed -system.cpu1.commit.membars 18284 # Number of memory barriers committed -system.cpu1.commit.branches 746127 # Number of branches committed -system.cpu1.commit.fp_insts 32538 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 4917553 # Number of committed integer instructions. -system.cpu1.commit.function_calls 83297 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 165011 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3965647 # Number of memory references committed +system.cpu1.commit.loads 2293191 # Number of loads committed +system.cpu1.commit.membars 64658 # Number of memory barriers committed +system.cpu1.commit.branches 1777478 # Number of branches committed +system.cpu1.commit.fp_insts 139699 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 11488003 # Number of committed integer instructions. +system.cpu1.commit.function_calls 194670 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 403327 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 14229924 # The number of ROB reads -system.cpu1.rob.rob_writes 12929135 # The number of ROB writes -system.cpu1.timesIdled 74630 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 579742 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3783284242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5057664 # Number of Instructions Simulated -system.cpu1.committedOps 5057664 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5057664 # Number of Instructions Simulated -system.cpu1.cpi 1.754346 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.754346 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.570013 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.570013 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 7235777 # number of integer regfile reads -system.cpu1.int_regfile_writes 3986410 # number of integer regfile writes -system.cpu1.fp_regfile_reads 21879 # number of floating regfile reads -system.cpu1.fp_regfile_writes 20613 # number of floating regfile writes -system.cpu1.misc_regfile_reads 262487 # number of misc regfile reads -system.cpu1.misc_regfile_writes 123180 # number of misc regfile writes -system.cpu1.icache.replacements 103776 # number of replacements -system.cpu1.icache.tagsinuse 452.422972 # Cycle average of tags in use -system.cpu1.icache.total_refs 841895 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 104287 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.072866 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1873827117000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 452.422972 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.883639 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.883639 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 841895 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 841895 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 841895 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 841895 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 841895 # number of overall hits -system.cpu1.icache.overall_hits::total 841895 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 109497 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 109497 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 109497 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 109497 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 109497 # number of overall misses -system.cpu1.icache.overall_misses::total 109497 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1632285999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1632285999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1632285999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1632285999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1632285999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1632285999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 951392 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 951392 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 951392 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 951392 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 951392 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 951392 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115091 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.115091 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115091 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.115091 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115091 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.115091 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14907.129867 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14907.129867 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14907.129867 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14907.129867 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 108999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 34238592 # The number of ROB reads +system.cpu1.rob.rob_writes 28901418 # The number of ROB writes +system.cpu1.timesIdled 230949 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1939000 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3778341690 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11789199 # Number of Instructions Simulated +system.cpu1.committedOps 11789199 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 11789199 # Number of Instructions Simulated +system.cpu1.cpi 1.926960 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.926960 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.518952 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.518952 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 16196586 # number of integer regfile reads +system.cpu1.int_regfile_writes 8796247 # number of integer regfile writes +system.cpu1.fp_regfile_reads 73611 # number of floating regfile reads +system.cpu1.fp_regfile_writes 74214 # number of floating regfile writes +system.cpu1.misc_regfile_reads 699711 # number of misc regfile reads +system.cpu1.misc_regfile_writes 299448 # number of misc regfile writes +system.cpu1.icache.replacements 315447 # number of replacements +system.cpu1.icache.tagsinuse 471.003081 # Cycle average of tags in use +system.cpu1.icache.total_refs 1635327 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 315959 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.175757 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1877367216000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 471.003081 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919928 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919928 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1635327 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1635327 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1635327 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1635327 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1635327 # number of overall hits +system.cpu1.icache.overall_hits::total 1635327 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 328187 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 328187 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 328187 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 328187 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 328187 # number of overall misses +system.cpu1.icache.overall_misses::total 328187 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323842998 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5323842998 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5323842998 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5323842998 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5323842998 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5323842998 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1963514 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1963514 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1963514 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1963514 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1963514 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1963514 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167143 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.167143 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167143 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.167143 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167143 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.167143 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 16221.980145 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 16221.980145 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 228998 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7266.600000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6189.135135 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 39 # number of writebacks -system.cpu1.icache.writebacks::total 39 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5150 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 5150 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 5150 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 5150 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 5150 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 5150 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 104347 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 104347 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 104347 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 104347 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 104347 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 104347 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1240890499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1240890499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1240890499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1240890499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1240890499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1240890499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.109678 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.109678 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.109678 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11891.961427 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 38 # number of writebacks +system.cpu1.icache.writebacks::total 38 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12173 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12173 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12173 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12173 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12173 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12173 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316014 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316014 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316014 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316014 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316014 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316014 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183208998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183208998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183208998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4183208998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183208998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4183208998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.160943 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.160943 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.160943 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 49122 # number of replacements -system.cpu1.dcache.tagsinuse 427.490507 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1549420 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 49435 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 31.342571 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1873347092000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 427.490507 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.834942 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.834942 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1023689 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1023689 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 507974 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 507974 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 14665 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 14665 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 12767 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 12767 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1531663 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1531663 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1531663 # number of overall hits -system.cpu1.dcache.overall_hits::total 1531663 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 89035 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 89035 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 104470 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 104470 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1314 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1314 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 680 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 680 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 193505 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 193505 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 193505 # number of overall misses -system.cpu1.dcache.overall_misses::total 193505 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1323211000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1323211000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3353600320 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3353600320 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 16083500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 16083500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7995500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 7995500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4676811320 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4676811320 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4676811320 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4676811320 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1112724 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1112724 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 612444 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 612444 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 15979 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 15979 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 13447 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 13447 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1725168 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1725168 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1725168 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1725168 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.080015 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.080015 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.170579 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.170579 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082233 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082233 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050569 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050569 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.112166 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.112166 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.112166 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.112166 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14861.694839 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14861.694839 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32101.084713 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32101.084713 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12240.106545 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12240.106545 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11758.088235 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11758.088235 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24168.943025 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24168.943025 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 52059498 # number of cycles access was blocked +system.cpu1.dcache.replacements 159076 # number of replacements +system.cpu1.dcache.tagsinuse 488.854290 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3388834 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 159588 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 21.234892 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 42819944000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 488.854290 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.954794 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.954794 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2022458 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2022458 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1251052 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1251052 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49972 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 49972 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48601 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 48601 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3273510 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3273510 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3273510 # number of overall hits +system.cpu1.dcache.overall_hits::total 3273510 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 307183 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 307183 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 360837 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 360837 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8700 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8700 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5048 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5048 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 668020 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 668020 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 668020 # number of overall misses +system.cpu1.dcache.overall_misses::total 668020 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6372115000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6372115000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11323925707 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11323925707 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121529000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 121529000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68413000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 68413000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 17696040707 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 17696040707 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 17696040707 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 17696040707 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2329641 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2329641 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611889 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1611889 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58672 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 58672 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53649 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 53649 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3941530 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3941530 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3941530 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3941530 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131859 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.131859 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223860 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.223860 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148282 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148282 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094093 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094093 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169482 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.169482 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169482 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.169482 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20743.709776 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20743.709776 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31382.385141 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31382.385141 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13968.850575 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13968.850575 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13552.496038 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13552.496038 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26490.285780 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26490.285780 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 57515988 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 4983 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6825 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10447.420831 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8427.250989 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 27321 # number of writebacks -system.cpu1.dcache.writebacks::total 27321 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 51379 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 51379 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 87869 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 87869 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 246 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 246 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 139248 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 139248 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 139248 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 139248 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37656 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37656 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 16601 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 16601 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 674 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 674 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 54257 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 54257 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 54257 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 54257 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 431650500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 431650500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 497061484 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 497061484 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9472500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9472500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5965000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5965000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 928711984 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 928711984 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 928711984 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 928711984 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18616500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18616500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 318558500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 318558500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 337175000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 337175000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033841 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033841 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027106 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027106 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066838 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066838 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050123 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050123 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031450 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031450 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11462.993945 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11462.993945 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29941.659177 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29941.659177 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8869.382022 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8869.382022 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8850.148368 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8850.148368 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 112743 # number of writebacks +system.cpu1.dcache.writebacks::total 112743 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 196860 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 196860 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298722 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 298722 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1021 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1021 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 495582 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 495582 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 495582 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 495582 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110323 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 110323 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62115 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62115 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7679 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7679 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5048 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5048 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 172438 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 172438 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 172438 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 172438 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1760210564 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1760210564 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471458330 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471458330 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78242000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78242000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52885501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52885501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3231668894 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3231668894 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3231668894 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3231668894 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18623000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18623000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400648500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400648500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419271500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419271500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047356 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047356 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038536 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038536 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130880 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130880 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094093 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094093 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043749 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043749 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15955.064347 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15955.064347 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23689.259116 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23689.259116 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10189.087121 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10189.087121 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10476.525555 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10476.525555 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1589,161 +1589,171 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6349 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 201504 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72229 40.68% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.13% 40.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1919 1.08% 41.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 103147 58.10% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 177538 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70862 49.25% 49.25% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.16% 49.42% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1919 1.33% 50.75% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.75% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70856 49.25% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 143880 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1857798011000 97.96% 97.96% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91384000 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 387547000 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 3124500 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38114922000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1896394988500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981074 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6699 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 167510 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 58590 40.24% 40.24% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 238 0.16% 40.40% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.32% 41.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 340 0.23% 41.96% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 84509 58.04% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 145601 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 57892 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 238 0.20% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.63% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 340 0.29% 51.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 57552 48.80% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 117946 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862592276000 98.01% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96187500 0.01% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 394889000 0.02% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 155178500 0.01% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37157854000 1.96% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900396385000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988087 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.686942 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810418 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed -system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 228 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.681016 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810063 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 5 2.38% 2.38% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.57% 10.95% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.43% 12.38% # number of syscalls executed +system.cpu0.kern.syscall::6 28 13.33% 25.71% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 26.19% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.48% 26.67% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.29% 30.95% # number of syscalls executed +system.cpu0.kern.syscall::19 5 2.38% 33.33% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.90% 35.24% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.95% 36.19% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.90% 38.10% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.33% 41.43% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.95% 42.38% # number of syscalls executed +system.cpu0.kern.syscall::45 35 16.67% 59.05% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.90% 60.95% # number of syscalls executed +system.cpu0.kern.syscall::48 6 2.86% 63.81% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.29% 68.10% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 68.57% # number of syscalls executed +system.cpu0.kern.syscall::59 4 1.90% 70.48% # number of syscalls executed +system.cpu0.kern.syscall::71 32 15.24% 85.71% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.43% 87.14% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.29% 91.43% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 91.90% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.48% 92.38% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.33% 95.71% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.95% 96.67% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.95% 97.62% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.95% 98.57% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.48% 99.05% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 210 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3893 2.09% 2.15% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed -system.cpu0.kern.callpal::swpipl 170509 91.52% 93.70% # number of callpals executed -system.cpu0.kern.callpal::rdps 6338 3.40% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.11% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed -system.cpu0.kern.callpal::rti 4866 2.61% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 386 0.21% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 186310 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7415 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1346 # number of protection mode switches +system.cpu0.kern.callpal::wripir 439 0.29% 0.29% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3076 2.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::tbi 37 0.02% 2.32% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed +system.cpu0.kern.callpal::swpipl 138810 90.43% 92.75% # number of callpals executed +system.cpu0.kern.callpal::rdps 6361 4.14% 96.89% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.89% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.89% # number of callpals executed +system.cpu0.kern.callpal::rdusp 6 0.00% 96.90% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.90% # number of callpals executed +system.cpu0.kern.callpal::rti 4288 2.79% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 327 0.21% 99.90% # number of callpals executed +system.cpu0.kern.callpal::imb 146 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 153507 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6690 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1345 -system.cpu0.kern.mode_good::user 1346 +system.cpu0.kern.mode_good::kernel 1098 +system.cpu0.kern.mode_good::user 1098 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181389 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.164126 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.307157 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1894436238500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1958742000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.281972 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1897963397000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1861803000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3894 # number of times the context was actually changed +system.cpu0.kern.swap_context 3077 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2266 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 36241 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9521 32.62% 32.62% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1918 6.57% 39.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 104 0.36% 39.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17647 60.46% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 29190 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9511 45.42% 45.42% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1918 9.16% 54.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 104 0.50% 55.08% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9407 44.92% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20940 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870201149000 98.64% 98.64% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 342845500 0.02% 98.65% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 41642500 0.00% 98.66% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25494039500 1.34% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1896079676500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998950 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2601 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 74467 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 24565 38.36% 38.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 3.00% 41.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 439 0.69% 42.05% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 37108 57.95% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 64035 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 23886 48.07% 48.07% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 3.87% 51.93% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 439 0.88% 52.82% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 23447 47.18% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 49695 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870827437000 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343518500 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 182737500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29176221000 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900529914000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.972359 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.533065 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.717369 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed -system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed -system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 98 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.631858 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.776060 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 3 2.59% 2.59% # number of syscalls executed +system.cpu1.kern.syscall::3 12 10.34% 12.93% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.86% 13.79% # number of syscalls executed +system.cpu1.kern.syscall::6 14 12.07% 25.86% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.17% 31.03% # number of syscalls executed +system.cpu1.kern.syscall::19 5 4.31% 35.34% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.72% 37.07% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.72% 38.79% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.72% 40.52% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.45% 43.97% # number of syscalls executed +system.cpu1.kern.syscall::45 19 16.38% 60.34% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.72% 62.07% # number of syscalls executed +system.cpu1.kern.syscall::48 4 3.45% 65.52% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.86% 66.38% # number of syscalls executed +system.cpu1.kern.syscall::59 3 2.59% 68.97% # number of syscalls executed +system.cpu1.kern.syscall::71 22 18.97% 87.93% # number of syscalls executed +system.cpu1.kern.syscall::74 7 6.03% 93.97% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.72% 95.69% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.72% 97.41% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.72% 99.14% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.86% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 116 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 334 1.11% 1.14% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.15% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.17% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24745 82.19% 83.36% # number of callpals executed -system.cpu1.kern.callpal::rdps 2407 7.99% 91.36% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.36% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.37% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed -system.cpu1.kern.callpal::rti 2422 8.04% 99.43% # number of callpals executed -system.cpu1.kern.callpal::callsys 129 0.43% 99.86% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.14% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 340 0.51% 0.51% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.51% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.52% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1824 2.74% 3.26% # number of callpals executed +system.cpu1.kern.callpal::tbi 16 0.02% 3.28% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.29% # number of callpals executed +system.cpu1.kern.callpal::swpipl 57992 87.22% 90.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2394 3.60% 94.11% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.11% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.12% # number of callpals executed +system.cpu1.kern.callpal::rdusp 3 0.00% 94.13% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.13% # number of callpals executed +system.cpu1.kern.callpal::rti 3680 5.53% 99.66% # number of callpals executed +system.cpu1.kern.callpal::callsys 188 0.28% 99.95% # number of callpals executed +system.cpu1.kern.callpal::imb 34 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 30107 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 710 # number of protection mode switches -system.cpu1.kern.mode_switch::user 392 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 420 -system.cpu1.kern.mode_good::user 392 -system.cpu1.kern.mode_good::idle 28 -system.cpu1.kern.mode_switch_good::kernel 0.591549 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 66490 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2119 # number of protection mode switches +system.cpu1.kern.mode_switch::user 641 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2717 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 1003 +system.cpu1.kern.mode_good::user 641 +system.cpu1.kern.mode_good::idle 362 +system.cpu1.kern.mode_switch_good::kernel 0.473336 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.013672 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.266667 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1688462500 0.09% 0.09% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 719657500 0.04% 0.13% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893332404000 99.87% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 335 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.133235 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.366259 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 7877043500 0.41% 0.41% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 912149500 0.05% 0.46% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1891740713000 99.54% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1825 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 3ccfd349b..b1df0f096 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -517,7 +517,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.tsunami.pciconfig.pio master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma @@ -579,7 +579,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port[0] slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -636,7 +636,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 3b2f5c4a1..a30a37ba8 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:47:37 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 11:00:25 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858879782500 because m5_exit instruction encountered +Exiting @ tick 1865402113500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 90f62bf97..a9a5c3cb0 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858880 # Number of seconds simulated -sim_ticks 1858879782500 # Number of ticks simulated -final_tick 1858879782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.865402 # Number of seconds simulated +sim_ticks 1865402113500 # Number of ticks simulated +final_tick 1865402113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196297 # Simulator instruction rate (inst/s) -host_op_rate 196297 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6876664069 # Simulator tick rate (ticks/s) -host_mem_usage 298988 # Number of bytes of host memory used -host_seconds 270.32 # Real time elapsed on the host -sim_insts 53062487 # Number of instructions simulated -sim_ops 53062487 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24884032 # Number of bytes read from this memory +host_inst_rate 131129 # Simulator instruction rate (inst/s) +host_op_rate 131129 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4607058697 # Simulator tick rate (ticks/s) +host_mem_usage 298956 # Number of bytes of host memory used +host_seconds 404.90 # Real time elapsed on the host +sim_insts 53094243 # Number of instructions simulated +sim_ops 53094243 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 967424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24877312 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28505408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory -system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388813 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28497024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 967424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516928 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516928 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15116 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388708 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445397 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 521329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13386574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1426821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15334724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 521329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 521329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 521329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13386574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1426821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19382788 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 338457 # number of replacements -system.l2c.tagsinuse 65351.732427 # Cycle average of tags in use -system.l2c.total_refs 2557615 # Total number of references to valid blocks. -system.l2c.sampled_refs 403631 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.336518 # Average number of references to valid blocks. -system.l2c.warmup_cycle 4816079000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53832.150010 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5352.172668 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6167.409749 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.821413 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.081668 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094107 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997188 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 1006386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 826813 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1833199 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 841169 # number of Writeback hits -system.l2c.Writeback_hits::total 841169 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185491 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185491 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 1006386 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1012304 # number of demand (read+write) hits -system.l2c.demand_hits::total 2018690 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 1006386 # number of overall hits -system.l2c.overall_hits::cpu.data 1012304 # number of overall hits -system.l2c.overall_hits::total 2018690 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 273879 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289023 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 27 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 115423 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115423 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 15144 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 389302 # number of demand (read+write) misses -system.l2c.demand_misses::total 404446 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 15144 # number of overall misses -system.l2c.overall_misses::cpu.data 389302 # number of overall misses -system.l2c.overall_misses::total 404446 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 792218000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14246173000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15038391000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 322000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 322000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6056487000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6056487000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 792218000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20302660000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21094878000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 792218000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20302660000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21094878000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 1021530 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1100692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2122222 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 841169 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 841169 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 42 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 42 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 300914 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300914 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 1021530 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1401606 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2423136 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1021530 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1401606 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2423136 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014825 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.248824 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.136189 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.642857 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.642857 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383575 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383575 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014825 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.277754 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.166910 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014825 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.277754 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.166910 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52312.334918 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52016.302820 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52031.814077 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 11925.925926 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 11925.925926 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52472.098282 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52472.098282 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52157.464779 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52157.464779 # average overall miss latency +system.physmem.num_reads::total 445266 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117452 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117452 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13336166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1421832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15276612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4029656 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4029656 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4029656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13336166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1421832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19306267 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 338323 # number of replacements +system.l2c.tagsinuse 65346.781313 # Cycle average of tags in use +system.l2c.total_refs 2566599 # Total number of references to valid blocks. +system.l2c.sampled_refs 403491 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.360982 # Average number of references to valid blocks. +system.l2c.warmup_cycle 4861120000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53937.288272 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5357.413768 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6052.079273 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.823018 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.081748 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.092347 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997113 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1010692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 829338 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1840030 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 843192 # number of Writeback hits +system.l2c.Writeback_hits::total 843192 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 35 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 185767 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 185767 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 1010692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1015105 # number of demand (read+write) hits +system.l2c.demand_hits::total 2025797 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 1010692 # number of overall hits +system.l2c.overall_hits::cpu.data 1015105 # number of overall hits +system.l2c.overall_hits::total 2025797 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 15118 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 273845 # number of ReadReq misses +system.l2c.ReadReq_misses::total 288963 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 49 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 49 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 115352 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115352 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 15118 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 389197 # number of demand (read+write) misses +system.l2c.demand_misses::total 404315 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 15118 # number of overall misses +system.l2c.overall_misses::cpu.data 389197 # number of overall misses +system.l2c.overall_misses::total 404315 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 805739998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14260725000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15066464998 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 501500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 501500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6190534997 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6190534997 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 805739998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20451259997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21256999995 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 805739998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20451259997 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21256999995 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1025810 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1103183 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2128993 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 843192 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 843192 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 301119 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 301119 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 1025810 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1404302 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2430112 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1025810 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1404302 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2430112 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014738 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.248232 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.135728 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.583333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.583333 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383078 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383078 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014738 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.277146 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.166377 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014738 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.277146 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.166377 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53296.732240 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52075.900601 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52139.772213 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 10234.693878 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 10234.693878 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53666.473030 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53666.473030 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52547.321786 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52575.343470 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52547.321786 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52575.343470 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -145,72 +145,72 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 76064 # number of writebacks -system.l2c.writebacks::total 76064 # number of writebacks +system.l2c.writebacks::writebacks 75940 # number of writebacks +system.l2c.writebacks::total 75940 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 273879 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289022 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 115423 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 115423 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 389302 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 404445 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 389302 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 404445 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 606782500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 10958767000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11565549500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1142000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1142000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4653345000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4653345000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 606782500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15612112000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16218894500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 606782500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15612112000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16218894500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810071000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 810071000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114787998 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1114787998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924858998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1924858998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248824 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.136188 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.642857 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.642857 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383575 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383575 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.166910 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.166910 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40070.164432 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40013.170050 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.156210 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42296.296296 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42296.296296 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40315.578351 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40315.578351 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.inst 15117 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 273845 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 288962 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 49 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 49 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 115352 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 115352 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 15117 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 389197 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 404314 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 15117 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 389197 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 404314 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 620965998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10975082500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11596048498 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2065000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 2065000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4796966997 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4796966997 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 620965998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15772049497 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16393015495 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 620965998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15772049497 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16393015495 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810224030 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 810224030 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1103797000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1103797000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1914021030 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1914021030 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248232 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.135727 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.583333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.583333 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383078 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383078 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166377 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166377 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41077.330026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40077.717322 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.011898 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42142.857143 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.468800 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.468800 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -219,14 +219,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.268378 # Cycle average of tags in use +system.iocache.tagsinuse 1.294799 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338896000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.268378 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079274 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079274 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1711277767000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.294799 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.080925 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.080925 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -235,14 +235,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721900806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721900806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741838804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741838804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741838804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741838804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7641897806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7641897806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7662570804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7662570804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7662570804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7662570804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -259,19 +259,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115248.543353 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.582355 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137704.582355 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137611.475231 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137611.475231 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64649068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183911.672266 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183911.672266 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183644.596860 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183644.596860 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7656000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7143 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6171.159603 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1071.818564 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -285,14 +285,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561047996 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3561047996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571989994 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571989994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571989994 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571989994 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5481043992 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5481043992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5492719992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5492719992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5492719992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5492719992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -301,14 +301,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85701.001059 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85701.001059 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131908.066808 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131908.066808 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -326,22 +326,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9957395 # DTB read hits -system.cpu.dtb.read_misses 44300 # DTB read misses -system.cpu.dtb.read_acv 564 # DTB read access violations -system.cpu.dtb.read_accesses 948872 # DTB read accesses -system.cpu.dtb.write_hits 6634412 # DTB write hits -system.cpu.dtb.write_misses 10394 # DTB write misses -system.cpu.dtb.write_acv 384 # DTB write access violations -system.cpu.dtb.write_accesses 338929 # DTB write accesses -system.cpu.dtb.data_hits 16591807 # DTB hits -system.cpu.dtb.data_misses 54694 # DTB misses -system.cpu.dtb.data_acv 948 # DTB access violations -system.cpu.dtb.data_accesses 1287801 # DTB accesses -system.cpu.itb.fetch_hits 1332166 # ITB hits -system.cpu.itb.fetch_misses 40283 # ITB misses -system.cpu.itb.fetch_acv 1114 # ITB acv -system.cpu.itb.fetch_accesses 1372449 # ITB accesses +system.cpu.dtb.read_hits 9972402 # DTB read hits +system.cpu.dtb.read_misses 43929 # DTB read misses +system.cpu.dtb.read_acv 494 # DTB read access violations +system.cpu.dtb.read_accesses 957886 # DTB read accesses +system.cpu.dtb.write_hits 6649938 # DTB write hits +system.cpu.dtb.write_misses 10071 # DTB write misses +system.cpu.dtb.write_acv 391 # DTB write access violations +system.cpu.dtb.write_accesses 340693 # DTB write accesses +system.cpu.dtb.data_hits 16622340 # DTB hits +system.cpu.dtb.data_misses 54000 # DTB misses +system.cpu.dtb.data_acv 885 # DTB access violations +system.cpu.dtb.data_accesses 1298579 # DTB accesses +system.cpu.itb.fetch_hits 1343669 # ITB hits +system.cpu.itb.fetch_misses 37345 # ITB misses +system.cpu.itb.fetch_acv 1146 # ITB acv +system.cpu.itb.fetch_accesses 1381014 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -354,279 +354,279 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 114963877 # number of cpu cycles simulated +system.cpu.numCycles 122571263 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 13985774 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11671873 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 444413 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10112209 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5892039 # Number of BTB hits +system.cpu.BPredUnit.lookups 14075987 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11741614 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 452517 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10126525 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5926302 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 933191 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 42453 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29251616 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71181997 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13985774 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6825230 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13396576 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2069716 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36268090 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 34293 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 258776 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 311439 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 136 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8761444 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 288106 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80878220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.880113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220739 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 942334 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45003 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31564050 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71567580 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14075987 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6868636 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13486844 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2151091 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 41804632 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33708 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 276041 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 314295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 187 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8859322 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 305645 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 88896899 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.805063 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.137281 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67481644 83.44% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 875531 1.08% 84.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1743396 2.16% 86.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 848384 1.05% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2751006 3.40% 91.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 598052 0.74% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 674963 0.83% 92.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011492 1.25% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4893752 6.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75410055 84.83% 84.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 885656 1.00% 85.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1762066 1.98% 87.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 856601 0.96% 88.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2772547 3.12% 91.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 605003 0.68% 92.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 676052 0.76% 93.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1014878 1.14% 94.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4914041 5.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80878220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121654 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.619168 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30302953 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36036206 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12267887 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 956730 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1314443 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 612620 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43298 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69919175 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129721 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1314443 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31429322 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12715444 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19630106 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11479703 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4309200 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66239771 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6813 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505927 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1528052 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44253229 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80320067 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79838854 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 481213 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38235996 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6017225 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1699905 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 247549 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12108783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10535735 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6944708 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1299665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 826518 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58678192 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2085341 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57178934 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 114167 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7323387 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3670404 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1417353 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80878220 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.706976 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.364710 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 88896899 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.114839 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.583885 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32604567 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 41610698 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12250426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1057078 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1374129 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 617310 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43428 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70293890 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 133239 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1374129 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33752767 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16324711 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21058224 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11548980 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4838086 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66572257 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7187 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 753146 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1801877 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44498273 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80714962 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80226097 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 488865 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38261328 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6236937 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1703640 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251709 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12757763 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10570492 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6981683 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1316603 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 922104 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58981346 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2097651 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57326676 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 120953 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7579711 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3887654 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1429592 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 88896899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.644867 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.291957 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55943146 69.17% 69.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11029219 13.64% 82.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5183069 6.41% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3467547 4.29% 93.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2613614 3.23% 96.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1475312 1.82% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 724581 0.90% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331422 0.41% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 110310 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 62967728 70.83% 70.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 12048856 13.55% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5390899 6.06% 90.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3449544 3.88% 94.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2613461 2.94% 97.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1329807 1.50% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 686975 0.77% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 354371 0.40% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 55258 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80878220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 88896899 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90406 11.39% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 375907 47.36% 58.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 327352 41.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 75491 10.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 363771 48.19% 58.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315594 41.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39009688 68.22% 68.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61923 0.11% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10404436 18.20% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6713568 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952795 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39127581 68.25% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61956 0.11% 68.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10418296 18.17% 86.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6729507 11.74% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952802 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57178934 # Type of FU issued -system.cpu.iq.rate 0.497364 # Inst issue rate -system.cpu.iq.fu_busy_cnt 793665 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013880 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195448703 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67761433 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55894957 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 695216 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 339032 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327938 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57602239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363079 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 589978 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57326676 # Type of FU issued +system.cpu.iq.rate 0.467701 # Inst issue rate +system.cpu.iq.fu_busy_cnt 754856 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013168 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 203729346 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68333375 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56036726 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 696713 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 339202 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327718 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57709702 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 364539 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 594776 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1427299 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3440 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13878 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 554882 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1456655 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2870 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14252 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 588832 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 151980 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18348 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 104302 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1314443 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8887747 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 615033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64324837 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 661005 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10535735 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6944708 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1835122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 481853 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16088 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13878 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 240769 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 420658 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 661427 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56655096 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10030988 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 523837 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1374129 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11393417 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 869281 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64652535 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 684492 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10570492 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6981683 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1845589 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 621506 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12714 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14252 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 241539 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 423865 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 665404 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56791406 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10044983 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 535269 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3561304 # number of nop insts executed -system.cpu.iew.exec_refs 16691010 # number of memory reference insts executed -system.cpu.iew.exec_branches 8986521 # Number of branches executed -system.cpu.iew.exec_stores 6660022 # Number of stores executed -system.cpu.iew.exec_rate 0.492808 # Inst execution rate -system.cpu.iew.wb_sent 56341255 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56222895 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27828941 # num instructions producing a value -system.cpu.iew.wb_consumers 37695611 # num instructions consuming a value +system.cpu.iew.exec_nop 3573538 # number of nop insts executed +system.cpu.iew.exec_refs 16720258 # number of memory reference insts executed +system.cpu.iew.exec_branches 9005988 # Number of branches executed +system.cpu.iew.exec_stores 6675275 # Number of stores executed +system.cpu.iew.exec_rate 0.463334 # Inst execution rate +system.cpu.iew.wb_sent 56476627 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56364444 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27797872 # num instructions producing a value +system.cpu.iew.wb_consumers 37663953 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.489048 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738254 # average fanout of values written-back +system.cpu.iew.wb_rate 0.459850 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738050 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56255888 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56255888 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 7955379 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 613263 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79563777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.707054 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.631051 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56288834 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56288834 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 8251602 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 668059 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 621198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 87522770 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.643134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.558246 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58612311 73.67% 73.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8734565 10.98% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4655391 5.85% 90.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2574186 3.24% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1496332 1.88% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 659939 0.83% 96.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 486345 0.61% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 472774 0.59% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1871934 2.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 66254825 75.70% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8962066 10.24% 85.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4828588 5.52% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2603942 2.98% 94.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1449491 1.66% 96.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 603705 0.69% 96.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 515511 0.59% 97.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 488925 0.56% 97.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1815717 2.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79563777 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56255888 # Number of instructions committed -system.cpu.commit.committedOps 56255888 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 87522770 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56288834 # Number of instructions committed +system.cpu.commit.committedOps 56288834 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15498262 # Number of memory references committed -system.cpu.commit.loads 9108436 # Number of loads committed -system.cpu.commit.membars 227920 # Number of memory barriers committed -system.cpu.commit.branches 8459857 # Number of branches committed +system.cpu.commit.refs 15506688 # Number of memory references committed +system.cpu.commit.loads 9113837 # Number of loads committed +system.cpu.commit.membars 227975 # Number of memory barriers committed +system.cpu.commit.branches 8463674 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52095164 # Number of committed integer instructions. -system.cpu.commit.function_calls 744157 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1871934 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52126817 # Number of committed integer instructions. +system.cpu.commit.function_calls 744625 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1815717 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141652037 # The number of ROB reads -system.cpu.rob.rob_writes 129738562 # The number of ROB writes -system.cpu.timesIdled 1269768 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34085657 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3602789251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53062487 # Number of Instructions Simulated -system.cpu.committedOps 53062487 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53062487 # Number of Instructions Simulated -system.cpu.cpi 2.166575 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.166575 # CPI: Total CPI of All Threads -system.cpu.ipc 0.461558 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.461558 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74266984 # number of integer regfile reads -system.cpu.int_regfile_writes 40553865 # number of integer regfile writes -system.cpu.fp_regfile_reads 166054 # number of floating regfile reads -system.cpu.fp_regfile_writes 167450 # number of floating regfile writes -system.cpu.misc_regfile_reads 1999349 # number of misc regfile reads -system.cpu.misc_regfile_writes 950331 # number of misc regfile writes +system.cpu.rob.rob_reads 149996318 # The number of ROB reads +system.cpu.rob.rob_writes 130455868 # The number of ROB writes +system.cpu.timesIdled 1387986 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33674364 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3608226532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53094243 # Number of Instructions Simulated +system.cpu.committedOps 53094243 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 53094243 # Number of Instructions Simulated +system.cpu.cpi 2.308560 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.308560 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433170 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433170 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74446052 # number of integer regfile reads +system.cpu.int_regfile_writes 40661007 # number of integer regfile writes +system.cpu.fp_regfile_reads 166346 # number of floating regfile reads +system.cpu.fp_regfile_writes 166939 # number of floating regfile writes +system.cpu.misc_regfile_reads 1998850 # number of misc regfile reads +system.cpu.misc_regfile_writes 950370 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -658,247 +658,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1020915 # number of replacements -system.cpu.icache.tagsinuse 509.977219 # Cycle average of tags in use -system.cpu.icache.total_refs 7681837 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1021424 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.520713 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23212946000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.977219 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996049 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996049 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7681838 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7681838 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7681838 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7681838 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7681838 # number of overall hits -system.cpu.icache.overall_hits::total 7681838 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1079605 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079605 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1079605 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079605 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1079605 # number of overall misses -system.cpu.icache.overall_misses::total 1079605 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16072965497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16072965497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16072965497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16072965497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16072965497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16072965497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8761443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8761443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8761443 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8761443 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8761443 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8761443 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123222 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123222 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123222 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123222 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123222 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123222 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14887.820543 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14887.820543 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14887.820543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14887.820543 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1368497 # number of cycles access was blocked +system.cpu.icache.replacements 1025209 # number of replacements +system.cpu.icache.tagsinuse 509.960172 # Cycle average of tags in use +system.cpu.icache.total_refs 7772148 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1025718 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.577276 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23722278000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.960172 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996016 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996016 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7772149 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7772149 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7772149 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7772149 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7772149 # number of overall hits +system.cpu.icache.overall_hits::total 7772149 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1087170 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1087170 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1087170 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1087170 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1087170 # number of overall misses +system.cpu.icache.overall_misses::total 1087170 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528418489 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17528418489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17528418489 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17528418489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17528418489 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17528418489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8859319 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8859319 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8859319 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8859319 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8859319 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8859319 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122715 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122715 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122715 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122715 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122715 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122715 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16122.978457 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16122.978457 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16122.978457 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16122.978457 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1581994 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9845.302158 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8071.397959 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 236 # number of writebacks -system.cpu.icache.writebacks::total 236 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57973 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 57973 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 57973 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 57973 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 57973 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 57973 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021632 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1021632 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1021632 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1021632 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1021632 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1021632 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12173342997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12173342997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12173342997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12173342997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12173342997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12173342997 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116605 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116605 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116605 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11915.585061 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11915.585061 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 238 # number of writebacks +system.cpu.icache.writebacks::total 238 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61204 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 61204 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 61204 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 61204 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 61204 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 61204 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025966 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1025966 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1025966 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1025966 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1025966 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1025966 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13510508994 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13510508994 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13510508994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13510508994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13510508994 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13510508994 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115806 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115806 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115806 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13168.573807 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13168.573807 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13168.573807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13168.573807 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1401226 # number of replacements -system.cpu.dcache.tagsinuse 511.995976 # Cycle average of tags in use -system.cpu.dcache.total_refs 11915698 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401738 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.500660 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19319000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995976 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1403926 # number of replacements +system.cpu.dcache.tagsinuse 511.995922 # Cycle average of tags in use +system.cpu.dcache.total_refs 11884045 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1404438 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.461780 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19693000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995922 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7290659 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7290659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4213930 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4213930 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 190794 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 190794 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 220142 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220142 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11504589 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11504589 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11504589 # number of overall hits -system.cpu.dcache.overall_hits::total 11504589 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1799381 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1799381 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1940587 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1940587 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23075 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23075 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3739968 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3739968 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3739968 # number of overall misses -system.cpu.dcache.overall_misses::total 3739968 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37711411500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37711411500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57880522429 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57880522429 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 335593000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 335593000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 14000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 14000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95591933929 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95591933929 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95591933929 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95591933929 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9090040 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9090040 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6154517 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6154517 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213869 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 213869 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 220143 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220143 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15244557 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15244557 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15244557 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15244557 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197951 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.197951 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315311 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.315311 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107893 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107893 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245331 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245331 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245331 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20957.991387 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20957.991387 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29826.296079 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29826.296079 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14543.575298 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14543.575298 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25559.559314 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25559.559314 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 805076325 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 99334 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 7283526 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7283526 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4189382 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4189382 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190687 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190687 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 220149 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220149 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11472908 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11472908 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11472908 # number of overall hits +system.cpu.dcache.overall_hits::total 11472908 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1829585 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1829585 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1968134 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1968134 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23417 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23417 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3797719 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3797719 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3797719 # number of overall misses +system.cpu.dcache.overall_misses::total 3797719 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48849966500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48849966500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 74989002011 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 74989002011 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 432032000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 432032000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 56500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 56500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 123838968511 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 123838968511 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 123838968511 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 123838968511 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9113111 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9113111 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157516 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157516 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214104 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214104 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 220153 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220153 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15270627 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15270627 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15270627 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15270627 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319631 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319631 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000018 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000018 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.248694 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.248694 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.248694 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.248694 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26700.025689 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26700.025689 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38101.573374 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38101.573374 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18449.502498 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18449.502498 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14125 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14125 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32608.776087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32608.776087 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 732928021 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72145 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8104.740824 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10159.096556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840933 # number of writebacks -system.cpu.dcache.writebacks::total 840933 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 715397 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 715397 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640618 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1640618 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5145 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5145 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2356015 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2356015 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2356015 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2356015 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083984 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083984 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299969 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299969 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17930 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17930 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383953 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383953 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383953 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383953 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24067895500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24067895500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8474806325 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8474806325 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206484500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206484500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32542701825 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32542701825 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32542701825 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32542701825 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904540000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904540000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234101998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234101998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138641998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138641998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048740 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048740 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083836 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083836 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090783 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090783 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22203.183350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22203.183350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28252.273818 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28252.273818 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11516.146124 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11516.146124 # average LoadLockedReq mshr miss latency +system.cpu.dcache.writebacks::writebacks 842954 # number of writebacks +system.cpu.dcache.writebacks::total 842954 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 743747 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 743747 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667534 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1667534 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5230 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5230 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2411281 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2411281 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2411281 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2411281 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085838 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1085838 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300600 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300600 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386438 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386438 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386438 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386438 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28239740000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28239740000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9650792448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9650792448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 273508500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 273508500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37890532448 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37890532448 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37890532448 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37890532448 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 905949500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 905949500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1225663998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1225663998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2131613498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2131613498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084945 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084945 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000018 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000018 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090791 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26007.323376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26007.323376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32105.097964 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32105.097964 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15038.681476 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15038.681476 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -907,28 +907,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211701 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74930 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105874 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182929 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73563 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73566 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149254 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820291216500 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94615000 0.01% 97.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 380636500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38112442500 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858878910500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211694 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74899 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 247 0.14% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1887 1.03% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105884 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182917 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73532 49.28% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 247 0.17% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149203 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1825754390000 97.87% 97.87% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 99081000 0.01% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 381309500 0.02% 97.90% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 39166410000 2.10% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865401190500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694845 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815912 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694505 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815687 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -967,29 +967,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175590 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6787 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175564 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5216 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5223 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192549 # number of callpals executed +system.cpu.kern.callpal::total 192535 # number of callpals executed system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_switch::user 1736 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2110 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1736 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320403 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320067 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.389547 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29004913500 1.56% 1.56% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2663331000 0.14% 1.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827210658000 98.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080569 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.388940 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29632954500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2782152500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832986075500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index ea1e9a4d7..7eac6f043 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -577,7 +577,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -638,7 +638,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -1051,7 +1051,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 570320fa8..3620c0fb4 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,25 +10,25 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 5596738500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 -warn: 5604531500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5613988500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5652343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 5668456500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6102531000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 5800930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5810491000: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5849158000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 5865375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6307702500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 53268640500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 53639390500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2455592103500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2467697849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2487360820500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2487895818500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2493686984500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2494805379500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2494806652500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2456135822500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2468351819500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2488200522500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2488780405500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2494975875500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2496192426500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2496193716500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2496816594500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 494cdd6ff..f106f905a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:32:52 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 17:05:39 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2500827052500 because m5_exit instruction encountered +Exiting @ tick 2502549875500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 655a3d26b..4976e4992 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,16 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.500827 # Number of seconds simulated -sim_ticks 2500827052500 # Number of ticks simulated -final_tick 2500827052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.502550 # Number of seconds simulated +sim_ticks 2502549875500 # Number of ticks simulated +final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76093 # Simulator instruction rate (inst/s) -host_op_rate 98249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3194009596 # Simulator tick rate (ticks/s) -host_mem_usage 386968 # Number of bytes of host memory used -host_seconds 782.97 # Real time elapsed on the host -sim_insts 59579144 # Number of instructions simulated -sim_ops 76926734 # Number of ops (including micro ops) simulated +host_inst_rate 75474 # Simulator instruction rate (inst/s) +host_op_rate 97450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3170228022 # Simulator tick rate (ticks/s) +host_mem_usage 386888 # Number of bytes of host memory used +host_seconds 789.39 # Real time elapsed on the host +sim_insts 59578267 # Number of instructions simulated +sim_ops 76925839 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory +system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -23,191 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 117964800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095824 # Number of bytes read from this memory -system.physmem.bytes_read::total 127863440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14745600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142156 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14900300 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47170315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3637126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51128462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1513330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1206030 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2719360 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1513330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47170315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4843156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53847821 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64425 # number of replacements -system.l2c.tagsinuse 51220.169448 # Cycle average of tags in use -system.l2c.total_refs 2029411 # Total number of references to valid blocks. -system.l2c.sampled_refs 129819 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.632619 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2490891834000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36757.661469 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 42.093314 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000181 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8185.117102 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6235.297383 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.560877 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000642 # Average percentage of cache occupancy +system.l2c.replacements 64431 # number of replacements +system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use +system.l2c.total_refs 2028510 # Total number of references to valid blocks. +system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.624716 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124895 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781558 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122696 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11776 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 977061 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 384470 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1496003 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 675876 # number of Writeback hits -system.l2c.Writeback_hits::total 675876 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 50 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112893 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112893 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122696 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 977061 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 497363 # number of demand (read+write) hits -system.l2c.demand_hits::total 1608896 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122696 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11776 # number of overall hits -system.l2c.overall_hits::cpu.inst 977061 # number of overall hits -system.l2c.overall_hits::cpu.data 497363 # number of overall hits -system.l2c.overall_hits::total 1608896 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits +system.l2c.Writeback_hits::total 675442 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits +system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits +system.l2c.overall_hits::cpu.inst 977935 # number of overall hits +system.l2c.overall_hits::cpu.data 496445 # number of overall hits +system.l2c.overall_hits::total 1608169 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12370 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10695 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23118 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2910 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133257 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133257 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12370 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143952 # number of demand (read+write) misses -system.l2c.demand_misses::total 156375 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 52 # number of overall misses +system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses +system.l2c.demand_misses::total 156364 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 59 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12370 # number of overall misses -system.l2c.overall_misses::cpu.data 143952 # number of overall misses -system.l2c.overall_misses::total 156375 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2714000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 53000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 647826500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 558032000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1208625500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 993500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 993500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6991862500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6991862500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2714000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 53000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 647826500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7549894500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8200488000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2714000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 53000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 647826500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7549894500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8200488000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 122748 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11777 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 989431 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 395165 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1519121 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 675876 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 675876 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2960 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2960 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246150 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246150 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 122748 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11777 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 989431 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 641315 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1765271 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 122748 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11777 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 989431 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 641315 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1765271 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000424 # miss rate for ReadReq accesses +system.l2c.overall_misses::cpu.inst 12384 # number of overall misses +system.l2c.overall_misses::cpu.data 143920 # number of overall misses +system.l2c.overall_misses::total 156364 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3091500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 659591498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 562236498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1224979496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 944500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 944500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7069904999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7069904999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3091500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1764533 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 122022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11827 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 990319 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 640365 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1764533 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012502 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.027065 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015218 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.983108 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.983108 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.294118 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541365 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541365 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000424 # miss rate for demand accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012505 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.027107 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015235 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.985768 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.985768 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.541656 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541656 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012502 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.224464 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088584 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000424 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu.inst 0.012505 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.224747 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.088615 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012502 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.224464 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.088584 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52370.776071 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52176.905096 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52280.711999 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 341.408935 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 341.408935 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 10400 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 10400 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52469.007257 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52469.007257 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52441.170264 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52441.170264 # average overall miss latency +system.l2c.overall_miss_rate::cpu.inst 0.012505 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.224747 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.088615 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52949.189367 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 324.682021 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 324.682021 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53065.811490 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53048.556541 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53048.556541 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -216,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59134 # number of writebacks -system.l2c.writebacks::total 59134 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 59159 # number of writebacks +system.l2c.writebacks::total 59159 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12362 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10633 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2910 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2910 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133257 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133257 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12375 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10629 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 133229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133229 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12362 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143890 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156305 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12375 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 143858 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156293 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12362 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143890 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156305 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2081000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 41000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 496452000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 425891000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 924465000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116622000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116622000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5338935000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5338935000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2081000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 41000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 496452000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5764826000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6263400000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2081000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 41000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 496452000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5764826000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6263400000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5219000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32353763131 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32353763131 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5219000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164123546631 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_misses::cpu.inst 12375 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 143858 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156293 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2372000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 508160500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 430170499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 940750999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116825000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 116825000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5436034999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5436034999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2372000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 508160500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5866205498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6376785998 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2372000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 508160500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5866205498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6376785998 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31373446015 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31373446015 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 162795884015 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026908 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015172 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983108 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.983108 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541365 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541365 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088544 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088544 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660 # average UpgradeReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -336,26 +332,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048239 # DTB read hits -system.cpu.checker.dtb.read_misses 7308 # DTB read misses -system.cpu.checker.dtb.write_hits 11293838 # DTB write hits -system.cpu.checker.dtb.write_misses 2191 # DTB write misses +system.cpu.checker.dtb.read_hits 15048164 # DTB read hits +system.cpu.checker.dtb.read_misses 7309 # DTB read misses +system.cpu.checker.dtb.write_hits 11293826 # DTB write hits +system.cpu.checker.dtb.write_misses 2190 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15055547 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296029 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15055473 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296016 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26342077 # DTB hits +system.cpu.checker.dtb.hits 26341990 # DTB hits system.cpu.checker.dtb.misses 9499 # DTB misses -system.cpu.checker.dtb.accesses 26351576 # DTB accesses -system.cpu.checker.itb.inst_hits 60745761 # ITB inst hits +system.cpu.checker.dtb.accesses 26351489 # DTB accesses +system.cpu.checker.itb.inst_hits 60744881 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -372,36 +368,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 60750232 # ITB inst accesses -system.cpu.checker.itb.hits 60745761 # DTB hits +system.cpu.checker.itb.inst_accesses 60749352 # ITB inst accesses +system.cpu.checker.itb.hits 60744881 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 60750232 # DTB accesses -system.cpu.checker.numCycles 77205158 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 60749352 # DTB accesses +system.cpu.checker.numCycles 77204260 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51785537 # DTB read hits -system.cpu.dtb.read_misses 81591 # DTB read misses -system.cpu.dtb.write_hits 11872923 # DTB write hits -system.cpu.dtb.write_misses 18231 # DTB write misses +system.cpu.dtb.read_hits 51771660 # DTB read hits +system.cpu.dtb.read_misses 81258 # DTB read misses +system.cpu.dtb.write_hits 11880398 # DTB write hits +system.cpu.dtb.write_misses 17961 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8065 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2988 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8043 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1351 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51867128 # DTB read accesses -system.cpu.dtb.write_accesses 11891154 # DTB write accesses +system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51852918 # DTB read accesses +system.cpu.dtb.write_accesses 11898359 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63658460 # DTB hits -system.cpu.dtb.misses 99822 # DTB misses -system.cpu.dtb.accesses 63758282 # DTB accesses -system.cpu.itb.inst_hits 13022422 # ITB inst hits -system.cpu.itb.inst_misses 12153 # ITB inst misses +system.cpu.dtb.hits 63652058 # DTB hits +system.cpu.dtb.misses 99219 # DTB misses +system.cpu.dtb.accesses 63751277 # DTB accesses +system.cpu.itb.inst_hits 13142261 # ITB inst hits +system.cpu.itb.inst_misses 12247 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -410,542 +406,542 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5249 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5262 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3259 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13034575 # ITB inst accesses -system.cpu.itb.hits 13022422 # DTB hits -system.cpu.itb.misses 12153 # DTB misses -system.cpu.itb.accesses 13034575 # DTB accesses -system.cpu.numCycles 408047924 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154508 # ITB inst accesses +system.cpu.itb.hits 13142261 # DTB hits +system.cpu.itb.misses 12247 # DTB misses +system.cpu.itb.accesses 13154508 # DTB accesses +system.cpu.numCycles 413642740 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14895929 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11838635 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 749498 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9774236 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7761608 # Number of BTB hits +system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450585 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80646 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32131999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 99541579 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14895929 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9212193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21738174 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6062724 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 161664 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 89532236 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 119247 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208172 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13018415 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 931788 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6733 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 148050131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.832729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.216336 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 126328884 85.33% 85.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1364567 0.92% 86.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1757577 1.19% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2627928 1.78% 89.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1817598 1.23% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1139974 0.77% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2881875 1.95% 93.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 793207 0.54% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9338521 6.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148050131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.036505 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.243946 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34138786 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89344652 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19542719 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1039822 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3984152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2096721 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174752 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 115904821 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572765 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3984152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36116919 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36990471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46307759 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18567490 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6083340 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 109034273 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3076 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1021710 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4089268 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 41156 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 113585552 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 502111824 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 502019660 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 92164 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77687957 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35897594 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898050 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797560 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12232946 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20954804 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13881914 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1960286 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2534637 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 99654588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1554944 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124705745 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186396 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23520309 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 64631044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 267642 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148050131 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.842321 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.546134 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 103452672 69.88% 69.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13854502 9.36% 79.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7174552 4.85% 84.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5822865 3.93% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12669865 8.56% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2797622 1.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1712436 1.16% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 433578 0.29% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132039 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148050131 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 59948 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8388673 94.51% 95.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 427083 4.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58643579 47.03% 47.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95161 0.08% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 13 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53352582 42.78% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12505747 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124705745 # Type of FU issued -system.cpu.iq.rate 0.305615 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8875706 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406599918 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124750196 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85869603 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23265 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12672 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10345 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133462587 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 642048 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued +system.cpu.iq.rate 0.301258 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5239514 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10265 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34172 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2083712 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107049 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1151692 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3984152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28395992 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 447371 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101464012 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 233619 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20954804 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13881914 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 964089 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112476 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6557 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34172 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 381147 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 331860 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713007 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121711788 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52474170 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2993957 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 254480 # number of nop insts executed -system.cpu.iew.exec_refs 64857639 # number of memory reference insts executed -system.cpu.iew.exec_branches 11392260 # Number of branches executed -system.cpu.iew.exec_stores 12383469 # Number of stores executed -system.cpu.iew.exec_rate 0.298278 # Inst execution rate -system.cpu.iew.wb_sent 120307041 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85879948 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46962413 # num instructions producing a value -system.cpu.iew.wb_consumers 87363153 # num instructions consuming a value +system.cpu.iew.exec_nop 256054 # number of nop insts executed +system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed +system.cpu.iew.exec_branches 11412736 # Number of branches executed +system.cpu.iew.exec_stores 12391364 # Number of stores executed +system.cpu.iew.exec_rate 0.293583 # Inst execution rate +system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46459932 # num instructions producing a value +system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210465 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.537554 # average fanout of values written-back +system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59729525 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77077115 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24198873 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287302 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 621123 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 144148394 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.534707 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.521609 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions +system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 116600934 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13538329 9.39% 90.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3987949 2.77% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2150587 1.49% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1741345 1.21% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1028717 0.71% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1566098 1.09% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 669906 0.46% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2864529 1.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 144148394 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59729525 # Number of instructions committed -system.cpu.commit.committedOps 77077115 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59728648 # Number of instructions committed +system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513492 # Number of memory references committed -system.cpu.commit.loads 15715290 # Number of loads committed -system.cpu.commit.membars 413064 # Number of memory barriers committed -system.cpu.commit.branches 9904425 # Number of branches committed +system.cpu.commit.refs 27513345 # Number of memory references committed +system.cpu.commit.loads 15715170 # Number of loads committed +system.cpu.commit.membars 413057 # Number of memory barriers committed +system.cpu.commit.branches 9904308 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68617780 # Number of committed integer instructions. -system.cpu.commit.function_calls 995959 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2864529 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68616986 # Number of committed integer instructions. +system.cpu.commit.function_calls 995953 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240802540 # The number of ROB reads -system.cpu.rob.rob_writes 206662154 # The number of ROB writes -system.cpu.timesIdled 1878638 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 259997793 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593518134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59579144 # Number of Instructions Simulated -system.cpu.committedOps 76926734 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59579144 # Number of Instructions Simulated -system.cpu.cpi 6.848838 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.848838 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146010 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.146010 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 552215112 # number of integer regfile reads -system.cpu.int_regfile_writes 88113132 # number of integer regfile writes -system.cpu.fp_regfile_reads 8314 # number of floating regfile reads -system.cpu.fp_regfile_writes 2878 # number of floating regfile writes -system.cpu.misc_regfile_reads 131767968 # number of misc regfile reads -system.cpu.misc_regfile_writes 912736 # number of misc regfile writes -system.cpu.icache.replacements 990445 # number of replacements -system.cpu.icache.tagsinuse 511.614969 # Cycle average of tags in use -system.cpu.icache.total_refs 11943122 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990957 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.052109 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6217994000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.614969 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999248 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999248 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11943122 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11943122 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11943122 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11943122 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11943122 # number of overall hits -system.cpu.icache.overall_hits::total 11943122 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1075156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1075156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1075156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1075156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1075156 # number of overall misses -system.cpu.icache.overall_misses::total 1075156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15637742995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15637742995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15637742995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15637742995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15637742995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15637742995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13018278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13018278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13018278 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13018278 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13018278 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13018278 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082588 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082588 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082588 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082588 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082588 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082588 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14544.627008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14544.627008 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2121995 # number of cycles access was blocked +system.cpu.rob.rob_reads 246021016 # The number of ROB reads +system.cpu.rob.rob_writes 206855771 # The number of ROB writes +system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59578267 # Number of Instructions Simulated +system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated +system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 551124725 # number of integer regfile reads +system.cpu.int_regfile_writes 87730819 # number of integer regfile writes +system.cpu.fp_regfile_reads 8186 # number of floating regfile reads +system.cpu.fp_regfile_writes 2858 # number of floating regfile writes +system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads +system.cpu.misc_regfile_writes 912697 # number of misc regfile writes +system.cpu.icache.replacements 991190 # number of replacements +system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use +system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits +system.cpu.icache.overall_hits::total 12061455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses +system.cpu.icache.overall_misses::total 1076423 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7342.543253 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 67776 # number of writebacks -system.cpu.icache.writebacks::total 67776 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84152 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84152 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84152 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84152 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84152 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84152 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991004 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991004 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991004 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991004 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991004 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991004 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11660559495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11660559495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11660559495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11660559495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11660559495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11660559495 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6997000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6997000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076124 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076124 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076124 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 67899 # number of writebacks +system.cpu.icache.writebacks::total 67899 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644124 # number of replacements -system.cpu.dcache.tagsinuse 511.991568 # Cycle average of tags in use -system.cpu.dcache.total_refs 21775548 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644636 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.779603 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 49161000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991568 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13910712 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13910712 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7293091 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7293091 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 282930 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 282930 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285654 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285654 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21203803 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21203803 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21203803 # number of overall hits -system.cpu.dcache.overall_hits::total 21203803 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 740801 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 740801 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2957315 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2957315 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13662 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3698116 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3698116 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3698116 # number of overall misses -system.cpu.dcache.overall_misses::total 3698116 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10501483000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10501483000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 106800352759 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 200535500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 200535500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 452000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 452000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117301835759 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117301835759 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117301835759 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117301835759 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14651513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 643139 # number of replacements +system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use +system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits +system.cpu.dcache.overall_hits::total 21161261 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 765252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 765252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2993311 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2993311 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13765 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13765 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3758563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3758563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3758563 # number of overall misses +system.cpu.dcache.overall_misses::total 3758563 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14844603000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14844603000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129412035593 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223977000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223977000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 405000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 405000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144256638593 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144256638593 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144256638593 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144256638593 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14669418 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14669418 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296592 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 296592 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24901919 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24901919 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24901919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24901919 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050561 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050561 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288507 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288507 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046063 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046063 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000060 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000060 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148507 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148507 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148507 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148507 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31719.350004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31719.350004 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14079439 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7830500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2852 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4936.689691 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285658 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285658 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24919824 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24919824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24919824 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24919824 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052166 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052166 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292019 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292019 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046252 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046252 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150826 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150826 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150826 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150826 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38380.795691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38380.795691 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32633902 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7260500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7285 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4479.602196 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608100 # number of writebacks -system.cpu.dcache.writebacks::total 608100 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354542 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 354542 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2708293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2708293 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1346 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1346 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3062835 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3062835 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3062835 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3062835 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386259 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386259 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12316 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12316 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635281 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635281 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635281 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635281 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4943544500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4943544500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8596724439 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8596724439 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 143823500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 143823500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 395000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 395000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13540268939 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13540268939 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13540268939 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13540268939 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42257629539 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42257629539 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026363 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026363 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks +system.cpu.dcache.writebacks::total 607543 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -967,16 +963,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1290934638893 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88048 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 8259e7988..8ee00f929 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -960,7 +960,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -1021,7 +1021,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -1434,7 +1434,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index c3484784a..6f1b9eba3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -14,7 +14,6 @@ warn: Returning thumbEE disabled for now since we don't support CP14config regis warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 02c5cc88a..fe27005da 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:33:16 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 17:16:08 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2569716290500 because m5_exit instruction encountered +Exiting @ tick 2581527583500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 038e4aa5b..ba015b214 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,75 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.569716 # Number of seconds simulated -sim_ticks 2569716290500 # Number of ticks simulated -final_tick 2569716290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.581528 # Number of seconds simulated +sim_ticks 2581527583500 # Number of ticks simulated +final_tick 2581527583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91215 # Simulator instruction rate (inst/s) -host_op_rate 117813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3779331614 # Simulator tick rate (ticks/s) -host_mem_usage 391064 # Number of bytes of host memory used -host_seconds 679.94 # Real time elapsed on the host -sim_insts 62020337 # Number of instructions simulated -sim_ops 80105642 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 383040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4310004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 438272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5311600 # Number of bytes read from this memory -system.physmem.bytes_read::total 129982372 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 383040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4277376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7306512 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 5985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 83020 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15105505 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66834 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824118 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46517845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 149059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1677230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 170553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2066999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50582382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 149059 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 170553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1664532 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6616 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1172167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2843315 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1664532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46517845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 149059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1683845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 170553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3239165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53425697 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 89313 # Simulator instruction rate (inst/s) +host_op_rate 115365 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3717496726 # Simulator tick rate (ticks/s) +host_mem_usage 390980 # Number of bytes of host memory used +host_seconds 694.43 # Real time elapsed on the host +sim_insts 62021206 # Number of instructions simulated +sim_ops 80112751 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory @@ -80,259 +21,300 @@ system.realview.nvmem.num_reads::cpu0.inst 1 # system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 125 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 125 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 125 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72902 # number of replacements -system.l2c.tagsinuse 52914.655952 # Cycle average of tags in use -system.l2c.total_refs 2024041 # Total number of references to valid blocks. -system.l2c.sampled_refs 138037 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.663032 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4372084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5226480 # Number of bytes read from this memory +system.physmem.bytes_read::total 129958756 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 820544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244480 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7273616 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81690 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15105136 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66320 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46305011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 153013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1693603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2024569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50341804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 153013 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1644174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6585 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1166804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2817563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1644174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46305011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 153013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1700189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3191372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53159367 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72536 # number of replacements +system.l2c.tagsinuse 53024.626088 # Cycle average of tags in use +system.l2c.total_refs 2019266 # Total number of references to valid blocks. +system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.660834 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37560.940783 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.394478 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000176 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4213.394018 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2969.636370 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 12.170115 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.970249 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4028.311406 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4125.838357 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.573134 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000052 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37701.415204 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.259804 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000179 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4215.968317 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2959.624437 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 13.637835 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4028.150256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4102.570055 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575278 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000050 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064291 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045313 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000186 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061467 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062955 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.807414 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 50859 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5940 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 395141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 161674 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 79156 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 619717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 202375 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1521452 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 646021 # number of Writeback hits -system.l2c.Writeback_hits::total 646021 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 861 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1085 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1946 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 373 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 50919 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55813 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106732 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 50859 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5940 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 395141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 212593 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 79156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 619717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 258188 # number of demand (read+write) hits -system.l2c.demand_hits::total 1628184 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 50859 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5940 # number of overall hits -system.l2c.overall_hits::cpu0.inst 395141 # number of overall hits -system.l2c.overall_hits::cpu0.data 212593 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 79156 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6590 # number of overall hits -system.l2c.overall_hits::cpu1.inst 619717 # number of overall hits -system.l2c.overall_hits::cpu1.data 258188 # number of overall hits -system.l2c.overall_hits::total 1628184 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses +system.l2c.occ_percent::cpu0.inst 0.064331 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045160 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000208 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061465 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062600 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.809092 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 53338 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6106 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 398719 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 164464 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 78886 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6452 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 615129 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 199702 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1522796 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 645710 # number of Writeback hits +system.l2c.Writeback_hits::total 645710 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 806 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1849 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48030 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59189 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107219 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 53338 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6106 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 398719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 212494 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 78886 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6452 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 615129 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 258891 # number of demand (read+write) hits +system.l2c.demand_hits::total 1630015 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 53338 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6106 # number of overall hits +system.l2c.overall_hits::cpu0.inst 398719 # number of overall hits +system.l2c.overall_hits::cpu0.data 212494 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 78886 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6452 # number of overall hits +system.l2c.overall_hits::cpu1.inst 615129 # number of overall hits +system.l2c.overall_hits::cpu1.data 258891 # number of overall hits +system.l2c.overall_hits::total 1630015 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5853 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6139 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6809 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6537 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25366 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5294 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4767 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10061 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 775 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 577 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1352 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 62637 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77700 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140337 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 6044 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6302 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6609 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6328 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25314 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5683 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4287 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9970 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 777 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1366 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63451 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76572 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140023 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5853 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 68776 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6809 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 84237 # number of demand (read+write) misses -system.l2c.demand_misses::total 165703 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses +system.l2c.demand_misses::cpu0.inst 6044 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69753 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6609 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 82900 # number of demand (read+write) misses +system.l2c.demand_misses::total 165337 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5853 # number of overall misses -system.l2c.overall_misses::cpu0.data 68776 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6809 # number of overall misses -system.l2c.overall_misses::cpu1.data 84237 # number of overall misses -system.l2c.overall_misses::total 165703 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 521500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 53000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 306091000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 320158000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 783000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 356464000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 341134500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1325309000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 18664500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 31259000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 49923500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1307000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6272500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 7579500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3285106999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4081053500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7366160499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 521500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 53000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 306091000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3605264999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 783000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 104000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 356464000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4422188000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8691469499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 521500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 53000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 306091000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3605264999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 783000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 104000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 356464000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4422188000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8691469499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 50869 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5941 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 400994 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 167813 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 79171 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6592 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 626526 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 208912 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1546818 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 646021 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 646021 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6155 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5852 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 12007 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 984 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 741 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1725 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 113556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 133513 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247069 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 50869 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5941 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 400994 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 281369 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 79171 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6592 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 626526 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 342425 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1793887 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 50869 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5941 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 400994 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 281369 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 79171 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6592 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 626526 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 342425 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1793887 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000168 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014596 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036582 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000303 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010868 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.031291 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016399 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.860114 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.814593 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.837928 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787602 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.778677 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.783768 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.551596 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.581966 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.568007 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014596 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244433 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010868 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.246001 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.092371 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014596 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244433 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010868 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.246001 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.092371 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 53000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52296.429182 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52151.490471 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52200 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52351.887208 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52185.176687 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52247.457226 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3525.595013 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6557.373610 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4962.081304 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1686.451613 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 10870.883882 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5606.139053 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52446.748711 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52523.211068 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52489.083413 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 53000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52296.429182 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52420.393727 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52200 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52351.887208 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52496.978762 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52452.095007 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 53000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52296.429182 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52420.393727 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52200 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52351.887208 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52496.978762 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52452.095007 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 6044 # number of overall misses +system.l2c.overall_misses::cpu0.data 69753 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6609 # number of overall misses +system.l2c.overall_misses::cpu1.data 82900 # number of overall misses +system.l2c.overall_misses::total 165337 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 471000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 60000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 322261499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 330895497 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1101000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 351559997 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 332583499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1338932492 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 20202500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27410499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 47612999 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1721500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7138500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 8860000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3379920986 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4071556980 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7451477966 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 471000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 60000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 322261499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3710816483 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1101000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 351559997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4404140479 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8790410458 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 471000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 60000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 322261499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3710816483 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1101000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 351559997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4404140479 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8790410458 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 53347 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6107 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 404763 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 170766 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 78907 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6452 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 621738 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 206030 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1548110 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 645710 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 645710 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6726 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5093 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11819 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 990 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 732 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1722 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111481 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135761 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247242 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 53347 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6107 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 404763 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 282247 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 78907 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6452 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 621738 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 341791 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1795352 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 53347 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6107 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 404763 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 282247 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 78907 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6452 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 621738 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 341791 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1795352 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000164 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014932 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036904 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010630 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016352 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844930 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.841744 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.843557 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784848 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.804645 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.793264 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.569164 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.564021 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566340 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000164 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014932 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.247135 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010630 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.242546 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.092092 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000164 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014932 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.247135 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010630 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.242546 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.092092 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53319.242058 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52506.426055 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.128764 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52557.442952 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52892.964052 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3554.900581 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6393.864941 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4775.626780 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2215.572716 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12119.694397 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 6486.090776 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.206742 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53172.921956 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53216.099969 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53166.626091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53166.626091 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,180 +323,170 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66834 # number of writebacks -system.l2c.writebacks::total 66834 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 66320 # number of writebacks +system.l2c.writebacks::total 66320 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5849 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6101 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6803 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6512 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25293 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5294 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4767 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 10061 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 775 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 577 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1352 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 62637 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77700 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140337 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6039 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6263 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6604 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6305 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25242 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5683 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4287 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 9970 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 777 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 589 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1366 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63450 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76572 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140022 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5849 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 68738 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6803 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 84212 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165630 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6039 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69713 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6604 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 82877 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165264 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5849 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 68738 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6803 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 84212 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165630 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 41000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 234434500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 244221500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 601000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 273121500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 260689500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1013589000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 211949500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190864500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 402814000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31033000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23118500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 54151500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2507451999 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3115007000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5622458999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 41000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 234434500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2751673499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 601000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 273121500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3375696500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6636047999 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 41000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 234434500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2751673499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 601000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 273121500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3375696500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6636047999 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5501500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 21616744000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2009500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 110336260000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131960515000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 713445484 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31812115712 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32525561196 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5501500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 22330189484 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2009500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 142148375712 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164486076196 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036356 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.031171 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016352 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.860114 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.814593 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.837928 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787602 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.778677 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.783768 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.551596 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581966 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.568007 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244298 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.245928 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.092330 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244298 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.245928 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.092330 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses::cpu0.inst 6039 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69713 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6604 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 82877 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165264 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 48000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 248302999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253032000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 846000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270719997 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254713500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1028022496 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227576000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 171718000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 399294000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31112500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23586500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 54699000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2608560498 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3134816489 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5743376987 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 48000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 248302999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2861592498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 846000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 270719997 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3389529989 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6771399483 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 48000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 248302999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2861592498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 846000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 270719997 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3389529989 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6771399483 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5579000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9186859000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2133500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122397706500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131592278000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 704572999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30781654107 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31486227106 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9891431999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2133500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153179360607 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163078505106 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036676 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030602 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016305 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.844930 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.841744 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.843557 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784848 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.804645 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.793264 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569155 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564021 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566336 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.092051 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.092051 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.749221 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40032.171376 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.893963 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.795240 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.703587 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.173243 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40042.580645 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.724437 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40052.884615 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40031.482973 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40090.180180 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40063.981694 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40401.085742 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40398.651864 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40726.665716 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40045.046630 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40055.516678 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40049.548646 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.827542 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40044.991511 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40043.191801 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41112.064586 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40939.462062 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41017.675701 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -537,27 +509,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12222008 # DTB read hits -system.cpu0.dtb.read_misses 34799 # DTB read misses -system.cpu0.dtb.write_hits 5155654 # DTB write hits -system.cpu0.dtb.write_misses 4970 # DTB write misses +system.cpu0.dtb.read_hits 9084255 # DTB read hits +system.cpu0.dtb.read_misses 36769 # DTB read misses +system.cpu0.dtb.write_hits 5284576 # DTB write hits +system.cpu0.dtb.write_misses 6773 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2546 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1270 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 369 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2261 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1412 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 383 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 661 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12256807 # DTB read accesses -system.cpu0.dtb.write_accesses 5160624 # DTB write accesses +system.cpu0.dtb.perms_faults 588 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9121024 # DTB read accesses +system.cpu0.dtb.write_accesses 5291349 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17377662 # DTB hits -system.cpu0.dtb.misses 39769 # DTB misses -system.cpu0.dtb.accesses 17417431 # DTB accesses -system.cpu0.itb.inst_hits 4312814 # ITB inst hits -system.cpu0.itb.inst_misses 5659 # ITB inst misses +system.cpu0.dtb.hits 14368831 # DTB hits +system.cpu0.dtb.misses 43542 # DTB misses +system.cpu0.dtb.accesses 14412373 # DTB accesses +system.cpu0.itb.inst_hits 4421795 # ITB inst hits +system.cpu0.itb.inst_misses 5958 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -566,542 +538,542 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1615 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1415 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1550 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1713 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4318473 # ITB inst accesses -system.cpu0.itb.hits 4312814 # DTB hits -system.cpu0.itb.misses 5659 # DTB misses -system.cpu0.itb.accesses 4318473 # DTB accesses -system.cpu0.numCycles 91755333 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4427753 # ITB inst accesses +system.cpu0.itb.hits 4421795 # DTB hits +system.cpu0.itb.misses 5958 # DTB misses +system.cpu0.itb.accesses 4427753 # DTB accesses +system.cpu0.numCycles 66112093 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5952266 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4505075 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 304047 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3800923 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2764349 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6172143 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4680207 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 316413 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3902841 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2861272 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 686219 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 29965 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12225669 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 31634782 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5952266 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3450568 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7438203 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1498517 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 86111 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 25429329 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 56004 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 89121 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 253 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4310960 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 168036 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2895 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 46396814 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.887686 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.274992 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 700420 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 30889 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12972431 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32579396 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6172143 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3561692 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7636967 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1568394 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 92289 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21876805 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 73340 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 91549 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4419869 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 175391 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2999 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 43870869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.963501 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.353712 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 38966492 83.99% 83.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 608768 1.31% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 793531 1.71% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 678621 1.46% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 615872 1.33% 89.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 550838 1.19% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 680018 1.47% 92.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 365085 0.79% 93.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3137589 6.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 36242473 82.61% 82.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 623814 1.42% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 820212 1.87% 85.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686089 1.56% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 622737 1.42% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 578948 1.32% 90.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 720296 1.64% 91.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 370745 0.85% 92.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3205555 7.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 46396814 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.064871 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.344773 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12690058 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 25456221 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6703467 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 545759 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1001309 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 958631 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66338 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39766150 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 219028 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1001309 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13289637 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7972865 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15343248 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6631332 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2158423 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38589176 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 848 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 416461 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1242307 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 106 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 38596643 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175113710 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175069465 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 44245 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30775876 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7820767 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 452714 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 409285 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5195885 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7781233 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5757511 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1120127 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1192401 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36577178 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 791583 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 40176979 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 83237 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5967561 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13599049 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 145097 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 46396814 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.865943 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.513269 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 43870869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.093359 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.492790 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 13461534 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21912526 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6836712 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 603785 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1056312 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 995110 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66550 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40827533 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 217718 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1056312 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 14066817 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6153021 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13456769 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6788701 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2349249 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39593607 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1040 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 472233 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1335984 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 103 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39791095 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 179675714 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 179640853 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34861 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31537071 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8254023 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 463697 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 419128 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5673165 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7928571 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5881726 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132931 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1238845 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37538443 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 794373 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37739879 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92690 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6264606 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14354053 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 137507 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 43870869 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.860249 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.478315 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 30520128 65.78% 65.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5937185 12.80% 78.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3046653 6.57% 85.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2264959 4.88% 90.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2893477 6.24% 96.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 928258 2.00% 98.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 563400 1.21% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 186019 0.40% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 56735 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 28164784 64.20% 64.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6326126 14.42% 78.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3234526 7.37% 85.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2361316 5.38% 91.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2098246 4.78% 96.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 936106 2.13% 98.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 514694 1.17% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 181493 0.41% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53578 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 46396814 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 43870869 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26385 1.46% 1.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.03% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 1567613 86.92% 88.41% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 209022 11.59% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27565 2.58% 2.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 466 0.04% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 837939 78.44% 81.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202337 18.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 25309 0.06% 0.06% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 21935197 54.60% 54.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48039 0.12% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 725 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 12687286 31.58% 86.36% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5480393 13.64% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 20407 0.05% 0.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22494595 59.60% 59.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 50051 0.13% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9563453 25.34% 85.13% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5610668 14.87% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 40176979 # Type of FU issued -system.cpu0.iq.rate 0.437871 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1803473 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.044888 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 128665759 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43343315 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34031138 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11205 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6096 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4927 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 41949154 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5989 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 311358 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37739879 # Type of FU issued +system.cpu0.iq.rate 0.570847 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1068307 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028307 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 120546534 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44606042 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34820056 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8333 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4740 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38783456 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4323 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 326383 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1414489 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4027 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13694 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 607908 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1507630 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4080 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13930 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 608245 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 5397304 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5188 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149509 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5404 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1001309 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6077720 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 124694 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37485087 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 95046 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7781233 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5757511 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 467034 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 52649 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13694 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 153875 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 138964 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 292839 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 39778235 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 12530314 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 398744 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1056312 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4064319 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 129740 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38471177 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 88757 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7928571 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5881726 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 461616 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 49674 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17745 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13930 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 159357 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144737 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 304094 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37337331 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9402148 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 402548 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116326 # number of nop insts executed -system.cpu0.iew.exec_refs 17957262 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4780864 # Number of branches executed -system.cpu0.iew.exec_stores 5426948 # Number of stores executed -system.cpu0.iew.exec_rate 0.433525 # Inst execution rate -system.cpu0.iew.wb_sent 39572300 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34036065 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18213937 # num instructions producing a value -system.cpu0.iew.wb_consumers 35297892 # num instructions consuming a value +system.cpu0.iew.exec_nop 138361 # number of nop insts executed +system.cpu0.iew.exec_refs 14958639 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4921687 # Number of branches executed +system.cpu0.iew.exec_stores 5556491 # Number of stores executed +system.cpu0.iew.exec_rate 0.564758 # Inst execution rate +system.cpu0.iew.wb_sent 37117116 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34823949 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18360594 # num instructions producing a value +system.cpu0.iew.wb_consumers 34980725 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.370944 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.516006 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.526741 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.524877 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 23601687 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 31186721 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6143896 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 646486 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 256571 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 45430638 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.686469 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.654503 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 24134633 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 31866160 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6466683 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 656866 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 267750 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 42850944 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.743651 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.697776 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33717084 74.22% 74.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5850006 12.88% 87.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1884843 4.15% 91.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 960822 2.11% 93.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 731888 1.61% 94.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 454898 1.00% 95.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 476885 1.05% 97.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 212485 0.47% 97.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1141727 2.51% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 30739496 71.74% 71.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6075340 14.18% 85.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1944692 4.54% 90.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1041937 2.43% 92.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 773699 1.81% 94.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 503770 1.18% 95.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 405337 0.95% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 203427 0.47% 97.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1163246 2.71% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 45430638 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23601687 # Number of instructions committed -system.cpu0.commit.committedOps 31186721 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 42850944 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24134633 # Number of instructions committed +system.cpu0.commit.committedOps 31866160 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11516347 # Number of memory references committed -system.cpu0.commit.loads 6366744 # Number of loads committed -system.cpu0.commit.membars 228774 # Number of memory barriers committed -system.cpu0.commit.branches 4268909 # Number of branches committed -system.cpu0.commit.fp_insts 4838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27636133 # Number of committed integer instructions. -system.cpu0.commit.function_calls 492618 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1141727 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11694422 # Number of memory references committed +system.cpu0.commit.loads 6420941 # Number of loads committed +system.cpu0.commit.membars 234529 # Number of memory barriers committed +system.cpu0.commit.branches 4382702 # Number of branches committed +system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 28193395 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499856 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1163246 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 80832744 # The number of ROB reads -system.cpu0.rob.rob_writes 75665562 # The number of ROB writes -system.cpu0.timesIdled 511317 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 45358519 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5047039822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23536584 # Number of Instructions Simulated -system.cpu0.committedOps 31121618 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23536584 # Number of Instructions Simulated -system.cpu0.cpi 3.898413 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.898413 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.256515 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.256515 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 183926116 # number of integer regfile reads -system.cpu0.int_regfile_writes 33429350 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4511 # number of floating regfile reads -system.cpu0.fp_regfile_writes 934 # number of floating regfile writes -system.cpu0.misc_regfile_reads 45525801 # number of misc regfile reads -system.cpu0.misc_regfile_writes 515221 # number of misc regfile writes -system.cpu0.icache.replacements 402234 # number of replacements -system.cpu0.icache.tagsinuse 511.630403 # Cycle average of tags in use -system.cpu0.icache.total_refs 3875529 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 402746 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.622762 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6260006000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.630403 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999278 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999278 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3875529 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3875529 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3875529 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3875529 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3875529 # number of overall hits -system.cpu0.icache.overall_hits::total 3875529 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 435289 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 435289 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 435289 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 435289 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 435289 # number of overall misses -system.cpu0.icache.overall_misses::total 435289 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6419795491 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6419795491 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6419795491 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6419795491 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6419795491 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6419795491 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4310818 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4310818 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4310818 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4310818 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4310818 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4310818 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100976 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100976 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100976 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100976 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100976 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100976 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14748.352223 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14748.352223 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14748.352223 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14748.352223 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1456992 # number of cycles access was blocked +system.cpu0.rob.rob_reads 79207972 # The number of ROB reads +system.cpu0.rob.rob_writes 77724528 # The number of ROB writes +system.cpu0.timesIdled 427936 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22241224 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5096899290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24053891 # Number of Instructions Simulated +system.cpu0.committedOps 31785418 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24053891 # Number of Instructions Simulated +system.cpu0.cpi 2.748499 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.748499 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.363835 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.363835 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174526329 # number of integer regfile reads +system.cpu0.int_regfile_writes 34331240 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3280 # number of floating regfile reads +system.cpu0.fp_regfile_writes 898 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46875879 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527497 # number of misc regfile writes +system.cpu0.icache.replacements 406974 # number of replacements +system.cpu0.icache.tagsinuse 511.614338 # Cycle average of tags in use +system.cpu0.icache.total_refs 3978434 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 407486 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.763364 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6469268000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.614338 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999247 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999247 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3978434 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3978434 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3978434 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3978434 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3978434 # number of overall hits +system.cpu0.icache.overall_hits::total 3978434 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 441298 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 441298 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 441298 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 441298 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 441298 # number of overall misses +system.cpu0.icache.overall_misses::total 441298 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7186656997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7186656997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7186656997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7186656997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7186656997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7186656997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4419732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4419732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4419732 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4419732 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4419732 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4419732 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099847 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.099847 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099847 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.099847 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099847 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.099847 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16285.269811 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16285.269811 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16285.269811 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16285.269811 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1454497 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8938.601227 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8505.830409 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 31582 # number of writebacks -system.cpu0.icache.writebacks::total 31582 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32527 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 32527 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 32527 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 32527 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 32527 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 32527 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 402762 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 402762 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 402762 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 402762 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 402762 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 402762 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4809385492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4809385492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4809385492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4809385492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4809385492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4809385492 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7376000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7376000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7376000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7376000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093431 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093431 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093431 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11941.011049 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 29234 # number of writebacks +system.cpu0.icache.writebacks::total 29234 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33802 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 33802 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 33802 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 33802 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 33802 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 33802 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407496 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 407496 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 407496 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 407496 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 407496 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 407496 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5527499503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5527499503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5527499503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5527499503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5527499503 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5527499503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092199 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.092199 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.092199 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13564.549107 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 272390 # number of replacements -system.cpu0.dcache.tagsinuse 477.646995 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9259935 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 272772 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.947528 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49645000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 477.646995 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.932904 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.932904 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5751664 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5751664 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3128629 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3128629 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172667 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172667 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 169954 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 169954 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8880293 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8880293 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8880293 # number of overall hits -system.cpu0.dcache.overall_hits::total 8880293 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 380393 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 380393 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1568163 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1568163 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9112 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9112 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7881 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7881 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1948556 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1948556 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1948556 # number of overall misses -system.cpu0.dcache.overall_misses::total 1948556 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5112833000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5112833000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57745298395 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 57745298395 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100839000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 100839000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 84292000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 84292000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 62858131395 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 62858131395 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 62858131395 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 62858131395 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6132057 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6132057 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4696792 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4696792 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181779 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 181779 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 177835 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 177835 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10828849 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10828849 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10828849 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10828849 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062034 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062034 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333880 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333880 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.050127 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.050127 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044316 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044316 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179941 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.179941 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179941 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.179941 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13440.922940 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13440.922940 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 36823.530714 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 36823.530714 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11066.615452 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11066.615452 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10695.597005 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10695.597005 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32258.827252 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32258.827252 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3762493 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1470000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 438 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8590.166667 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18607.594937 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275761 # number of replacements +system.cpu0.dcache.tagsinuse 476.305820 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9551525 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276273 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.572778 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 476.305820 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.930285 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.930285 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5934693 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5934693 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3224707 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3224707 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174478 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174478 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171499 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171499 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9159400 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9159400 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9159400 # number of overall hits +system.cpu0.dcache.overall_hits::total 9159400 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 401255 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 401255 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1594245 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1594245 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9007 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9007 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7794 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7794 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1995500 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1995500 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1995500 # number of overall misses +system.cpu0.dcache.overall_misses::total 1995500 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7289566500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 7289566500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71816395371 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71816395371 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114642500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 114642500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93715000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 93715000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 79105961871 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 79105961871 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 79105961871 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 79105961871 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6335948 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6335948 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818952 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4818952 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183485 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183485 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179293 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179293 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11154900 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11154900 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11154900 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11154900 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063330 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063330 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330828 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330828 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049088 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049088 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043471 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043471 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178890 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178890 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178890 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178890 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18166.917546 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18166.917546 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45047.276530 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45047.276530 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12728.155879 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12728.155879 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12023.992815 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12023.992815 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39642.175831 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39642.175831 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7140493 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1629000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1441 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4955.234559 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18303.370787 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 253456 # number of writebacks -system.cpu0.dcache.writebacks::total 253456 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 195063 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 195063 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436472 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1436472 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 621 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 621 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1631535 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1631535 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1631535 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1631535 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 185330 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 185330 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131691 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131691 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8491 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8491 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7877 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7877 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 317021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 317021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 317021 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 317021 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2232196000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2232196000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4281157492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4281157492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67651500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67651500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60619000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60619000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6513353492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6513353492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6513353492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6513353492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 24166586500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 24166586500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 850308391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 850308391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 25016894891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 25016894891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030223 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030223 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028038 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028038 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046711 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046711 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029276 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029276 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12044.439648 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.439648 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32509.112179 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32509.112179 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7967.436109 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7967.436109 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7695.696331 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7695.696331 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks +system.cpu0.dcache.writebacks::total 255942 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211815 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 211815 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463184 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1463184 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 509 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 509 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674999 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1674999 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674999 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1674999 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189440 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189440 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131061 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131061 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8498 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8498 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7791 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7791 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320501 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320501 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2806583905 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2806583905 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685193022 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685193022 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 80265007 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 80265007 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 69214057 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 69214057 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7491776927 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7491776927 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7491776927 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7491776927 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315161000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315161000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849550399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849550399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164711399 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164711399 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029899 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029899 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027197 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027197 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046314 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046314 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043454 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043454 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028732 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028732 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14815.159971 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14815.159971 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.186127 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.186127 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9445.164392 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9445.164392 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8883.847645 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8883.847645 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1111,27 +1083,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 40314372 # DTB read hits -system.cpu1.dtb.read_misses 47835 # DTB read misses -system.cpu1.dtb.write_hits 7207214 # DTB write hits -system.cpu1.dtb.write_misses 14308 # DTB write misses +system.cpu1.dtb.read_hits 43446349 # DTB read hits +system.cpu1.dtb.read_misses 46684 # DTB read misses +system.cpu1.dtb.write_hits 7088138 # DTB write hits +system.cpu1.dtb.write_misses 12274 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2204 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3789 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 426 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2545 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3731 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 361 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 618 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 40362207 # DTB read accesses -system.cpu1.dtb.write_accesses 7221522 # DTB write accesses +system.cpu1.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43493033 # DTB read accesses +system.cpu1.dtb.write_accesses 7100412 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 47521586 # DTB hits -system.cpu1.dtb.misses 62143 # DTB misses -system.cpu1.dtb.accesses 47583729 # DTB accesses -system.cpu1.itb.inst_hits 9199147 # ITB inst hits -system.cpu1.itb.inst_misses 6537 # ITB inst misses +system.cpu1.dtb.hits 50534487 # DTB hits +system.cpu1.dtb.misses 58958 # DTB misses +system.cpu1.dtb.accesses 50593445 # DTB accesses +system.cpu1.itb.inst_hits 9221438 # ITB inst hits +system.cpu1.itb.inst_misses 6034 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1140,542 +1112,546 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1398 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1610 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1778 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1730 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9205684 # ITB inst accesses -system.cpu1.itb.hits 9199147 # DTB hits -system.cpu1.itb.misses 6537 # DTB misses -system.cpu1.itb.accesses 9205684 # DTB accesses -system.cpu1.numCycles 321589455 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9227472 # ITB inst accesses +system.cpu1.itb.hits 9221438 # DTB hits +system.cpu1.itb.misses 6034 # DTB misses +system.cpu1.itb.accesses 9227472 # DTB accesses +system.cpu1.numCycles 353824423 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9609219 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7804241 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 456907 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6466725 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5325877 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9470897 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7703385 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 447489 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6420671 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5281203 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 844527 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50619 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 21504333 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71435147 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9609219 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6170404 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15136389 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4734420 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 89053 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 66067639 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5715 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 64771 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 143196 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9197098 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 766779 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3914 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 106241109 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.815152 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.196213 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 834152 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 50449 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 22167103 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 70445168 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9470897 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6115355 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14956565 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4597208 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 88094 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 73687570 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 6011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 61739 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 141755 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9219303 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 857673 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3541 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114241434 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.747913 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.114106 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 91113370 85.76% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 835957 0.79% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1038807 0.98% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2054123 1.93% 89.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1283354 1.21% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 639035 0.60% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2277082 2.14% 93.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 459375 0.43% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6540006 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99293168 86.92% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 828706 0.73% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1015866 0.89% 88.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2054648 1.80% 90.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1280264 1.12% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 613123 0.54% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2273093 1.99% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 467514 0.41% 94.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6415052 5.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 106241109 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029880 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.222131 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23013271 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 65947642 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13617278 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 534194 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3128724 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1272359 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 103085 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 80569967 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 342001 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3128724 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 24438096 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 29197230 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 32706540 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12706787 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4063732 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74758294 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 627503 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2908939 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 45012 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 79187879 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 346602336 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 346555262 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 47074 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50022423 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 29165455 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 496148 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 429704 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7532124 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14054260 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8745175 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1095062 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1520090 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 67170682 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 857343 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 88258087 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 108704 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18559774 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53338169 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 154632 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 106241109 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.830734 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.556038 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114241434 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.026767 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199096 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23740446 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 73499308 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13432186 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 537783 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3031711 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1242419 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102480 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 79700896 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 342426 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3031711 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 25267828 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33699109 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 35312301 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12394168 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4536317 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 73261010 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3244 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 714923 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3281779 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33706 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 77426546 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 339504965 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 339445449 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59516 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49265102 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28161444 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 486276 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 420659 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8155263 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14019935 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8605996 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1069297 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1521896 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 66318588 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 855610 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 90596015 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108958 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18341957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53651445 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 163223 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114241434 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.793022 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.525613 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 76008182 71.54% 71.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8446540 7.95% 79.49% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4482838 4.22% 83.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3826420 3.60% 87.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 9985833 9.40% 96.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1963466 1.85% 98.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1174590 1.11% 99.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 267511 0.25% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 85729 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83094748 72.74% 72.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8828314 7.73% 80.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4518450 3.96% 84.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3737052 3.27% 87.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10664138 9.33% 97.02% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1972512 1.73% 98.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1063413 0.93% 99.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 282401 0.25% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 80406 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 106241109 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114241434 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 34820 0.48% 0.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 995 0.01% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 6868408 95.11% 95.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 317335 4.39% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29108 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 993 0.01% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7574349 95.84% 96.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 298565 3.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 81809 0.09% 0.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39074007 44.27% 44.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 63191 0.07% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 5 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1634 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 41444924 46.96% 91.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7592491 8.60% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 86745 0.10% 0.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 38337785 42.32% 42.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61539 0.07% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 4 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44639306 49.27% 91.76% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7468915 8.24% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 88258087 # Type of FU issued -system.cpu1.iq.rate 0.274443 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7221558 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.081823 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 290137702 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 86602000 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55480726 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11865 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6384 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95391603 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6233 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 377691 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 90596015 # Type of FU issued +system.cpu1.iq.rate 0.256048 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7903015 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.087234 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 303489486 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 85529327 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54443530 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14763 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8091 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6830 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 98404572 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7713 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 368848 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4014151 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6631 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 21303 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1605227 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4030694 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6909 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 21919 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1587988 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 28717238 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1149940 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965710 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1045299 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3128724 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 22478642 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 328290 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68173106 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 141945 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14054260 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8745175 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 539434 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 62530 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3755 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 21303 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 237741 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 202628 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 440369 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85609132 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 40707747 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2648955 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3031711 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25598263 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 405605 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 67299344 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 135063 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14019935 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8605996 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 545729 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 81019 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 7196 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 21919 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 232087 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 197105 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 429192 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87765278 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43831578 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2830737 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 145081 # number of nop insts executed -system.cpu1.iew.exec_refs 48220727 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7143156 # Number of branches executed -system.cpu1.iew.exec_stores 7512980 # Number of stores executed -system.cpu1.iew.exec_rate 0.266206 # Inst execution rate -system.cpu1.iew.wb_sent 84396881 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55486086 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30755357 # num instructions producing a value -system.cpu1.iew.wb_consumers 55849815 # num instructions consuming a value +system.cpu1.iew.exec_nop 125146 # number of nop insts executed +system.cpu1.iew.exec_refs 51224987 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7024509 # Number of branches executed +system.cpu1.iew.exec_stores 7393409 # Number of stores executed +system.cpu1.iew.exec_rate 0.248048 # Inst execution rate +system.cpu1.iew.wb_sent 86598496 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54450360 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30044182 # num instructions producing a value +system.cpu1.iew.wb_consumers 53342809 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.172537 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.550680 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.153891 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.563228 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38569031 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 49069302 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 19027054 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 702711 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 384240 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103162057 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.475653 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.464816 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38036954 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 48396972 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 18817114 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 692387 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 376510 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111258144 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.434997 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.402953 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 86125230 83.49% 83.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8314170 8.06% 91.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2284328 2.21% 93.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1318858 1.28% 95.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1066734 1.03% 96.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 616185 0.60% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1058049 1.03% 97.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 494277 0.48% 98.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1884226 1.83% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94210177 84.68% 84.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8524716 7.66% 92.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2208233 1.98% 94.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1307974 1.18% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1064973 0.96% 96.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 589982 0.53% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1003368 0.90% 97.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 487910 0.44% 98.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1860811 1.67% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103162057 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38569031 # Number of instructions committed -system.cpu1.commit.committedOps 49069302 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111258144 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38036954 # Number of instructions committed +system.cpu1.commit.committedOps 48396972 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17180057 # Number of memory references committed -system.cpu1.commit.loads 10040109 # Number of loads committed -system.cpu1.commit.membars 207982 # Number of memory barriers committed -system.cpu1.commit.branches 6108113 # Number of branches committed -system.cpu1.commit.fp_insts 5310 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43785233 # Number of committed integer instructions. -system.cpu1.commit.function_calls 563417 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1884226 # number cycles where commit BW limit reached +system.cpu1.commit.refs 17007249 # Number of memory references committed +system.cpu1.commit.loads 9989241 # Number of loads committed +system.cpu1.commit.membars 202226 # Number of memory barriers committed +system.cpu1.commit.branches 5993368 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43235909 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556157 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1860811 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 168322862 # The number of ROB reads -system.cpu1.rob.rob_writes 139443210 # The number of ROB writes -system.cpu1.timesIdled 1396987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 215348346 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4817788385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38483753 # Number of Instructions Simulated -system.cpu1.committedOps 48984024 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38483753 # Number of Instructions Simulated -system.cpu1.cpi 8.356499 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.356499 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.119667 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.119667 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 385614321 # number of integer regfile reads -system.cpu1.int_regfile_writes 58138574 # number of integer regfile writes -system.cpu1.fp_regfile_reads 3969 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1880 # number of floating regfile writes -system.cpu1.misc_regfile_reads 91635789 # number of misc regfile reads -system.cpu1.misc_regfile_writes 441645 # number of misc regfile writes -system.cpu1.icache.replacements 628575 # number of replacements -system.cpu1.icache.tagsinuse 498.649539 # Cycle average of tags in use -system.cpu1.icache.total_refs 8518604 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 629087 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.541218 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 73946666000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.649539 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.973925 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.973925 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8518604 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8518604 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8518604 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8518604 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8518604 # number of overall hits -system.cpu1.icache.overall_hits::total 8518604 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 678443 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 678443 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 678443 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 678443 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 678443 # number of overall misses -system.cpu1.icache.overall_misses::total 678443 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9864551499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9864551499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9864551499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9864551499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9864551499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9864551499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9197047 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9197047 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9197047 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9197047 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9197047 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9197047 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073767 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073767 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073767 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073767 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073767 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073767 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14539.985672 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14539.985672 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14539.985672 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14539.985672 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 932999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 175585773 # The number of ROB reads +system.cpu1.rob.rob_writes 137553768 # The number of ROB writes +system.cpu1.timesIdled 1520299 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 239582989 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4808538839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37967315 # Number of Instructions Simulated +system.cpu1.committedOps 48327333 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37967315 # Number of Instructions Simulated +system.cpu1.cpi 9.319185 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 9.319185 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.107306 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.107306 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 393921761 # number of integer regfile reads +system.cpu1.int_regfile_writes 56840694 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4925 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes +system.cpu1.misc_regfile_reads 90313719 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429414 # number of misc regfile writes +system.cpu1.icache.replacements 622931 # number of replacements +system.cpu1.icache.tagsinuse 498.760560 # Cycle average of tags in use +system.cpu1.icache.total_refs 8545880 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 623443 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.707556 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74633827000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.760560 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974142 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974142 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8545880 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8545880 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8545880 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8545880 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8545880 # number of overall hits +system.cpu1.icache.overall_hits::total 8545880 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 673372 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 673372 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 673372 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 673372 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 673372 # number of overall misses +system.cpu1.icache.overall_misses::total 673372 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10716931993 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10716931993 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10716931993 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10716931993 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10716931993 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10716931993 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9219252 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9219252 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9219252 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9219252 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9219252 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9219252 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073040 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.073040 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073040 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.073040 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073040 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.073040 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15915.321684 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15915.321684 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15915.321684 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15915.321684 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1332494 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6098.032680 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6499.970732 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 30976 # number of writebacks -system.cpu1.icache.writebacks::total 30976 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49327 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 49327 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 49327 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 49327 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 49327 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 49327 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 629116 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 629116 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 629116 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 629116 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 629116 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 629116 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7390302499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7390302499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7390302499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7390302499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7390302499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7390302499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2676000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2676000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2676000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2676000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068404 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.068404 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.068404 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11747.122151 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 33068 # number of writebacks +system.cpu1.icache.writebacks::total 33068 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49906 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 49906 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 49906 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 49906 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 49906 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 49906 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623466 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 623466 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 623466 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 623466 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 623466 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 623466 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8227032008 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8227032008 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8227032008 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8227032008 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8227032008 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8227032008 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3154000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3154000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3154000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3154000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067627 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.067627 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.067627 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13195.638588 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 365990 # number of replacements -system.cpu1.dcache.tagsinuse 486.374853 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13437990 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 366502 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.665530 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70078369000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 486.374853 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.949951 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.949951 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8795505 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8795505 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4385128 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4385128 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 106581 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 106581 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102282 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 102282 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 13180633 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 13180633 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 13180633 # number of overall hits -system.cpu1.dcache.overall_hits::total 13180633 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 408153 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 408153 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1582783 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1582783 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13916 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13916 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10800 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10800 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1990936 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1990936 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1990936 # number of overall misses -system.cpu1.dcache.overall_misses::total 1990936 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5766799000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5766799000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 55285236443 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 55285236443 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 141367500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 141367500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 89573500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 89573500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 61052035443 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 61052035443 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 61052035443 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 61052035443 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9203658 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9203658 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5967911 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5967911 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120497 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 120497 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 113082 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 113082 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 15171569 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 15171569 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 15171569 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 15171569 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044347 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044347 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.265216 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.265216 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115488 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115488 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095506 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095506 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131228 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.131228 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131228 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.131228 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14129.012895 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14129.012895 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34929.132069 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34929.132069 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10158.630354 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10158.630354 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8293.842593 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8293.842593 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 30664.991463 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 30664.991463 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 12254574 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5966500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3013 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4067.233322 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 35727.544910 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 362729 # number of replacements +system.cpu1.dcache.tagsinuse 487.126779 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13112337 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 363073 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.114878 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70483759000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.126779 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951419 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951419 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8613908 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8613908 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4252702 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4252702 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105106 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 105106 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100709 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100709 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12866610 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12866610 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12866610 # number of overall hits +system.cpu1.dcache.overall_hits::total 12866610 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 410185 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 410185 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1595357 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1595357 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10900 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10900 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2005542 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2005542 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2005542 # number of overall misses +system.cpu1.dcache.overall_misses::total 2005542 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8114216000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8114216000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66620735237 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 66620735237 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166584000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 166584000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94819000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 94819000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 74734951237 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 74734951237 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 74734951237 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 74734951237 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9024093 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9024093 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848059 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5848059 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119384 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 119384 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111609 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 111609 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14872152 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14872152 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14872152 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14872152 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045454 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045454 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272801 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.272801 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119597 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119597 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097662 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097662 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134852 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134852 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134852 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134852 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19781.844777 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19781.844777 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41759.139326 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41759.139326 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11667.180277 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11667.180277 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8698.990826 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8698.990826 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 37264.216475 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 37264.216475 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29196505 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5606000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6645 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 174 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4393.755455 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32218.390805 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 330007 # number of writebacks -system.cpu1.dcache.writebacks::total 330007 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172901 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 172901 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1420692 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1420692 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1265 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1265 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1593593 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1593593 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1593593 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1593593 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 235252 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 235252 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162091 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162091 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12651 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12651 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10796 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10796 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 397343 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 397343 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 397343 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 397343 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2772800000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2772800000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5167139074 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5167139074 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88580000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88580000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57154000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57154000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7939939074 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7939939074 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7939939074 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7939939074 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 123239389500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 123239389500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41654166350 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41654166350 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 164893555850 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 164893555850 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025561 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025561 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027160 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027160 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104990 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104990 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095471 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095471 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026190 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026190 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11786.509785 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11786.509785 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31878.013425 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31878.013425 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7001.818038 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7001.818038 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5293.997777 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5293.997777 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327467 # number of writebacks +system.cpu1.dcache.writebacks::total 327467 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179191 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 179191 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432552 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1432552 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1457 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1457 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1611743 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1611743 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1611743 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1611743 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 230994 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 230994 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162805 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162805 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12821 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12821 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10892 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10892 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 393799 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 393799 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 393799 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 393799 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3545762451 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3545762451 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5565749199 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5565749199 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104395505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104395505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60832506 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60832506 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9111511650 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9111511650 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9111511650 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9111511650 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004750500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004750500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40571899654 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40571899654 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177576650154 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177576650154 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025597 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027839 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027839 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107393 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107393 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097591 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097591 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026479 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026479 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.019702 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15350.019702 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34186.598686 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34186.598686 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8142.539973 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8142.539973 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5585.062982 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5585.062982 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1697,18 +1673,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308136748055 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308136748055 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1305278151135 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1305278151135 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42935 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43785 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 54742 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53912 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 027fdffc2..71f536288 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -518,7 +518,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -579,7 +579,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -992,7 +992,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 9c5baf3db..34717b2ec 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:31:55 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 17:04:56 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2500827052500 because m5_exit instruction encountered +Exiting @ tick 2502549875500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 2b0eb45e9..6df4de0df 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.500827 # Number of seconds simulated -sim_ticks 2500827052500 # Number of ticks simulated -final_tick 2500827052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.502550 # Number of seconds simulated +sim_ticks 2502549875500 # Number of ticks simulated +final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90125 # Simulator instruction rate (inst/s) -host_op_rate 116367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3783000939 # Simulator tick rate (ticks/s) -host_mem_usage 386964 # Number of bytes of host memory used -host_seconds 661.07 # Real time elapsed on the host -sim_insts 59579144 # Number of instructions simulated -sim_ops 76926734 # Number of ops (including micro ops) simulated +host_inst_rate 90191 # Simulator instruction rate (inst/s) +host_op_rate 116452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3788406278 # Simulator tick rate (ticks/s) +host_mem_usage 386884 # Number of bytes of host memory used +host_seconds 660.58 # Real time elapsed on the host +sim_insts 59578267 # Number of instructions simulated +sim_ops 76925839 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory +system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -23,191 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 117964800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095824 # Number of bytes read from this memory -system.physmem.bytes_read::total 127863440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14745600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142156 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14900300 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47170315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3637126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51128462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1513330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1206030 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2719360 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1513330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47170315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4843156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53847821 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64425 # number of replacements -system.l2c.tagsinuse 51220.169448 # Cycle average of tags in use -system.l2c.total_refs 2029411 # Total number of references to valid blocks. -system.l2c.sampled_refs 129819 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.632619 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2490891834000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36757.661469 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 42.093314 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000181 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8185.117102 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6235.297383 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.560877 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000642 # Average percentage of cache occupancy +system.l2c.replacements 64431 # number of replacements +system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use +system.l2c.total_refs 2028510 # Total number of references to valid blocks. +system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.624716 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124895 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781558 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122696 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11776 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 977061 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 384470 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1496003 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 675876 # number of Writeback hits -system.l2c.Writeback_hits::total 675876 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 50 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112893 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112893 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122696 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 977061 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 497363 # number of demand (read+write) hits -system.l2c.demand_hits::total 1608896 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122696 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11776 # number of overall hits -system.l2c.overall_hits::cpu.inst 977061 # number of overall hits -system.l2c.overall_hits::cpu.data 497363 # number of overall hits -system.l2c.overall_hits::total 1608896 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits +system.l2c.Writeback_hits::total 675442 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits +system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits +system.l2c.overall_hits::cpu.inst 977935 # number of overall hits +system.l2c.overall_hits::cpu.data 496445 # number of overall hits +system.l2c.overall_hits::total 1608169 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12370 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10695 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23118 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2910 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133257 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133257 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12370 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143952 # number of demand (read+write) misses -system.l2c.demand_misses::total 156375 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 52 # number of overall misses +system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses +system.l2c.demand_misses::total 156364 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 59 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12370 # number of overall misses -system.l2c.overall_misses::cpu.data 143952 # number of overall misses -system.l2c.overall_misses::total 156375 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2714000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 53000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 647826500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 558032000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1208625500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 993500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 993500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6991862500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6991862500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2714000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 53000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 647826500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7549894500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8200488000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2714000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 53000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 647826500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7549894500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8200488000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 122748 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11777 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 989431 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 395165 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1519121 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 675876 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 675876 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2960 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2960 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246150 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246150 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 122748 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11777 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 989431 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 641315 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1765271 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 122748 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11777 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 989431 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 641315 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1765271 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000424 # miss rate for ReadReq accesses +system.l2c.overall_misses::cpu.inst 12384 # number of overall misses +system.l2c.overall_misses::cpu.data 143920 # number of overall misses +system.l2c.overall_misses::total 156364 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3091500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 659591498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 562236498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1224979496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 944500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 944500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7069904999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7069904999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3091500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1764533 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 122022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11827 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 990319 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 640365 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1764533 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012502 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.027065 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015218 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.983108 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.983108 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.294118 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541365 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541365 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000424 # miss rate for demand accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012505 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.027107 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015235 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.985768 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.985768 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.541656 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541656 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012502 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.224464 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088584 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000424 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu.inst 0.012505 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.224747 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.088615 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012502 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.224464 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.088584 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52370.776071 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52176.905096 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52280.711999 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 341.408935 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 341.408935 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 10400 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 10400 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52469.007257 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52469.007257 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52441.170264 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52441.170264 # average overall miss latency +system.l2c.overall_miss_rate::cpu.inst 0.012505 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.224747 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.088615 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52949.189367 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 324.682021 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 324.682021 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53065.811490 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53048.556541 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53048.556541 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -216,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59134 # number of writebacks -system.l2c.writebacks::total 59134 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 59159 # number of writebacks +system.l2c.writebacks::total 59159 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12362 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10633 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2910 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2910 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133257 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133257 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12375 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10629 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 133229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133229 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12362 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143890 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156305 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12375 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 143858 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156293 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12362 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143890 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156305 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2081000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 41000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 496452000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 425891000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 924465000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116622000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116622000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5338935000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5338935000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2081000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 41000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 496452000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5764826000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6263400000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2081000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 41000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 496452000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5764826000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6263400000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5219000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32353763131 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32353763131 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5219000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164123546631 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_misses::cpu.inst 12375 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 143858 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156293 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2372000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 508160500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 430170499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 940750999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116825000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 116825000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5436034999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5436034999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2372000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 508160500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5866205498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6376785998 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2372000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 508160500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5866205498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6376785998 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31373446015 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31373446015 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 162795884015 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026908 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015172 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983108 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.983108 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541365 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541365 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088544 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088544 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660 # average UpgradeReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -336,27 +332,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51785537 # DTB read hits -system.cpu.dtb.read_misses 81591 # DTB read misses -system.cpu.dtb.write_hits 11872923 # DTB write hits -system.cpu.dtb.write_misses 18231 # DTB write misses +system.cpu.dtb.read_hits 51771660 # DTB read hits +system.cpu.dtb.read_misses 81258 # DTB read misses +system.cpu.dtb.write_hits 11880398 # DTB write hits +system.cpu.dtb.write_misses 17961 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4506 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2988 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4471 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1351 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51867128 # DTB read accesses -system.cpu.dtb.write_accesses 11891154 # DTB write accesses +system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51852918 # DTB read accesses +system.cpu.dtb.write_accesses 11898359 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63658460 # DTB hits -system.cpu.dtb.misses 99822 # DTB misses -system.cpu.dtb.accesses 63758282 # DTB accesses -system.cpu.itb.inst_hits 13022422 # ITB inst hits -system.cpu.itb.inst_misses 12153 # ITB inst misses +system.cpu.dtb.hits 63652058 # DTB hits +system.cpu.dtb.misses 99219 # DTB misses +system.cpu.dtb.accesses 63751277 # DTB accesses +system.cpu.itb.inst_hits 13142261 # ITB inst hits +system.cpu.itb.inst_misses 12247 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -365,542 +361,542 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2627 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2634 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3259 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13034575 # ITB inst accesses -system.cpu.itb.hits 13022422 # DTB hits -system.cpu.itb.misses 12153 # DTB misses -system.cpu.itb.accesses 13034575 # DTB accesses -system.cpu.numCycles 408047924 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154508 # ITB inst accesses +system.cpu.itb.hits 13142261 # DTB hits +system.cpu.itb.misses 12247 # DTB misses +system.cpu.itb.accesses 13154508 # DTB accesses +system.cpu.numCycles 413642740 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14895929 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11838635 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 749498 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9774236 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7761608 # Number of BTB hits +system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450585 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80646 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32131999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 99541579 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14895929 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9212193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21738174 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6062724 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 161664 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 89532236 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 119247 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208172 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13018415 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 931788 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6733 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 148050131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.832729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.216336 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 126328884 85.33% 85.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1364567 0.92% 86.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1757577 1.19% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2627928 1.78% 89.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1817598 1.23% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1139974 0.77% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2881875 1.95% 93.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 793207 0.54% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9338521 6.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148050131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.036505 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.243946 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34138786 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89344652 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19542719 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1039822 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3984152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2096721 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174752 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 115904821 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572765 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3984152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36116919 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36990471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46307759 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18567490 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6083340 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 109034273 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3076 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1021710 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4089268 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 41156 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 113585552 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 502111824 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 502019660 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 92164 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77687957 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35897594 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898050 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797560 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12232946 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20954804 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13881914 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1960286 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2534637 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 99654588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1554944 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124705745 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186396 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23520309 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 64631044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 267642 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148050131 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.842321 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.546134 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 103452672 69.88% 69.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13854502 9.36% 79.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7174552 4.85% 84.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5822865 3.93% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12669865 8.56% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2797622 1.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1712436 1.16% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 433578 0.29% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132039 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148050131 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 59948 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8388673 94.51% 95.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 427083 4.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58643579 47.03% 47.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95161 0.08% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 13 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53352582 42.78% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12505747 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124705745 # Type of FU issued -system.cpu.iq.rate 0.305615 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8875706 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406599918 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124750196 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85869603 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23265 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12672 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10345 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133462587 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 642048 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued +system.cpu.iq.rate 0.301258 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5239514 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10265 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34172 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2083712 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107049 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1151692 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3984152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28395992 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 447371 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101464012 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 233619 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20954804 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13881914 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 964089 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112476 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6557 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34172 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 381147 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 331860 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713007 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121711788 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52474170 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2993957 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 254480 # number of nop insts executed -system.cpu.iew.exec_refs 64857639 # number of memory reference insts executed -system.cpu.iew.exec_branches 11392260 # Number of branches executed -system.cpu.iew.exec_stores 12383469 # Number of stores executed -system.cpu.iew.exec_rate 0.298278 # Inst execution rate -system.cpu.iew.wb_sent 120307041 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85879948 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46962413 # num instructions producing a value -system.cpu.iew.wb_consumers 87363153 # num instructions consuming a value +system.cpu.iew.exec_nop 256054 # number of nop insts executed +system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed +system.cpu.iew.exec_branches 11412736 # Number of branches executed +system.cpu.iew.exec_stores 12391364 # Number of stores executed +system.cpu.iew.exec_rate 0.293583 # Inst execution rate +system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46459932 # num instructions producing a value +system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210465 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.537554 # average fanout of values written-back +system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59729525 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77077115 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24198873 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287302 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 621123 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 144148394 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.534707 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.521609 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions +system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 116600934 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13538329 9.39% 90.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3987949 2.77% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2150587 1.49% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1741345 1.21% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1028717 0.71% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1566098 1.09% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 669906 0.46% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2864529 1.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 144148394 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59729525 # Number of instructions committed -system.cpu.commit.committedOps 77077115 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59728648 # Number of instructions committed +system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513492 # Number of memory references committed -system.cpu.commit.loads 15715290 # Number of loads committed -system.cpu.commit.membars 413064 # Number of memory barriers committed -system.cpu.commit.branches 9904425 # Number of branches committed +system.cpu.commit.refs 27513345 # Number of memory references committed +system.cpu.commit.loads 15715170 # Number of loads committed +system.cpu.commit.membars 413057 # Number of memory barriers committed +system.cpu.commit.branches 9904308 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68617780 # Number of committed integer instructions. -system.cpu.commit.function_calls 995959 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2864529 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68616986 # Number of committed integer instructions. +system.cpu.commit.function_calls 995953 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240802540 # The number of ROB reads -system.cpu.rob.rob_writes 206662154 # The number of ROB writes -system.cpu.timesIdled 1878638 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 259997793 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593518134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59579144 # Number of Instructions Simulated -system.cpu.committedOps 76926734 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59579144 # Number of Instructions Simulated -system.cpu.cpi 6.848838 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.848838 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146010 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.146010 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 552215109 # number of integer regfile reads -system.cpu.int_regfile_writes 88113131 # number of integer regfile writes -system.cpu.fp_regfile_reads 8314 # number of floating regfile reads -system.cpu.fp_regfile_writes 2878 # number of floating regfile writes -system.cpu.misc_regfile_reads 131767968 # number of misc regfile reads -system.cpu.misc_regfile_writes 912736 # number of misc regfile writes -system.cpu.icache.replacements 990445 # number of replacements -system.cpu.icache.tagsinuse 511.614969 # Cycle average of tags in use -system.cpu.icache.total_refs 11943122 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990957 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.052109 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6217994000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.614969 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999248 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999248 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11943122 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11943122 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11943122 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11943122 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11943122 # number of overall hits -system.cpu.icache.overall_hits::total 11943122 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1075156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1075156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1075156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1075156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1075156 # number of overall misses -system.cpu.icache.overall_misses::total 1075156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15637742995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15637742995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15637742995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15637742995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15637742995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15637742995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13018278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13018278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13018278 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13018278 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13018278 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13018278 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082588 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082588 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082588 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082588 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082588 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082588 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14544.627008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14544.627008 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2121995 # number of cycles access was blocked +system.cpu.rob.rob_reads 246021016 # The number of ROB reads +system.cpu.rob.rob_writes 206855771 # The number of ROB writes +system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59578267 # Number of Instructions Simulated +system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated +system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 551124722 # number of integer regfile reads +system.cpu.int_regfile_writes 87730818 # number of integer regfile writes +system.cpu.fp_regfile_reads 8186 # number of floating regfile reads +system.cpu.fp_regfile_writes 2858 # number of floating regfile writes +system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads +system.cpu.misc_regfile_writes 912697 # number of misc regfile writes +system.cpu.icache.replacements 991190 # number of replacements +system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use +system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits +system.cpu.icache.overall_hits::total 12061455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses +system.cpu.icache.overall_misses::total 1076423 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7342.543253 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 67776 # number of writebacks -system.cpu.icache.writebacks::total 67776 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84152 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84152 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84152 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84152 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84152 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84152 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991004 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991004 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991004 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991004 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991004 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991004 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11660559495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11660559495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11660559495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11660559495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11660559495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11660559495 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6997000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6997000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076124 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076124 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076124 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 67899 # number of writebacks +system.cpu.icache.writebacks::total 67899 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644124 # number of replacements -system.cpu.dcache.tagsinuse 511.991568 # Cycle average of tags in use -system.cpu.dcache.total_refs 21775548 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644636 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.779603 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 49161000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991568 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13910712 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13910712 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7293091 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7293091 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 282930 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 282930 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285654 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285654 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21203803 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21203803 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21203803 # number of overall hits -system.cpu.dcache.overall_hits::total 21203803 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 740801 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 740801 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2957315 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2957315 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13662 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3698116 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3698116 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3698116 # number of overall misses -system.cpu.dcache.overall_misses::total 3698116 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10501483000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10501483000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 106800352759 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 200535500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 200535500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 452000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 452000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117301835759 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117301835759 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117301835759 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117301835759 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14651513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 643139 # number of replacements +system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use +system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits +system.cpu.dcache.overall_hits::total 21161261 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 765252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 765252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2993311 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2993311 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13765 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13765 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3758563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3758563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3758563 # number of overall misses +system.cpu.dcache.overall_misses::total 3758563 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14844603000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14844603000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129412035593 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223977000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223977000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 405000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 405000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144256638593 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144256638593 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144256638593 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144256638593 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14669418 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14669418 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296592 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 296592 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24901919 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24901919 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24901919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24901919 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050561 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050561 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288507 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288507 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046063 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046063 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000060 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000060 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148507 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148507 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148507 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148507 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31719.350004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31719.350004 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14079439 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7830500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2852 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4936.689691 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285658 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285658 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24919824 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24919824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24919824 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24919824 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052166 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052166 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292019 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292019 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046252 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046252 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150826 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150826 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150826 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150826 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38380.795691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38380.795691 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32633902 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7260500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7285 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4479.602196 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608100 # number of writebacks -system.cpu.dcache.writebacks::total 608100 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354542 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 354542 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2708293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2708293 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1346 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1346 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3062835 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3062835 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3062835 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3062835 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386259 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386259 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12316 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12316 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635281 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635281 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635281 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635281 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4943544500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4943544500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8596724439 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8596724439 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 143823500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 143823500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 395000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 395000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13540268939 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13540268939 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13540268939 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13540268939 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42257629539 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42257629539 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026363 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026363 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks +system.cpu.dcache.writebacks::total 607543 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -922,16 +918,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1290934638893 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88048 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 1c6d485f3..43a81f743 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -935,7 +935,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.pc.pciconfig.pio master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master @@ -997,7 +997,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master @@ -1477,7 +1477,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index fefd6bd25..c8a74a70a 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 29 2012 00:25:59 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 14:54:43 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5147413032500 because m5_exit instruction encountered +Exiting @ tick 5173840734500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 674b1d778..4862f54d8 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.147413 # Number of seconds simulated -sim_ticks 5147413032500 # Number of ticks simulated -final_tick 5147413032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.173841 # Number of seconds simulated +sim_ticks 5173840734500 # Number of ticks simulated +final_tick 5173840734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192321 # Simulator instruction rate (inst/s) -host_op_rate 378987 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2320932369 # Simulator tick rate (ticks/s) -host_mem_usage 367552 # Number of bytes of host memory used -host_seconds 2217.82 # Real time elapsed on the host -sim_insts 426532736 # Number of instructions simulated -sim_ops 840526050 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2503168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1073280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10624512 # Number of bytes read from this memory -system.physmem.bytes_read::total 14204736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1073280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1073280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9409088 # Number of bytes written to this memory -system.physmem.bytes_written::total 9409088 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 39112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 166008 # Number of read requests responded to by this memory -system.physmem.num_reads::total 221949 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 147017 # Number of write requests responded to by this memory -system.physmem.num_writes::total 147017 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 486296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 208509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2064049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2759587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 208509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 208509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1827926 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1827926 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1827926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 486296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 208509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2064049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4587513 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 110659 # number of replacements -system.l2c.tagsinuse 64846.009272 # Cycle average of tags in use -system.l2c.total_refs 3990913 # Total number of references to valid blocks. -system.l2c.sampled_refs 174907 # Sample count of references to valid blocks. -system.l2c.avg_refs 22.817343 # Average number of references to valid blocks. +host_inst_rate 158571 # Simulator instruction rate (inst/s) +host_op_rate 312487 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1923470418 # Simulator tick rate (ticks/s) +host_mem_usage 368528 # Number of bytes of host memory used +host_seconds 2689.85 # Real time elapsed on the host +sim_insts 426531587 # Number of instructions simulated +sim_ops 840543055 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2458496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1064640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10449152 # Number of bytes read from this memory +system.physmem.bytes_read::total 13975936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1064640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1064640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9180480 # Number of bytes written to this memory +system.physmem.bytes_written::total 9180480 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 50 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16635 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 163268 # Number of read requests responded to by this memory +system.physmem.num_reads::total 218374 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143445 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143445 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 475178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 205774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2019612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2701269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 205774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 205774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1774403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1774403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1774403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 475178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 205774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2019612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4475672 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 107079 # number of replacements +system.l2c.tagsinuse 64844.194000 # Cycle average of tags in use +system.l2c.total_refs 3995584 # Total number of references to valid blocks. +system.l2c.sampled_refs 171337 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.320030 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50048.797239 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 13.777958 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.155980 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3384.461133 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11398.816962 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.763684 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000210 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051643 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.173932 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989472 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 111705 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 9478 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1055456 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1342066 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2518705 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1610504 # number of Writeback hits -system.l2c.Writeback_hits::total 1610504 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 315 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 315 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 161822 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 161822 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 111705 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 9478 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1055456 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1503888 # number of demand (read+write) hits -system.l2c.demand_hits::total 2680527 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 111705 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 9478 # number of overall hits -system.l2c.overall_hits::cpu.inst 1055456 # number of overall hits -system.l2c.overall_hits::cpu.data 1503888 # number of overall hits -system.l2c.overall_hits::total 2680527 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16771 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 36056 # number of ReadReq misses -system.l2c.ReadReq_misses::total 52886 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1746 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1746 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 130897 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130897 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 16771 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 166953 # number of demand (read+write) misses -system.l2c.demand_misses::total 183783 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 53 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses -system.l2c.overall_misses::cpu.inst 16771 # number of overall misses -system.l2c.overall_misses::cpu.data 166953 # number of overall misses -system.l2c.overall_misses::total 183783 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2763500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 312000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 876462500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1897742000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2777280000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 38052500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 38052500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6815913500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6815913500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2763500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 312000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 876462500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8713655500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9593193500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2763500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 312000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 876462500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8713655500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9593193500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 111758 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 9484 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1072227 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1378122 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2571591 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1610504 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1610504 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2061 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2061 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 292719 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292719 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 111758 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 9484 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1072227 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1670841 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2864310 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 111758 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 9484 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1072227 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1670841 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2864310 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000474 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.015641 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.026163 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020565 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.847162 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.847162 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.447176 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.447176 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000474 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000633 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.015641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.099922 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.064163 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000474 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000633 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.015641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.099922 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.064163 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52141.509434 # average ReadReq miss latency +system.l2c.occ_blocks::writebacks 50153.806815 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 12.883885 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.168545 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3383.279361 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11294.055394 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.765286 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000197 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.051625 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.172334 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989444 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 110015 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 8879 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1055721 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1346083 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2520698 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1613450 # number of Writeback hits +system.l2c.Writeback_hits::total 1613450 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 329 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 329 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 163813 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 163813 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 110015 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 8879 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1055721 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1509896 # number of demand (read+write) hits +system.l2c.demand_hits::total 2684511 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 110015 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 8879 # number of overall hits +system.l2c.overall_hits::cpu.inst 1055721 # number of overall hits +system.l2c.overall_hits::cpu.data 1509896 # number of overall hits +system.l2c.overall_hits::total 2684511 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 50 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 16637 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 34998 # number of ReadReq misses +system.l2c.ReadReq_misses::total 51692 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1514 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1514 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 129215 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 129215 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 50 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 16637 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 164213 # number of demand (read+write) misses +system.l2c.demand_misses::total 180907 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 50 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu.inst 16637 # number of overall misses +system.l2c.overall_misses::cpu.data 164213 # number of overall misses +system.l2c.overall_misses::total 180907 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2626500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 883116000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1863608490 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2749714990 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 39367500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 39367500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6737631498 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6737631498 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 2626500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 883116000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8601239988 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9487346488 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 2626500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 883116000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8601239988 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9487346488 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 110065 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 8886 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1072358 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1381081 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2572390 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1613450 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1613450 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 1843 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1843 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 293028 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 293028 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 110065 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 8886 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1072358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1674109 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2865418 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 110065 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 8886 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1072358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1674109 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2865418 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000454 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000788 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.015514 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.025341 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020095 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.821487 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.821487 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.440965 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.440965 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000454 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000788 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.015514 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.098090 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.063135 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000454 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000788 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.015514 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.098090 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.063135 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52530 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52260.598652 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52633.181717 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52514.465076 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 21794.100802 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 21794.100802 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52070.815221 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52070.815221 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52141.509434 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53081.444972 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 53248.999657 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 53194.207808 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 26002.311757 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 26002.311757 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52142.796873 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52142.796873 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52530 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52260.598652 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52192.266686 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52198.481361 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52141.509434 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53081.444972 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52378.557045 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52443.224906 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52530 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52260.598652 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52192.266686 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52198.481361 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53081.444972 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52378.557045 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52443.224906 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,99 +189,99 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 100350 # number of writebacks -system.l2c.writebacks::total 100350 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 96778 # number of writebacks +system.l2c.writebacks::total 96778 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 16770 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 36055 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 52884 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 1746 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1746 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 130897 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 130897 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 16770 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 166952 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 183781 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 16770 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 166952 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 183781 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2121000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 671584500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 1456546000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2130491500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 70212000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 70212000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5237071500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5237071500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2121000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 671584500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6693617500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7367563000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2121000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 671584500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6693617500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7367563000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59976004500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 59976004500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1230258000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1230258000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 61206262500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 61206262500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000474 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000633 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015640 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026162 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020565 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.847162 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.847162 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.447176 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.447176 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000474 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000633 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.015640 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.099921 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.064162 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000474 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000633 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.015640 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.099921 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.064162 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average ReadReq mshr miss latency +system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 50 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 16635 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 34997 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 51689 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 1514 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1514 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 129215 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 129215 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 50 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 16635 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 164212 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 180904 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 50 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 16635 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 164212 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 180904 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2020500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 680227000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1435916999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2118444499 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 60967500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 60967500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5181066001 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5181066001 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2020500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 680227000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6616983000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7299510500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2020500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 680227000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6616983000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7299510500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59191869564 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59191869564 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1211082000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1211082000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 60402951564 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60402951564 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025340 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020094 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.821487 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.821487 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.440965 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.440965 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.098089 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063134 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.098089 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063134 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40046.779964 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40397.892109 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40286.126239 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40213.058419 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40213.058419 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40009.102577 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40009.102577 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40891.313496 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41029.716804 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40984.435741 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40269.154557 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40269.154557 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40096.474875 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40096.474875 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40046.779964 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40093.065672 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40088.817669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40046.779964 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40093.065672 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40088.817669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47569 # number of replacements -system.iocache.tagsinuse 0.147452 # Cycle average of tags in use +system.iocache.replacements 47568 # number of replacements +system.iocache.tagsinuse 0.202980 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996357767000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.147452 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.009216 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.009216 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.warmup_cycle 5000598826000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.202980 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.012686 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.012686 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses +system.iocache.ReadReq_misses::total 903 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses -system.iocache.demand_misses::total 47624 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses -system.iocache.overall_misses::total 47624 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 113343932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 113343932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6309295160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6309295160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6422639092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6422639092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6422639092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6422639092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses +system.iocache.demand_misses::total 47623 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses +system.iocache.overall_misses::total 47623 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135810932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 135810932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6905757160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6905757160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7041568092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7041568092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 7041568092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7041568092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +330,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125380.455752 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125380.455752 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 135044.845034 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 135044.845034 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134861.395347 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 134861.395347 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134861.395347 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 134861.395347 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 66555216 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150399.703212 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 150399.703212 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147811.583048 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 147811.583048 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 147860.657497 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 147860.657497 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11227 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5928.138951 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 903 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 903 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47624 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47624 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47624 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47624 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66312982 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 66312982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3879551568 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3879551568 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3945864550 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3945864550 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3945864550 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3945864550 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47623 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47623 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47623 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47623 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88823000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88823000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4476002926 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4476002926 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4564825926 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4564825926 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4564825926 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4564825926 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73355.068584 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73355.068584 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 83038.346918 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 83038.346918 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82854.538678 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82854.538678 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98364.341085 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 98364.341085 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95804.857149 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 95804.857149 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,413 +393,413 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 459902894 # number of cpu cycles simulated +system.cpu.numCycles 473010428 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90033870 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90033870 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1172024 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84304215 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81702749 # Number of BTB hits +system.cpu.BPredUnit.lookups 90027775 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90027775 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1176793 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84224638 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81706962 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29359737 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 447000113 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90033870 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81702749 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 169792580 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5290860 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 149776 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97806900 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37530 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 36600 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 214 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9375679 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 523969 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5232 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 301265833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.919513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.390338 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31360026 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 446936699 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90027775 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81706962 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169789390 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5321789 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 167863 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 104601282 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 44086 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9371006 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 537925 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5262 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 310106612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.836098 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376721 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131910949 43.79% 43.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1767278 0.59% 44.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72780383 24.16% 68.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 988082 0.33% 68.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1637864 0.54% 69.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3667894 1.22% 70.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1147346 0.38% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1446143 0.48% 71.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85919894 28.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140752877 45.39% 45.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1771842 0.57% 45.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72784841 23.47% 69.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 985545 0.32% 69.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1639332 0.53% 70.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3672529 1.18% 71.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1138013 0.37% 71.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1446532 0.47% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85915101 27.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 301265833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.195767 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.971945 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34474494 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93907388 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 163990791 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4810664 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4082496 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 876264710 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4082496 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38727929 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39278399 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10114969 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 164053704 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45008336 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 872424503 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9763 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 34576608 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3790570 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31863881 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1394114241 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2488384373 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2488383477 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1347565425 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46548809 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 469868 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476809 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46309775 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 18907776 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10445518 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1298255 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1025454 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 865635268 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1719822 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 864337626 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112774 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25913081 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 53108345 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 204185 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 301265833 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.869020 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.387854 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 310106612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.190329 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.944877 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36504487 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100689087 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164100014 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4706777 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4106247 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876222772 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 974 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4106247 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 40918052 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 44290154 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10988643 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 163783570 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46019946 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872439032 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9880 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 35250675 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3950071 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31995010 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1394183444 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2488413838 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2488413278 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1347594272 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 46589165 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 477213 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48119615 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18916713 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10445823 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1292985 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1005726 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865744936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1721292 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864337925 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 123293 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26001434 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 53514506 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 205573 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 310106612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.787228 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.396179 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 94932773 31.51% 31.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22142074 7.35% 38.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 18888671 6.27% 45.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7860945 2.61% 47.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 80656411 26.77% 74.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3302785 1.10% 75.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72810465 24.17% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 540656 0.18% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 131053 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 102391332 33.02% 33.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23760486 7.66% 40.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 19024925 6.13% 46.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7818761 2.52% 49.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 80618326 26.00% 75.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3106091 1.00% 76.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72752494 23.46% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 520993 0.17% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 113204 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 301265833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 310106612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 170381 8.07% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1776523 84.09% 92.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 165648 7.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 162823 7.80% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1765220 84.55% 92.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159742 7.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 297256 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 829421724 95.96% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25169917 2.91% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9448729 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 296671 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829442170 95.96% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25162510 2.91% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9436574 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 864337626 # Type of FU issued -system.cpu.iq.rate 1.879392 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2112552 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002444 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2032304206 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 893278706 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 853918308 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 381 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 418 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 98 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 866152744 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 178 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1572054 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 864337925 # Type of FU issued +system.cpu.iq.rate 1.827313 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2087785 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002415 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2041131934 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893478671 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 853934886 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866128931 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1577690 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3603717 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21501 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11898 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2033136 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3621025 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20103 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12189 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2042088 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821637 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2389 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821421 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4286 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4082496 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25489851 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1396862 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 867355090 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 297196 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 18907776 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10445518 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 881207 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 698514 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12367 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11898 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 698869 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 624345 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1323214 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 862415633 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24733940 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1921992 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4106247 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27916479 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1927801 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867466228 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 303428 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18916713 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10445834 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 882766 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 975199 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12189 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 699297 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 625213 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1324510 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862446659 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24735217 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1891265 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 33937040 # number of memory reference insts executed -system.cpu.iew.exec_branches 86496224 # Number of branches executed -system.cpu.iew.exec_stores 9203100 # Number of stores executed -system.cpu.iew.exec_rate 1.875212 # Inst execution rate -system.cpu.iew.wb_sent 861954133 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 853918406 # cumulative count of insts written-back -system.cpu.iew.wb_producers 669978264 # num instructions producing a value -system.cpu.iew.wb_consumers 1919317191 # num instructions consuming a value +system.cpu.iew.exec_refs 33929559 # number of memory reference insts executed +system.cpu.iew.exec_branches 86496146 # Number of branches executed +system.cpu.iew.exec_stores 9194342 # Number of stores executed +system.cpu.iew.exec_rate 1.823314 # Inst execution rate +system.cpu.iew.wb_sent 861961974 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 853934949 # cumulative count of insts written-back +system.cpu.iew.wb_producers 669649521 # num instructions producing a value +system.cpu.iew.wb_consumers 1918783501 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.856736 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.349071 # average fanout of values written-back +system.cpu.iew.wb_rate 1.805319 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.348997 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426532736 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840526050 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26723975 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1515635 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1176103 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 297198870 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.828160 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.864352 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426531587 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840543055 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26818803 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1515717 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1181719 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 306015924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.746730 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.861261 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 116541377 39.21% 39.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14339767 4.82% 44.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4295097 1.45% 45.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76671720 25.80% 71.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3910835 1.32% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1786901 0.60% 73.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1117084 0.38% 73.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71988132 24.22% 97.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6547957 2.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 125070317 40.87% 40.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14726015 4.81% 45.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4257326 1.39% 47.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76646045 25.05% 72.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3895754 1.27% 73.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1793252 0.59% 73.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1102852 0.36% 74.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71997039 23.53% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6527324 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 297198870 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426532736 # Number of instructions committed -system.cpu.commit.committedOps 840526050 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 306015924 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426531587 # Number of instructions committed +system.cpu.commit.committedOps 840543055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23716438 # Number of memory references committed -system.cpu.commit.loads 15304056 # Number of loads committed -system.cpu.commit.membars 781569 # Number of memory barriers committed -system.cpu.commit.branches 85505804 # Number of branches committed +system.cpu.commit.refs 23699431 # Number of memory references committed +system.cpu.commit.loads 15295685 # Number of loads committed +system.cpu.commit.membars 781577 # Number of memory barriers committed +system.cpu.commit.branches 85508404 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768351683 # Number of committed integer instructions. +system.cpu.commit.int_insts 768361520 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6547957 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6527324 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1157821631 # The number of ROB reads -system.cpu.rob.rob_writes 1738597524 # The number of ROB writes -system.cpu.timesIdled 2901104 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 158637061 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9834920608 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426532736 # Number of Instructions Simulated -system.cpu.committedOps 840526050 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426532736 # Number of Instructions Simulated -system.cpu.cpi 1.078236 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.078236 # CPI: Total CPI of All Threads -system.cpu.ipc 0.927441 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.927441 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2163268420 # number of integer regfile reads -system.cpu.int_regfile_writes 1362711366 # number of integer regfile writes -system.cpu.fp_regfile_reads 98 # number of floating regfile reads -system.cpu.misc_regfile_reads 281060274 # number of misc regfile reads -system.cpu.misc_regfile_writes 403581 # number of misc regfile writes -system.cpu.icache.replacements 1071746 # number of replacements -system.cpu.icache.tagsinuse 509.688073 # Cycle average of tags in use -system.cpu.icache.total_refs 8235470 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1072258 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.680493 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56594855000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.688073 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995485 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995485 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8235470 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8235470 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8235470 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8235470 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8235470 # number of overall hits -system.cpu.icache.overall_hits::total 8235470 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1140205 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1140205 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1140205 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1140205 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1140205 # number of overall misses -system.cpu.icache.overall_misses::total 1140205 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16916733991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16916733991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16916733991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16916733991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16916733991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16916733991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9375675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9375675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9375675 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9375675 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9375675 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9375675 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121613 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121613 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121613 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121613 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121613 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121613 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14836.572363 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14836.572363 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14836.572363 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14836.572363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14836.572363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14836.572363 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2216492 # number of cycles access was blocked +system.cpu.rob.rob_reads 1166770942 # The number of ROB reads +system.cpu.rob.rob_writes 1738844954 # The number of ROB writes +system.cpu.timesIdled 2997386 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 162903816 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9874668492 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426531587 # Number of Instructions Simulated +system.cpu.committedOps 840543055 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426531587 # Number of Instructions Simulated +system.cpu.cpi 1.108969 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108969 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901738 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.901738 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2163215430 # number of integer regfile reads +system.cpu.int_regfile_writes 1362691420 # number of integer regfile writes +system.cpu.fp_regfile_reads 63 # number of floating regfile reads +system.cpu.misc_regfile_reads 281069935 # number of misc regfile reads +system.cpu.misc_regfile_writes 403791 # number of misc regfile writes +system.cpu.icache.replacements 1071897 # number of replacements +system.cpu.icache.tagsinuse 510.429584 # Cycle average of tags in use +system.cpu.icache.total_refs 8228054 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1072409 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.672496 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56932855000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.429584 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996933 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996933 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8228054 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8228054 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8228054 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8228054 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8228054 # number of overall hits +system.cpu.icache.overall_hits::total 8228054 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1142948 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1142948 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1142948 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1142948 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1142948 # number of overall misses +system.cpu.icache.overall_misses::total 1142948 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18865193488 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18865193488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18865193488 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18865193488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18865193488 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18865193488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9371002 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9371002 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9371002 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9371002 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9371002 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9371002 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121966 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121966 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121966 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.121966 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.121966 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.121966 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16505.732096 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16505.732096 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16505.732096 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16505.732096 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3301994 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 399 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9197.062241 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8275.674185 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1572 # number of writebacks -system.cpu.icache.writebacks::total 1572 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67614 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67614 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67614 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67614 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67614 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67614 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072591 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1072591 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1072591 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1072591 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1072591 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1072591 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12848213492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12848213492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12848213492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12848213492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12848213492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12848213492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114401 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114401 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114401 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114401 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114401 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114401 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11978.669868 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11978.669868 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11978.669868 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11978.669868 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11978.669868 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11978.669868 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1600 # number of writebacks +system.cpu.icache.writebacks::total 1600 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70415 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70415 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70415 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70415 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70415 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70415 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072533 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1072533 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1072533 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1072533 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1072533 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1072533 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14734319994 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14734319994 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14734319994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14734319994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14734319994 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14734319994 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114452 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114452 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114452 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13737.870997 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13737.870997 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 12981 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.013322 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25373 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 12993 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 1.952821 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5123561713000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.013322 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375833 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375833 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25418 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25418 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 11177 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.030365 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 31227 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 11191 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.790367 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5136145388000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.030365 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376898 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376898 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31228 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 31228 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25421 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25421 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25421 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25421 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 13864 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 13864 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 13864 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 13864 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 13864 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 13864 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 165480500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 165480500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 165480500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 165480500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 165480500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 165480500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39282 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 39282 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31231 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 31231 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31231 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 31231 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12057 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 12057 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12057 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 12057 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12057 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 12057 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 192652500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 192652500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 192652500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 192652500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 192652500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 192652500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43285 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 43285 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39285 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 39285 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39285 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 39285 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352935 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352935 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352908 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.352908 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352908 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.352908 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11935.985286 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11935.985286 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11935.985286 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11935.985286 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11935.985286 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11935.985286 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43288 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 43288 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43288 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 43288 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.278549 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.278549 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.278530 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.278530 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.278530 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.278530 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 15978.477233 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 15978.477233 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 15978.477233 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 15978.477233 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,78 +808,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1460 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1460 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 13864 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 13864 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 13864 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 13864 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 13864 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 13864 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 123445500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 123445500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 123445500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 123445500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 123445500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 123445500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352935 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352935 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352908 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352908 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352908 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352908 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8904.032025 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8904.032025 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8904.032025 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1620 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1620 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12057 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12057 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12057 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 12057 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12057 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 12057 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155859527 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155859527 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155859527 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155859527 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155859527 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155859527 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.278549 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.278549 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.278530 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.278530 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12926.891184 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 120380 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.933344 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 133363 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 120396 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.107703 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5104613509000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.933344 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808334 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.808334 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 133363 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 133363 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 133363 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 133363 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 133363 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 133363 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 121457 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 121457 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 121457 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 121457 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 121457 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 121457 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1679660000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1679660000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1679660000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1679660000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1679660000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1679660000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 254820 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 254820 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 254820 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 254820 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 254820 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 254820 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.476638 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.476638 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.476638 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.476638 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.476638 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.476638 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13829.256445 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13829.256445 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13829.256445 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13829.256445 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13829.256445 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13829.256445 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 116226 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.942586 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 138119 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 116242 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.188202 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5112881220000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.942586 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808912 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.808912 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138119 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 138119 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138119 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 138119 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138119 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 138119 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117277 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 117277 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117277 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 117277 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117277 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 117277 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2115105000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2115105000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2115105000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2115105000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2115105000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2115105000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255396 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 255396 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255396 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 255396 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255396 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 255396 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.459197 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.459197 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.459197 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.459197 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.459197 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.459197 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18035.121976 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18035.121976 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18035.121976 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18035.121976 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,146 +888,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 37082 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 37082 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 121457 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 121457 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 121457 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 121457 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 121457 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 121457 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1312360500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1312360500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1312360500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.476638 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.476638 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.476638 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10805.145031 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10805.145031 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10805.145031 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 36600 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 36600 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117277 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117277 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117277 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 117277 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117277 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 117277 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1760668506 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1760668506 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1760668506 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.459197 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.459197 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.459197 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15012.905395 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1670972 # number of replacements -system.cpu.dcache.tagsinuse 511.998179 # Cycle average of tags in use -system.cpu.dcache.total_refs 19056575 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1671484 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.400992 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998179 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10967822 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10967822 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8085914 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8085914 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19053736 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19053736 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19053736 # number of overall hits -system.cpu.dcache.overall_hits::total 19053736 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2407391 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2407391 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2724500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2724500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2724500 # number of overall misses -system.cpu.dcache.overall_misses::total 2724500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35545734500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35545734500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10083377990 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10083377990 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45629112490 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45629112490 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45629112490 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45629112490 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13375213 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13375213 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8403023 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8403023 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21778236 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21778236 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21778236 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21778236 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.179989 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.179989 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037737 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037737 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.125102 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.125102 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.125102 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.125102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.251885 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.251885 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31797.829737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31797.829737 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16747.701409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16747.701409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16747.701409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16747.701409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19144990 # number of cycles access was blocked +system.cpu.dcache.replacements 1674194 # number of replacements +system.cpu.dcache.tagsinuse 511.997520 # Cycle average of tags in use +system.cpu.dcache.total_refs 19015880 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1674706 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.354757 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997520 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10936415 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10936415 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8076863 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8076863 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19013278 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19013278 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19013278 # number of overall hits +system.cpu.dcache.overall_hits::total 19013278 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2432524 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2432524 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317516 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317516 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2750040 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2750040 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2750040 # number of overall misses +system.cpu.dcache.overall_misses::total 2750040 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45245018000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45245018000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10626959991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10626959991 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55871977991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55871977991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55871977991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55871977991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13368939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13368939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8394379 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8394379 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21763318 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21763318 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21763318 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21763318 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181953 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.181953 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037825 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.126361 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.126361 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.126361 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.126361 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18600.029434 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18600.029434 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33469.053500 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33469.053500 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.787389 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20316.787389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.787389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20316.787389 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26625491 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3356 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4915 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5704.705006 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5417.190437 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1570390 # number of writebacks -system.cpu.dcache.writebacks::total 1570390 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1028077 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1028077 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22422 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22422 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1050499 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1050499 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1050499 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1050499 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1379314 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1379314 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294687 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 294687 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1674001 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1674001 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1674001 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1674001 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17753874500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17753874500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8876538990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8876538990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26630413490 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26630413490 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26630413490 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26630413490 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208379000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208379000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1393915000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1393915000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86602294000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86602294000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103125 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103125 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035069 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035069 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076866 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076866 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076866 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076866 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.524903 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.524903 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30121.922548 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30121.922548 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15908.242283 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15908.242283 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15908.242283 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15908.242283 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1573630 # number of writebacks +system.cpu.dcache.writebacks::total 1573630 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1050273 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1050273 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22706 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22706 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1072979 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1072979 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1072979 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1072979 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1382251 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1382251 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294810 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 294810 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1677061 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1677061 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1677061 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1677061 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23310362534 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23310362534 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9362745997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9362745997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32673108531 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32673108531 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32673108531 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32673108531 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207340500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207340500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386118500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386118500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86593459000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86593459000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103393 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103393 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035120 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035120 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077059 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077059 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16864.059085 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16864.059085 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31758.576700 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31758.576700 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini index c9fc9d3a5..d219b0faf 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini @@ -1190,7 +1190,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.pc.pciconfig.pio master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index d6cb455f2..9c27e2eb7 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:12 -gem5 started Jun 4 2012 17:11:29 +gem5 compiled Jul 2 2012 09:03:01 +gem5 started Jul 2 2012 15:09:17 gem5 executing on zizzer -command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory +command line: build/X86_MESI_CMP_directory/gem5.fast -d build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5304689685500 because m5_exit instruction encountered +Exiting @ tick 5305568291500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index b7d143468..b9331fa8f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.304690 # Number of seconds simulated -sim_ticks 5304689685500 # Number of ticks simulated -final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.305568 # Number of seconds simulated +sim_ticks 5305568291500 # Number of ticks simulated +final_tick 5305568291500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163049 # Simulator instruction rate (inst/s) -host_op_rate 333085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6301127704 # Simulator tick rate (ticks/s) -host_mem_usage 481488 # Number of bytes of host memory used -host_seconds 841.86 # Real time elapsed on the host -sim_insts 137264752 # Number of instructions simulated -sim_ops 280412254 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory -system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory +host_inst_rate 254586 # Simulator instruction rate (inst/s) +host_op_rate 522269 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9722568027 # Simulator tick rate (ticks/s) +host_mem_usage 466304 # Number of bytes of host memory used +host_seconds 545.70 # Real time elapsed on the host +sim_insts 138926459 # Number of instructions simulated +sim_ops 285000258 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 131880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 65368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 843624624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 40107648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 91872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 42696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 468878472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 53485285 # Number of bytes read from this memory +system.physmem.bytes_read::total 1406463005 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 843624624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 468878472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1312503096 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory -system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 32434308 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 35512736 # Number of bytes written to this memory +system.physmem.bytes_written::total 70938164 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 16485 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 105453078 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6721984 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58609809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8980290 # Number of read requests responded to by this memory +system.physmem.num_reads::total 179807449 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 4872641 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4951979 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9871358 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 24857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 12321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 159007401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7559539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 17316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8047 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 88374788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10080972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 265091867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 159007401 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 88374788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247382189 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563767 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6113258 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6693484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13370512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 24857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 12324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 159007401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13672797 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 17316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8047 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 88374788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16774456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 278462379 # Total bandwidth to/from this memory (bytes/s) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -84,52 +84,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10608177450 # number of cpu cycles simulated +system.cpu0.numCycles 10611136583 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 88690468 # Number of instructions committed -system.cpu0.committedOps 187060545 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 168469813 # Number of integer alu accesses +system.cpu0.committedInsts 90467543 # Number of instructions committed +system.cpu0.committedOps 191745753 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 172320951 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls -system.cpu0.num_int_insts 168469813 # number of integer instructions +system.cpu0.num_conditional_control_insts 18433460 # number of instructions that are conditional controls +system.cpu0.num_int_insts 172320951 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read -system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written +system.cpu0.num_int_register_reads 529440727 # number of times the integer registers were read +system.cpu0.num_int_register_writes 286411795 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 19132508 # number of memory refs -system.cpu0.num_load_insts 14284566 # Number of load instructions -system.cpu0.num_store_insts 4847942 # Number of store instructions -system.cpu0.num_idle_cycles 10086452980.871330 # Number of idle cycles -system.cpu0.num_busy_cycles 521724469.128670 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049181 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950819 # Percentage of idle cycles +system.cpu0.num_mem_refs 19683524 # number of memory refs +system.cpu0.num_load_insts 14800104 # Number of load instructions +system.cpu0.num_store_insts 4883420 # Number of store instructions +system.cpu0.num_idle_cycles 10087380547.886099 # Number of idle cycles +system.cpu0.num_busy_cycles 523756035.113901 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049359 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950641 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10609379371 # number of cpu cycles simulated +system.cpu1.numCycles 10608184508 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48574284 # Number of instructions committed -system.cpu1.committedOps 93351709 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 89110416 # Number of integer alu accesses +system.cpu1.committedInsts 48458916 # Number of instructions committed +system.cpu1.committedOps 93254505 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88898001 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls -system.cpu1.num_int_insts 89110416 # number of integer instructions +system.cpu1.num_conditional_control_insts 8156206 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88898001 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read -system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written +system.cpu1.num_int_register_reads 272266493 # number of times the integer registers were read +system.cpu1.num_int_register_writes 138281277 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 14426742 # number of memory refs -system.cpu1.num_load_insts 9181010 # Number of load instructions -system.cpu1.num_store_insts 5245732 # Number of store instructions -system.cpu1.num_idle_cycles 10273661233.326063 # Number of idle cycles -system.cpu1.num_busy_cycles 335718137.673937 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031644 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968356 # Percentage of idle cycles +system.cpu1.num_mem_refs 14383510 # number of memory refs +system.cpu1.num_load_insts 9129721 # Number of load instructions +system.cpu1.num_store_insts 5253789 # Number of store instructions +system.cpu1.num_idle_cycles 10274260882.632458 # Number of idle cycles +system.cpu1.num_busy_cycles 333923625.367543 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031478 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968522 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |