diff options
Diffstat (limited to 'tests/long/fs')
9 files changed, 2792 insertions, 2792 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index e59e9b3f5..f7596e329 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -17,7 +17,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -661,8 +661,8 @@ voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table -children=entries0 entries1 entries2 -entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 +children=entries0 entries1 entries2 entries3 +entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 [system.e820_table.entries0] type=X86E820Entry @@ -682,6 +682,12 @@ addr=1048576 range_type=1 size=133169152 +[system.e820_table.entries3] +type=X86E820Entry +addr=4294901760 +range_type=2 +size=65536 + [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 @@ -1350,7 +1356,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/andreas/m5/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1370,7 +1376,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/andreas/m5/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index a681181ed..96081bfab 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -3,7 +3,6 @@ warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. -warn: instruction 'fxsave' unimplemented warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unimplemented function 8 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 332ea85eb..c5fec8887 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:54:38 -gem5 executing on zizzer +gem5 compiled Oct 1 2013 21:55:52 +gem5 started Oct 1 2013 22:49:39 +gem5 executing on steam command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5133762710000 because m5_exit instruction encountered +Exiting @ tick 5133817564000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 610192884..e1d1abdbc 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133763 # Number of seconds simulated -sim_ticks 5133762710000 # Number of ticks simulated -final_tick 5133762710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133818 # Number of seconds simulated +sim_ticks 5133817564000 # Number of ticks simulated +final_tick 5133817564000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156198 # Simulator instruction rate (inst/s) -host_op_rate 308758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1966557914 # Simulator tick rate (ticks/s) -host_mem_usage 728732 # Number of bytes of host memory used -host_seconds 2610.53 # Real time elapsed on the host -sim_insts 407759186 # Number of instructions simulated -sim_ops 806023868 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2444032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1025408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10767936 # Number of bytes read from this memory -system.physmem.bytes_read::total 14241664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1025408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1025408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9508160 # Number of bytes written to this memory -system.physmem.bytes_written::total 9508160 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16022 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168249 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222526 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148565 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148565 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 199738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2097474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2774118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1852084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1852084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1852084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2097474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4626202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222526 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 148565 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 222526 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 148565 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 14241664 # Total number of bytes read from memory -system.physmem.bytesWritten 9508160 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14241664 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9508160 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 1733 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14338 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13735 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 14393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 13573 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13628 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13175 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 13794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13620 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13949 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13975 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14348 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 14346 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 13392 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9773 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 9207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 9622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 9014 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9405 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 9183 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8703 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9254 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 9156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9240 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 9684 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9527 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 9658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8799 # Track writes on a per bank basis +host_inst_rate 116267 # Simulator instruction rate (inst/s) +host_op_rate 229827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1463849171 # Simulator tick rate (ticks/s) +host_mem_usage 730944 # Number of bytes of host memory used +host_seconds 3507.07 # Real time elapsed on the host +sim_insts 407756178 # Number of instructions simulated +sim_ops 806017145 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2427456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1027392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10775296 # Number of bytes read from this memory +system.physmem.bytes_read::total 14234240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1027392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1027392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9523712 # Number of bytes written to this memory +system.physmem.bytes_written::total 9523712 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16053 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168364 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222410 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148808 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148808 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 472836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2098886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2772642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1855094 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1855094 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1855094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 472836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 200122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2098886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4627736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222410 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 148808 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 222410 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 148808 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 14234240 # Total number of bytes read from memory +system.physmem.bytesWritten 9523712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14234240 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9523712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 1680 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14445 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 14292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 13655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13870 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13478 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14003 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13556 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13489 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 14708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 14115 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 13636 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9830 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 9327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 9583 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 9096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 9291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8927 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9335 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9016 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8994 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 9147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 9992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9572 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 9603 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 9152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry -system.physmem.totGap 5133762656000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 5133817509500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 222526 # Categorize read packet sizes +system.physmem.readPktSize::6 222410 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 148565 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 174531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148808 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 174478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -137,336 +137,342 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62801 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 377.966975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.936826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1272.632195 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 27908 44.44% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 9784 15.58% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 5938 9.46% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 3957 6.30% 75.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2545 4.05% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 2018 3.21% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1524 2.43% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1187 1.89% 87.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 1022 1.63% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 897 1.43% 90.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 594 0.95% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 559 0.89% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 423 0.67% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 383 0.61% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 375 0.60% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 421 0.67% 94.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 292 0.46% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 205 0.33% 95.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 163 0.26% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 146 0.23% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 144 0.23% 96.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 476 0.76% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 183 0.29% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 124 0.20% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 88 0.14% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 60 0.10% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 51 0.08% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 42 0.07% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 29 0.05% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 32 0.05% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 30 0.05% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 17 0.03% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 11 0.02% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 16 0.03% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 10 0.02% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 13 0.02% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 7 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 8 0.01% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.00% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 6 0.01% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 6 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 8 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 4 0.01% 98.62% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 5406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62679 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 378.930359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.401970 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1268.483208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 27823 44.39% 44.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 9775 15.60% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5839 9.32% 69.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3939 6.28% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2540 4.05% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2068 3.30% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1534 2.45% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1237 1.97% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 969 1.55% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 885 1.41% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 570 0.91% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 566 0.90% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 409 0.65% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 368 0.59% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 359 0.57% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 470 0.75% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 261 0.42% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 223 0.36% 95.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 183 0.29% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 154 0.25% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 153 0.24% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 166 0.26% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 503 0.80% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 192 0.31% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 116 0.19% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 97 0.15% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 69 0.11% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 63 0.10% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 31 0.05% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 26 0.04% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 27 0.04% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 24 0.04% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 21 0.03% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 14 0.02% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 16 0.03% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 18 0.03% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 13 0.02% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 7 0.01% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 6 0.01% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 5 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 7 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 8 0.01% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 3 0.00% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 4 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 4 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 8 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 4 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.00% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 3 0.00% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 8 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 27 0.04% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 3 0.00% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 4 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 3 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 3 0.00% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 8 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 6 0.01% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 2 0.00% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 10 0.02% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 4 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 2 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 4 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 25 0.04% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 7 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 2 0.00% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 5 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 5 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 5 0.01% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 4 0.01% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 6 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 2 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 2 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 2 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 3 0.00% 98.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 3 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 2 0.00% 98.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 5 0.01% 98.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 2 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 2 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 4 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 3 0.00% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 3 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 3 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 4 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 4 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 10 0.02% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 3 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 2 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 2 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 5 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 3 0.00% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 8 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 2 0.00% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 3 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 4 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 340 0.54% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 3 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 3 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 33 0.05% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 11 0.02% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 12 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 9 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 8 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 5 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 3 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 7 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 32 0.05% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 7 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 11 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 5 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 6 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 5 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 9 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 3 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 8 0.01% 99.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::15936-15939 3 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 10 0.02% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 5 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 6 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 10 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 63 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 8 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 8 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 15 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 59 0.09% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18371 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62801 # Bytes accessed per row activation -system.physmem.totQLat 4020206249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8301079999 # Sum of mem lat for all requests -system.physmem.totBusLat 1112255000 # Total cycles spent in databus access -system.physmem.totBankLat 3168618750 # Total cycles spent in bank access -system.physmem.avgQLat 18072.32 # Average queueing delay per request -system.physmem.avgBankLat 14244.12 # Average bank access latency per request +system.physmem.bytesPerActivate::17792-17795 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62679 # Bytes accessed per row activation +system.physmem.totQLat 3976321749 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8255787999 # Sum of mem lat for all requests +system.physmem.totBusLat 1111755000 # Total cycles spent in databus access +system.physmem.totBankLat 3167711250 # Total cycles spent in bank access +system.physmem.avgQLat 17883.08 # Average queueing delay per request +system.physmem.avgBankLat 14246.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37316.44 # Average memory access latency +system.physmem.avgMemAccLat 37129.53 # Average memory access latency system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 13.16 # Average write queue length over time -system.physmem.readRowHits 198897 # Number of row buffer hits during reads -system.physmem.writeRowHits 109310 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes -system.physmem.avgGap 13834241.89 # Average gap between requests -system.membus.throughput 5102506 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662304 # Transaction distribution -system.membus.trans_dist::ReadResp 662304 # Transaction distribution -system.membus.trans_dist::WriteReq 13698 # Transaction distribution -system.membus.trans_dist::WriteResp 13698 # Transaction distribution -system.membus.trans_dist::Writeback 148565 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2229 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1751 # Transaction distribution -system.membus.trans_dist::ReadExReq 179560 # Transaction distribution -system.membus.trans_dist::ReadExResp 179558 # Transaction distribution -system.membus.trans_dist::MessageReq 1642 # Transaction distribution -system.membus.trans_dist::MessageResp 1642 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1856826 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20110919 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5430720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5430720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25548207 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25548207 # Total data (bytes) -system.membus.snoop_data_through_bus 646848 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250293000 # Layer occupancy (ticks) +system.physmem.avgWrQLen 11.10 # Average write queue length over time +system.physmem.readRowHits 198876 # Number of row buffer hits during reads +system.physmem.writeRowHits 109583 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.64 # Row buffer hit rate for writes +system.physmem.avgGap 13829656.72 # Average gap between requests +system.membus.throughput 5107370 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662136 # Transaction distribution +system.membus.trans_dist::ReadResp 662131 # Transaction distribution +system.membus.trans_dist::WriteReq 13778 # Transaction distribution +system.membus.trans_dist::WriteResp 13778 # Transaction distribution +system.membus.trans_dist::Writeback 148808 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2204 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution +system.membus.trans_dist::ReadExReq 179955 # Transaction distribution +system.membus.trans_dist::ReadExResp 179952 # Transaction distribution +system.membus.trans_dist::MessageReq 1643 # Transaction distribution +system.membus.trans_dist::MessageResp 1643 # Transaction distribution +system.membus.trans_dist::BadAddressError 5 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132231 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132231 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1857341 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18343808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20135781 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5414144 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5414144 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25556497 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25556497 # Total data (bytes) +system.membus.snoop_data_through_bus 663808 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250614500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583289000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583282500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1608355497 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1610621247 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3156883661 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3158121946 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429399995 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429462997 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47574 # number of replacements -system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use +system.iocache.tags.replacements 47580 # number of replacements +system.iocache.tags.tagsinuse 0.104004 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103958 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006497 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.tags.warmup_cycle 4992837152000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.104004 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006500 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006500 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses +system.iocache.ReadReq_misses::total 915 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151796185 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 151796185 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10322328602 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10322328602 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10474124787 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10474124787 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10474124787 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10474124787 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47635 # number of demand (read+write) misses +system.iocache.demand_misses::total 47635 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47635 # number of overall misses +system.iocache.overall_misses::total 47635 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 155029196 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 155029196 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10272164340 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10272164340 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10427193536 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10427193536 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10427193536 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10427193536 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47635 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47635 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47635 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47635 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -475,40 +481,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166992.502750 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 166992.502750 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 220940.252611 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 220940.252611 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 219910.659199 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 219910.659199 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 148616 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169430.815301 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 169430.815301 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 219866.531250 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 219866.531250 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 218897.733515 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 218897.733515 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 218897.733515 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 218897.733515 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 145846 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13635 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13667 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.899597 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.671398 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104494685 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104494685 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7891444112 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7891444112 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7995938797 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7995938797 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47635 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47635 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47635 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47635 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 107414696 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 107414696 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7841262846 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7841262846 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7948677542 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7948677542 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7948677542 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7948677542 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -517,18 +523,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114955.649065 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 114955.649065 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 168909.334589 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 168909.334589 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117393.110383 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117393.110383 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 167835.249272 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 167835.249272 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 166866.328162 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 166866.328162 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 166866.328162 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 166866.328162 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -538,16 +544,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 638140 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225493 # Transaction distribution -system.iobus.trans_dist::ReadResp 225493 # Transaction distribution -system.iobus.trans_dist::WriteReq 57527 # Transaction distribution -system.iobus.trans_dist::WriteResp 57527 # Transaction distribution -system.iobus.trans_dist::MessageReq 1642 # Transaction distribution -system.iobus.trans_dist::MessageResp 1642 # Transaction distribution +system.iobus.throughput 638173 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225571 # Transaction distribution +system.iobus.trans_dist::ReadResp 225571 # Transaction distribution +system.iobus.trans_dist::WriteReq 57606 # Transaction distribution +system.iobus.trans_dist::WriteResp 57606 # Transaction distribution +system.iobus.trans_dist::MessageReq 1643 # Transaction distribution +system.iobus.trans_dist::MessageResp 1643 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -557,21 +563,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569324 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -581,26 +587,26 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.p system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276058 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276058 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3920600 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276264 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3919850 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -620,7 +626,7 @@ system.iobus.reqLayer11.occupancy 170000 # La system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -630,454 +636,455 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424430792 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424475539 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53423005 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53455003 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85618831 # Number of BP lookups -system.cpu.branchPred.condPredicted 85618831 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 881906 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79126559 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77540225 # Number of BTB hits +system.cpu.branchPred.lookups 85568278 # Number of BP lookups +system.cpu.branchPred.condPredicted 85568278 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 875805 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79194721 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77515005 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.995194 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1441540 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180626 # Number of incorrect RAS predictions. -system.cpu.numCycles 453839632 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.879005 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1436703 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179530 # Number of incorrect RAS predictions. +system.cpu.numCycles 453826303 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25514423 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422776164 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85618831 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78981765 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162666633 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3997481 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 100403 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 71304729 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 44393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 94570 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 219 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8483452 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 380361 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2201 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262796476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.177336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25491689 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422571983 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85568278 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78951708 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162597841 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3951278 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 103753 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71390541 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 42483 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 91488 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 407 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8456173 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 381386 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2285 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262749158 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.176501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411322 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100544783 38.26% 38.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1535684 0.58% 38.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71830288 27.33% 66.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 894888 0.34% 66.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1570094 0.60% 67.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2394528 0.91% 68.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1014297 0.39% 68.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1322217 0.50% 68.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81689697 31.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100566215 38.27% 38.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1530086 0.58% 38.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71818264 27.33% 66.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 889095 0.34% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1565087 0.60% 67.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2386199 0.91% 68.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1016423 0.39% 68.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1323196 0.50% 68.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81654593 31.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262796476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188654 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.931554 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29415381 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68460720 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158509709 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3339560 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3071106 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832655242 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 935 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3071106 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32114015 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43120028 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12611794 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158799152 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13080381 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829727330 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21673 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6047730 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5146675 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 9377 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 991375726 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800594508 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1800594068 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 440 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963942859 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27432865 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 453030 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 459006 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29568179 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16736842 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9827220 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1098890 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 921986 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824947174 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1184809 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820992991 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 145624 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19292542 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29357019 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 130694 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262796476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.124064 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400943 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262749158 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188549 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931132 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29394099 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68537094 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158445926 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3341083 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3030956 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832311849 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 975 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3030956 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32089229 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43247389 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12548061 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158740332 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13093191 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829412646 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22400 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6072204 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5134846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 9895 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 991013941 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1799757815 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1799757415 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 400 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963928798 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27085141 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 453471 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459839 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29598553 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16699186 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9813003 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1103116 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 919400 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824665019 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1185670 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820786759 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 149059 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19014850 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28966021 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 131061 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262749158 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.123842 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.400884 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76438982 29.09% 29.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15751400 5.99% 35.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10538627 4.01% 39.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7358771 2.80% 41.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75737390 28.82% 70.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3750331 1.43% 72.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72306613 27.51% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 767765 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 146597 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76415434 29.08% 29.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15773446 6.00% 35.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10534030 4.01% 39.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7363874 2.80% 41.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75721487 28.82% 70.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3737655 1.42% 72.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72289188 27.51% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 768072 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 145972 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262796476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262749158 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 351017 33.38% 33.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 33.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 348 0.03% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547344 52.04% 85.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152992 14.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 347595 33.06% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 298 0.03% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548989 52.22% 85.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 154170 14.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308184 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793508376 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149615 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124401 0.02% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17677574 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9224841 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308427 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793336759 96.66% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149572 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124334 0.02% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17650951 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9216716 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820992991 # Type of FU issued -system.cpu.iq.rate 1.808994 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1051702 # FU busy when requested +system.cpu.iq.FU_type_0::total 820786759 # Type of FU issued +system.cpu.iq.rate 1.808592 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1051293 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001281 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1906088677 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845434927 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817071068 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 189 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821736420 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 89 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1694381 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 1905631270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 844875947 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 816895262 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 170 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821529545 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 80 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1693324 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2750139 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17720 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12102 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1408836 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2710358 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18596 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11994 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1389490 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931381 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12080 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931520 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12323 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3071106 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31257120 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2152669 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826131983 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242676 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16736842 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9827220 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 690491 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620064 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13028 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12102 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 497258 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506632 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1003890 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819577252 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17369785 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1415738 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3030956 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31365465 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2153394 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 825850689 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 245046 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16699186 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9813003 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 690244 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620381 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14551 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11994 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 492991 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506844 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 999835 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819394540 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17351060 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1392218 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26409608 # number of memory reference insts executed -system.cpu.iew.exec_branches 83098710 # Number of branches executed -system.cpu.iew.exec_stores 9039823 # Number of stores executed -system.cpu.iew.exec_rate 1.805874 # Inst execution rate -system.cpu.iew.wb_sent 819172462 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817071124 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638600161 # num instructions producing a value -system.cpu.iew.wb_consumers 1043929120 # num instructions consuming a value +system.cpu.iew.exec_refs 26384270 # number of memory reference insts executed +system.cpu.iew.exec_branches 83073397 # Number of branches executed +system.cpu.iew.exec_stores 9033210 # Number of stores executed +system.cpu.iew.exec_rate 1.805525 # Inst execution rate +system.cpu.iew.wb_sent 818994723 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 816895310 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638461899 # num instructions producing a value +system.cpu.iew.wb_consumers 1043741013 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.800352 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800018 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611705 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19998846 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054115 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 892238 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259725370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.103370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863932 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19724455 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054609 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 885977 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259718202 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.103430 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863863 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88203628 33.96% 33.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11848657 4.56% 38.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3832219 1.48% 40.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74739253 28.78% 68.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2381920 0.92% 69.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1474779 0.57% 70.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 859132 0.33% 70.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70849609 27.28% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5536173 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88192844 33.96% 33.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11850002 4.56% 38.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3832476 1.48% 40.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74743456 28.78% 68.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2382743 0.92% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1477125 0.57% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 857323 0.33% 70.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70846576 27.28% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5535657 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259725370 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407759186 # Number of instructions committed -system.cpu.commit.committedOps 806023868 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259718202 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407756178 # Number of instructions committed +system.cpu.commit.committedOps 806017145 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22405086 # Number of memory references committed -system.cpu.commit.loads 13986702 # Number of loads committed -system.cpu.commit.membars 474409 # Number of memory barriers committed -system.cpu.commit.branches 82159690 # Number of branches committed +system.cpu.commit.refs 22412340 # Number of memory references committed +system.cpu.commit.loads 13988827 # Number of loads committed +system.cpu.commit.membars 474703 # Number of memory barriers committed +system.cpu.commit.branches 82157257 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735008844 # Number of committed integer instructions. -system.cpu.commit.function_calls 1154896 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5536173 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 735004802 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155200 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5535657 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080133651 # The number of ROB reads -system.cpu.rob.rob_writes 1655131261 # The number of ROB writes -system.cpu.timesIdled 1259877 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 191043156 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9813691352 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407759186 # Number of Instructions Simulated -system.cpu.committedOps 806023868 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407759186 # Number of Instructions Simulated -system.cpu.cpi 1.113009 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.113009 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898465 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898465 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1504423855 # number of integer regfile reads -system.cpu.int_regfile_writes 975340027 # number of integer regfile writes -system.cpu.fp_regfile_reads 56 # number of floating regfile reads -system.cpu.misc_regfile_reads 264091330 # number of misc regfile reads -system.cpu.misc_regfile_writes 402284 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53596956 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3010019 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3009469 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1583020 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2243 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2243 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288025 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1906694 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6122854 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 16266 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154977 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8200791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61010496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207591623 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 510912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5512832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 274625863 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274602311 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 551744 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4037956918 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1079845864 # The number of ROB reads +system.cpu.rob.rob_writes 1654528920 # The number of ROB writes +system.cpu.timesIdled 1259880 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 191077145 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9813814465 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407756178 # Number of Instructions Simulated +system.cpu.committedOps 806017145 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407756178 # Number of Instructions Simulated +system.cpu.cpi 1.112984 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112984 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898485 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898485 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1504160790 # number of integer regfile reads +system.cpu.int_regfile_writes 975149499 # number of integer regfile writes +system.cpu.fp_regfile_reads 48 # number of floating regfile reads +system.cpu.misc_regfile_reads 263996873 # number of misc regfile reads +system.cpu.misc_regfile_writes 402343 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53588361 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3012770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3012220 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1579976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2276 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2276 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334451 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287744 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1911499 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6119032 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17478 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 153515 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8201524 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61164352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207421989 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 548096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5363392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 274497829 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274473317 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 639552 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4034739870 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 552000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1434043234 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1437663197 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3142652791 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3140492264 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 12430241 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 13374496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 103328135 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 104626155 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 952820 # number of replacements -system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7477461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7477461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7477461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7477461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7477461 # number of overall hits -system.cpu.icache.overall_hits::total 7477461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1005989 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1005989 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1005989 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1005989 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1005989 # number of overall misses -system.cpu.icache.overall_misses::total 1005989 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232079935 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14232079935 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14232079935 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14232079935 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14232079935 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14232079935 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8483450 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8483450 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8483450 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8483450 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8483450 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8483450 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118583 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118583 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118583 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118583 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118583 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118583 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14147.351447 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14147.351447 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14147.351447 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14147.351447 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked +system.cpu.icache.tags.replacements 955225 # number of replacements +system.cpu.icache.tags.tagsinuse 509.955368 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7446917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 955737 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.791806 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147479365250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.955368 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996007 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996007 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7446917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7446917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7446917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7446917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7446917 # number of overall hits +system.cpu.icache.overall_hits::total 7446917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1009251 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1009251 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1009251 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1009251 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1009251 # number of overall misses +system.cpu.icache.overall_misses::total 1009251 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14258935392 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14258935392 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14258935392 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14258935392 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14258935392 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14258935392 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8456168 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8456168 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8456168 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8456168 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8456168 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8456168 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119351 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.119351 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.119351 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.119351 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.119351 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.119351 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14128.235089 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14128.235089 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14128.235089 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14128.235089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14128.235089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14128.235089 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6628 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 174 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 35.580460 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.943231 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52584 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52584 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52584 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52584 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52584 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52584 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953405 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 953405 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 953405 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 953405 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 953405 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 953405 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11737352011 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11737352011 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11737352011 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11737352011 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11737352011 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11737352011 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112384 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112384 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112384 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12310.982228 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12310.982228 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53445 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53445 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53445 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53445 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53445 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53445 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 955806 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 955806 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 955806 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 955806 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 955806 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 955806 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11762227547 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11762227547 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11762227547 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11762227547 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11762227547 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11762227547 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113031 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113031 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113031 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.113031 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113031 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.113031 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12306.082560 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12306.082560 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12306.082560 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12306.082560 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12306.082560 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12306.082560 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 7402 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 7416 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104253177000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006857 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375429 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.375429 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21911 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 21911 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 8028 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.311146 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21788 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 8039 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.710287 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5106556199500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.311146 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.394447 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.394447 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21802 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21802 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21913 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 21913 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21913 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 21913 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8283 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 8283 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8283 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 8283 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8283 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 8283 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 92582993 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 92582993 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 92582993 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 92582993 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 92582993 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 92582993 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30194 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30194 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21804 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21804 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21804 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21804 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8914 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8914 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8914 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8914 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8914 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8914 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 98082749 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 98082749 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 98082749 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 98082749 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 98082749 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 98082749 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30716 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30716 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30196 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30196 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30196 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30196 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.274326 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.274326 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.274308 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.274308 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.274308 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.274308 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11177.471085 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11177.471085 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11177.471085 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11177.471085 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11177.471085 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30718 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30718 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30718 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30718 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.290207 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.290207 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.290188 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.290188 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.290188 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.290188 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11003.225151 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11003.225151 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11003.225151 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11003.225151 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11003.225151 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11003.225151 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1086,78 +1093,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1499 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1499 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8283 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8283 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8283 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 8283 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8283 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 8283 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 76005511 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 76005511 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 76005511 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 76005511 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 76005511 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 76005511 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.274326 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.274326 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.274308 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.274308 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.274308 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.274308 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9176.084873 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1772 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1772 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8914 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8914 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8914 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8914 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8914 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80247757 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 80247757 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 80247757 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 80247757 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 80247757 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 80247757 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.290207 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.290207 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.290188 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.290188 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.290188 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.290188 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9002.440767 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9002.440767 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9002.440767 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9002.440767 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9002.440767 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9002.440767 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 67804 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 67819 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101460528500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.886481 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.867905 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.867905 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92498 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92498 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92498 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92498 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92498 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92498 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68839 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 68839 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68839 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 68839 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68839 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 68839 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 851625712 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 851625712 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 851625712 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 851625712 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 851625712 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 851625712 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161337 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 161337 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161337 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 161337 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161337 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 161337 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426678 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426678 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426678 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426678 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426678 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426678 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12371.267915 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12371.267915 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12371.267915 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12371.267915 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12371.267915 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 68638 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 13.809611 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 91506 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 68653 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.332877 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5104119753500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.809611 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.863101 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.863101 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91510 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 91510 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91510 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 91510 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91510 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 91510 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69712 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 69712 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69712 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 69712 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69712 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 69712 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854471475 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854471475 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854471475 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 854471475 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854471475 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 854471475 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161222 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 161222 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161222 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 161222 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161222 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 161222 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.432398 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.432398 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.432398 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.432398 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.432398 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.432398 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12257.164835 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12257.164835 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12257.164835 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12257.164835 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12257.164835 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12257.164835 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1166,146 +1173,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 23017 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 23017 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68839 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68839 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68839 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 68839 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68839 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 68839 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 713808442 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 713808442 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 713808442 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 713808442 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 713808442 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 713808442 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426678 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426678 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426678 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10369.244789 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20719 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20719 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69712 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69712 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69712 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 69712 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69712 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 69712 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 714931165 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 714931165 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 714931165 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 714931165 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 714931165 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 714931165 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.432398 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.432398 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.432398 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.432398 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.432398 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.432398 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10255.496399 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10255.496399 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10255.496399 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1656828 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1655321 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993756 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18976383 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1655833 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.460324 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10890330 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10890330 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8092849 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8092849 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18983179 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18983179 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18983179 # number of overall hits -system.cpu.dcache.overall_hits::total 18983179 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2236067 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2236067 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316060 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316060 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2552127 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2552127 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2552127 # number of overall misses -system.cpu.dcache.overall_misses::total 2552127 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33180539725 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33180539725 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12164482246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12164482246 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45345021971 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45345021971 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45345021971 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45345021971 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13126397 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13126397 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8408909 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8408909 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21535306 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21535306 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21535306 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21535306 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170349 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170349 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037586 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037586 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118509 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118509 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118509 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118509 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.794958 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.794958 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38487.889154 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38487.889154 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17767.541337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17767.541337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17767.541337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17767.541337 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 401774 # number of cycles access was blocked +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993756 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10875506 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10875506 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8098167 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8098167 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18973673 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18973673 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18973673 # number of overall hits +system.cpu.dcache.overall_hits::total 18973673 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2232931 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2232931 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315791 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315791 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2548722 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2548722 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2548722 # number of overall misses +system.cpu.dcache.overall_misses::total 2548722 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33105603008 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33105603008 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12178134710 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12178134710 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45283737718 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45283737718 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45283737718 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45283737718 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13108437 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13108437 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8413958 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8413958 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21522395 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21522395 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21522395 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21522395 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170343 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170343 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037532 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037532 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118422 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118422 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118422 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118422 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14826.075238 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14826.075238 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38563.906856 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38563.906856 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17767.233036 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17767.233036 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17767.233036 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17767.233036 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 397899 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42434 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42056 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.468209 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.461171 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558504 # number of writebacks -system.cpu.dcache.writebacks::total 1558504 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866614 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 866614 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25901 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25901 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 892515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 892515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 892515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 892515 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369453 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369453 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290159 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290159 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1659612 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1659612 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1659612 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1659612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17930492982 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17930492982 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11266233199 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11266233199 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29196726181 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29196726181 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29196726181 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29196726181 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349090500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349090500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2521949000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2521949000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99871039500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99871039500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104328 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104328 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077065 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077065 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077065 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077065 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13093.178796 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13093.178796 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38827.791656 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38827.791656 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17592.501248 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17592.501248 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17592.501248 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17592.501248 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1557485 # number of writebacks +system.cpu.dcache.writebacks::total 1557485 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864709 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 864709 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25884 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25884 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 890593 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 890593 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 890593 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 890593 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1368222 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1368222 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289907 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289907 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1658129 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1658129 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1658129 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1658129 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17890826726 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17890826726 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11280486479 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11280486479 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29171313205 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29171313205 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29171313205 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29171313205 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364618000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364618000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538596500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538596500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903214500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903214500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034455 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034455 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077042 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077042 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077042 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077042 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13075.967735 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13075.967735 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38910.707499 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38910.707499 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17592.909360 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17592.909360 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17592.909360 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17592.909360 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1313,141 +1320,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111287 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64824.187334 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3785036 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175649 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.548862 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111515 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64833.541766 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3779668 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175596 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.524796 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50594.922506 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.467907 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3127.998862 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11091.672124 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.772017 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000144 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169245 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989139 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63059 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6479 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 937263 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1332664 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2339465 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1583020 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1583020 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 302 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154882 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154882 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 63059 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 6479 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 937263 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1487546 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2494347 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 63059 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 6479 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 937263 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1487546 # number of overall hits -system.cpu.l2cache.overall_hits::total 2494347 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 62 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16026 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 36078 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52171 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1463 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1463 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133126 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133126 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16026 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 185297 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16026 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169204 # number of overall misses -system.cpu.l2cache.overall_misses::total 185297 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6809750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 417750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1389559236 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3040297215 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4437083951 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17341812 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17341812 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9382369904 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9382369904 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6809750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 417750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1389559236 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12422667119 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13819453855 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6809750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 417750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1389559236 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12422667119 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13819453855 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63121 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 6484 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 953289 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1368742 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2391636 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1583020 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1583020 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1765 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1765 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288008 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288008 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63121 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 6484 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 953289 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1656750 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2679644 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63121 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 6484 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 953289 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1656750 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2679644 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000771 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016811 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026359 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021814 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.828895 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.828895 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.462230 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.462230 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000771 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016811 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102130 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.069150 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000771 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016811 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102130 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.069150 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 109834.677419 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83550 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86706.554100 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84270.115167 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 85048.857622 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11853.596719 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11853.596719 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70477.366585 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70477.366585 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 109834.677419 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86706.554100 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73418.282777 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74580.019401 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 109834.677419 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86706.554100 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73418.282777 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74580.019401 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 50736.164769 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.333778 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.436924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3104.326837 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10979.279458 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.774172 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047368 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.167531 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989281 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63026 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6786 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 939635 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1331578 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2341025 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1579976 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1579976 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 330 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 330 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 154233 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154233 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 63026 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 6786 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 939635 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1485811 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2495258 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 63026 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 6786 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 939635 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1485811 # number of overall hits +system.cpu.l2cache.overall_hits::total 2495258 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 58 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16058 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 35805 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 51927 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1441 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1441 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133490 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133490 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 58 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16058 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169295 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185417 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 58 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16058 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169295 # number of overall misses +system.cpu.l2cache.overall_misses::total 185417 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6074750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 507000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1388421484 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3011977215 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4406980449 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17718298 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 17718298 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9403560917 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9403560917 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6074750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 507000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1388421484 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12415538132 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13810541366 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6074750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 507000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1388421484 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12415538132 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13810541366 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63084 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 6792 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 955693 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1367383 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2392952 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1579976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1579976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1771 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1771 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 287723 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 287723 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63084 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 6792 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 955693 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1655106 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2680675 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63084 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 6792 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 955693 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1655106 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2680675 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000919 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000883 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026185 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021700 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.813665 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.813665 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463953 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.463953 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000919 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000883 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016802 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102287 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.069168 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000919 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000883 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016802 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102287 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.069168 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 104737.068966 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86462.914684 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84121.692920 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 84868.766711 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12295.834837 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12295.834837 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70443.935254 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70443.935254 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 104737.068966 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86462.914684 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73336.708893 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74483.684700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 104737.068966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86462.914684 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73336.708893 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74483.684700 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1456,99 +1463,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks -system.cpu.l2cache.writebacks::total 101898 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 62 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16022 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36077 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 52166 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1463 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1463 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133126 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133126 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 62 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16022 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169203 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 185292 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 62 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16022 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169203 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 185292 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6018750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 353750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1186972764 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2585018535 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3778363799 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15641444 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15641444 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7710305096 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7710305096 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6018750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 353750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1186972764 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10295323631 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11488668895 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6018750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 353750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1186972764 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10295323631 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11488668895 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236799000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236799000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2357013000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2357013000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91593812000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91593812000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000771 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016807 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026358 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021812 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.828895 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.828895 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.462230 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.462230 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000771 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016807 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069148 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000771 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016807 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.069148 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74083.932343 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71652.813011 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72429.624641 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.349282 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.349282 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57917.349699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57917.349699 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74083.932343 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60845.987548 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62003.048675 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74083.932343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60845.987548 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62003.048675 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 102141 # number of writebacks +system.cpu.l2cache.writebacks::total 102141 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 58 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16053 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35803 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 51920 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1441 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1441 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133490 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133490 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 58 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16053 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169293 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185410 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 58 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16053 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169293 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185410 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5335250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 430000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1185393516 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2560977283 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3752136049 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15491421 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15491421 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7726929083 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7726929083 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5335250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1185393516 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10287906366 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11479065132 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5335250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 430000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1185393516 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10287906366 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11479065132 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251391500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251391500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372712000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372712000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624103500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624103500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000919 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000883 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016797 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026184 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021697 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.813665 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.813665 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000919 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000883 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102285 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069165 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000919 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000883 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102285 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.069165 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73842.491497 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71529.684188 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72267.643471 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10750.465649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10750.465649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.954476 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.954476 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73842.491497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60769.827258 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61911.790799 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73842.491497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60769.827258 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61911.790799 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index f7f063037..8b1d3ad58 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -4,8 +4,9 @@ BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
-end_pfn_map = 32768
-kernel direct mapping tables up to 8000000 @ 8000-a000
+ BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
+end_pfn_map = 1048576
+kernel direct mapping tables up to 100000000 @ 8000-d000
DMI 2.5 present.
Zone PFN ranges:
DMA 0 -> 4096
@@ -22,8 +23,8 @@ Setting APIC routing to flat Processors: 1
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
-Built 1 zonelists. Total pages: 30613
+Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
+Built 1 zonelists. Total pages: 30612
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
@@ -33,7 +34,7 @@ console handover: boot [earlyser0] -> real [ttyS0] Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
-Memory: 122188k/131072k available (3742k kernel code, 8460k reserved, 1874k data, 232k init)
+Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 9c98f7142..e88b54daa 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -17,7 +17,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -681,8 +681,8 @@ voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table -children=entries0 entries1 entries2 -entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 +children=entries0 entries1 entries2 entries3 +entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 [system.e820_table.entries0] type=X86E820Entry @@ -702,6 +702,12 @@ addr=1048576 range_type=1 size=133169152 +[system.e820_table.entries3] +type=X86E820Entry +addr=4294901760 +range_type=2 +size=65536 + [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 @@ -1401,7 +1407,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/andreas/m5/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1421,7 +1427,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/andreas/m5/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 4cf24e39a..99453da63 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -4,7 +4,7 @@ warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. hack: be nice to actually delete the event here -warn: instruction 'fxsave' unimplemented +warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unimplemented function 8 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index e3d68909a..4e965874c 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,155 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.139589 # Number of seconds simulated -sim_ticks 5139589353000 # Number of ticks simulated -final_tick 5139589353000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133841 # Number of seconds simulated +sim_ticks 5133841152500 # Number of ticks simulated +final_tick 5133841152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190335 # Simulator instruction rate (inst/s) -host_op_rate 378180 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4014985901 # Simulator tick rate (ticks/s) -host_mem_usage 934028 # Number of bytes of host memory used -host_seconds 1280.10 # Real time elapsed on the host -sim_insts 243647713 # Number of instructions simulated -sim_ops 484108731 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2450688 # Number of bytes read from this memory +host_inst_rate 177631 # Simulator instruction rate (inst/s) +host_op_rate 353062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3741933991 # Simulator tick rate (ticks/s) +host_mem_usage 941552 # Number of bytes of host memory used +host_seconds 1371.98 # Real time elapsed on the host +sim_insts 243704660 # Number of instructions simulated +sim_ops 484392635 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2439680 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 424832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5722240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1810944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 372032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2837824 # Number of bytes read from this memory -system.physmem.bytes_read::total 13771904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 424832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 372032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 947904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9105344 # Number of bytes written to this memory -system.physmem.bytes_written::total 9105344 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38292 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 417472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5435008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1637440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 389440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3273088 # Number of bytes read from this memory +system.physmem.bytes_read::total 13748288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 417472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 153664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 389440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 960576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9087296 # Number of bytes written to this memory +system.physmem.bytes_written::total 9087296 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38120 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6638 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 89410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 28296 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 30 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5813 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 44341 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215186 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142271 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142271 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476826 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6523 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 84922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2401 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 25585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 51142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 214817 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141989 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141989 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 475215 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1113365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 352352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 72386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 552150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2679573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29388 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 72386 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 184432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1771609 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1771609 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1771609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 81318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1058663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 318950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 75857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 637551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2677973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 81318 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29932 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 75857 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 187107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1770077 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1770077 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1770077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 475215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1113365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 352352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 72386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 552150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4451182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 96603 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 74912 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 96603 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 74912 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 6182592 # Total number of bytes read from memory -system.physmem.bytesWritten 4794368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6182592 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4794368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 12 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 732 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 5743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 5750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 5839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6214 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 5688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 5956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 5856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 5878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 5996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6119 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4526 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4556 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4674 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4457 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4557 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4556 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4962 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5050 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4641 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4582 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4382 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 81318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1058663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 318950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 75857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 637551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4448050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109407 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 86017 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 109407 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 86017 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 7002048 # Total number of bytes read from memory +system.physmem.bytesWritten 5505088 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7002048 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5505088 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 46 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 985 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6677 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6998 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 7052 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7052 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 7335 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7518 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6667 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6903 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6546 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6589 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6286 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5445 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5613 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5490 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5857 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5967 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5044 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4972 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5220 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5090 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4887 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5403 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4667 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 5136024228000 # Total gap between requests +system.physmem.totGap 5132841022000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 96603 # Categorize read packet sizes +system.physmem.readPktSize::6 109407 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 74912 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 77105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1026 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86017 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 82002 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 587 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -161,525 +157,526 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.902562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.864384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1038.972369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14693 44.19% 44.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5121 15.40% 59.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3144 9.46% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2114 6.36% 75.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1414 4.25% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1109 3.34% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 834 2.51% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 672 2.02% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 527 1.58% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 500 1.50% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 311 0.94% 91.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 308 0.93% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 231 0.69% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 204 0.61% 93.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 157 0.47% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 279 0.84% 95.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 147 0.44% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 117 0.35% 95.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 74 0.22% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 80 0.24% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 100 0.30% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 111 0.33% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 291 0.88% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 116 0.35% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 63 0.19% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 43 0.13% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 35 0.11% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 34 0.10% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 18 0.05% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 13 0.04% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 14 0.04% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 17 0.05% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 9 0.03% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 4 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 7 0.02% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 10 0.03% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 7 0.02% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 8 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 9 0.03% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 6 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 2 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 6 0.02% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 5 0.02% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 2 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 3 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 3 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 5 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 5 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 4 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 2 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 2 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 3 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 29 0.09% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 2 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 2 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 2 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 2 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 11 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 2 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 4 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 3 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 2 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 2 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 2 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 5 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 2 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 5 0.02% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 2 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 27 0.08% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 34126 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 366.337455 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.216704 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1274.009312 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 15243 44.67% 44.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5253 15.39% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3189 9.34% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2065 6.05% 75.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1417 4.15% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1112 3.26% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 885 2.59% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 703 2.06% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 508 1.49% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 509 1.49% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 307 0.90% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 283 0.83% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 211 0.62% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 233 0.68% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 184 0.54% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 239 0.70% 94.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 139 0.41% 95.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 117 0.34% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 116 0.34% 95.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 75 0.22% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 103 0.30% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 85 0.25% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 293 0.86% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 132 0.39% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 64 0.19% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 54 0.16% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 36 0.11% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 37 0.11% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 21 0.06% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 15 0.04% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 15 0.04% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 22 0.06% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 8 0.02% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 13 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 9 0.03% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 4 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 3 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 4 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 2 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 3 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 6 0.02% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 3 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 1 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 7 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 3 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 4 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 3 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 8 0.02% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 3 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 2 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 2 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 2 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 5 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 49 0.14% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 4 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 2 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 3 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 23 0.07% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 8 0.02% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 5 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 7 0.02% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 5 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 7 0.02% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 4 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 3 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 2 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 6 0.02% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 6 0.02% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 13 0.04% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 11 0.03% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 30 0.09% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 2 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 2 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 1 0.00% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33252 # Bytes accessed per row activation -system.physmem.totQLat 1788062000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3723402000 # Sum of mem lat for all requests -system.physmem.totBusLat 482955000 # Total cycles spent in databus access -system.physmem.totBankLat 1452385000 # Total cycles spent in bank access -system.physmem.avgQLat 18511.68 # Average queueing delay per request -system.physmem.avgBankLat 15036.44 # Average bank access latency per request +system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17411 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17987 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20483 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34126 # Bytes accessed per row activation +system.physmem.totQLat 2227577000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4316939500 # Sum of mem lat for all requests +system.physmem.totBusLat 546805000 # Total cycles spent in databus access +system.physmem.totBankLat 1542557500 # Total cycles spent in bank access +system.physmem.avgQLat 20369.03 # Average queueing delay per request +system.physmem.avgBankLat 14105.19 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38548.13 # Average memory access latency -system.physmem.avgRdBW 1.20 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.20 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.93 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 39474.21 # Average memory access latency +system.physmem.avgRdBW 1.36 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.07 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1.36 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.07 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.11 # Average write queue length over time -system.physmem.readRowHits 84146 # Number of row buffer hits during reads -system.physmem.writeRowHits 54105 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.22 # Row buffer hit rate for writes -system.physmem.avgGap 29945044.04 # Average gap between requests -system.membus.throughput 6414834 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 427545 # Transaction distribution -system.membus.trans_dist::ReadResp 427545 # Transaction distribution -system.membus.trans_dist::WriteReq 5661 # Transaction distribution -system.membus.trans_dist::WriteResp 5661 # Transaction distribution -system.membus.trans_dist::Writeback 74912 # Transaction distribution -system.membus.trans_dist::UpgradeReq 735 # Transaction distribution -system.membus.trans_dist::UpgradeResp 735 # Transaction distribution -system.membus.trans_dist::ReadExReq 72970 # Transaction distribution -system.membus.trans_dist::ReadExResp 72970 # Transaction distribution -system.membus.trans_dist::MessageReq 216 # Transaction distribution -system.membus.trans_dist::MessageResp 216 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1030222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 54502 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 54502 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1085156 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 864 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9889556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2243648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2243648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12134068 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32713165 # Total data (bytes) -system.membus.snoop_data_through_bus 256448 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 164366000 # Layer occupancy (ticks) +system.physmem.avgWrQLen 0.12 # Average write queue length over time +system.physmem.readRowHits 96443 # Number of row buffer hits during reads +system.physmem.writeRowHits 64788 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.32 # Row buffer hit rate for writes +system.physmem.avgGap 26265151.78 # Average gap between requests +system.membus.throughput 6435647 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 426045 # Transaction distribution +system.membus.trans_dist::ReadResp 426045 # Transaction distribution +system.membus.trans_dist::WriteReq 6051 # Transaction distribution +system.membus.trans_dist::WriteResp 6051 # Transaction distribution +system.membus.trans_dist::Writeback 86017 # Transaction distribution +system.membus.trans_dist::UpgradeReq 992 # Transaction distribution +system.membus.trans_dist::UpgradeResp 992 # Transaction distribution +system.membus.trans_dist::ReadExReq 86731 # Transaction distribution +system.membus.trans_dist::ReadExResp 86731 # Transaction distribution +system.membus.trans_dist::MessageReq 839 # Transaction distribution +system.membus.trans_dist::MessageResp 839 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1678 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1678 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 309632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497840 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 229352 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1036824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83140 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83140 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1121642 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3356 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3356 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158773 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995677 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 9079040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 10233490 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3428096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 3428096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13664942 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32675815 # Total data (bytes) +system.membus.snoop_data_through_bus 363776 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 162435000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314753000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315254500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 432000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1678000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 793885999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 909214250 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 216000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 839000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1632166487 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1669428217 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 175306750 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 266628000 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 104154 # number of replacements -system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use -system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks. +system.l2c.tags.replacements 103896 # number of replacements +system.l2c.tags.tagsinuse 64824.162456 # Cycle average of tags in use +system.l2c.tags.total_refs 3654371 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167960 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.757389 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51338.562640 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.124968 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1291.708374 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4472.671123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 224.398277 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1500.107620 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 12.436537 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1357.602773 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4626.550145 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.783364 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.069804 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.022344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 20178 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11162 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 357762 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 528228 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4903 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 153273 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 226490 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 46782 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 8793 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 321700 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 546165 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2227865 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.019710 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.068248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003424 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.022890 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000190 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.020715 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.070596 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989138 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 17952 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 9698 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 334064 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 501848 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 11245 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6309 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 156420 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 227136 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 54455 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 10230 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 347276 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 575532 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2252165 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1544497 # number of Writeback hits -system.l2c.Writeback_hits::total 1544497 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 143 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 76 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 255 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 71037 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43117 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 57018 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171172 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20178 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11164 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 357762 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 599265 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4903 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 153273 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 269607 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 46782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 8793 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 321700 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 603183 # number of demand (read+write) hits -system.l2c.demand_hits::total 2399039 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20178 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11164 # number of overall hits -system.l2c.overall_hits::cpu0.inst 357762 # number of overall hits -system.l2c.overall_hits::cpu0.data 599265 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4903 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits -system.l2c.overall_hits::cpu1.inst 153273 # number of overall hits -system.l2c.overall_hits::cpu1.data 269607 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 46782 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 8793 # number of overall hits -system.l2c.overall_hits::cpu2.inst 321700 # number of overall hits -system.l2c.overall_hits::cpu2.data 603183 # number of overall hits -system.l2c.overall_hits::total 2399039 # number of overall hits +system.l2c.Writeback_hits::writebacks 1543820 # number of Writeback hits +system.l2c.Writeback_hits::total 1543820 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 85 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 61 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 121 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 267 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 59704 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 38749 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 68883 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167336 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 17952 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 9700 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 334064 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 561552 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11245 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6309 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 156420 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 265885 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 54455 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 10230 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 347276 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 644415 # number of demand (read+write) hits +system.l2c.demand_hits::total 2419503 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 17952 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 9700 # number of overall hits +system.l2c.overall_hits::cpu0.inst 334064 # number of overall hits +system.l2c.overall_hits::cpu0.data 561552 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 11245 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6309 # number of overall hits +system.l2c.overall_hits::cpu1.inst 156420 # number of overall hits +system.l2c.overall_hits::cpu1.data 265885 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 54455 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 10230 # number of overall hits +system.l2c.overall_hits::cpu2.inst 347276 # number of overall hits +system.l2c.overall_hits::cpu2.data 644415 # number of overall hits +system.l2c.overall_hits::total 2419503 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6638 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 13571 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2360 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4761 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5815 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 14526 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47708 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 712 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 243 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 390 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1345 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76337 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 23772 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 30004 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130113 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 6523 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 13238 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2401 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4542 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 34 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 6087 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 15146 # number of ReadReq misses +system.l2c.ReadReq_misses::total 47976 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 449 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 296 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 618 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1363 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 72270 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 21215 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 36170 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 129655 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6638 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 89908 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2360 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 28533 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 31 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5815 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 44530 # number of demand (read+write) misses -system.l2c.demand_misses::total 177821 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6523 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 85508 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2401 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 25757 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 34 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 6087 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 51316 # number of demand (read+write) misses +system.l2c.demand_misses::total 177631 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6638 # number of overall misses -system.l2c.overall_misses::cpu0.data 89908 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2360 # number of overall misses -system.l2c.overall_misses::cpu1.data 28533 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 31 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5815 # number of overall misses -system.l2c.overall_misses::cpu2.data 44530 # number of overall misses -system.l2c.overall_misses::total 177821 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 185186500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 369106743 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3097499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 524253495 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1205998231 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2287731218 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2444401 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 4607806 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 7052207 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1673798209 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2232599179 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 3906397388 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 185186500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2042904952 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 3097499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 524253495 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3438597410 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6194128606 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 185186500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2042904952 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 3097499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 524253495 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3438597410 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6194128606 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 20178 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 11167 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 364400 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 541799 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4903 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 155633 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 231251 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 46813 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 8794 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 327515 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 560691 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2275573 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 6523 # number of overall misses +system.l2c.overall_misses::cpu0.data 85508 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2401 # number of overall misses +system.l2c.overall_misses::cpu1.data 25757 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 34 # number of overall misses +system.l2c.overall_misses::cpu2.inst 6087 # number of overall misses +system.l2c.overall_misses::cpu2.data 51316 # number of overall misses +system.l2c.overall_misses::total 177631 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 190776000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 357065989 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3670750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 535117250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1265414987 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2352044976 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 3779850 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 6916712 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 10696562 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1454896180 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2695279940 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 4150176120 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 190776000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1811962169 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 3670750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 535117250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3960694927 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6502221096 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 190776000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1811962169 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 3670750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 535117250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3960694927 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6502221096 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 17952 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 9703 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 340587 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 515086 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 11245 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6309 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 158821 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 231678 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 54489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 10230 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 353363 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 590678 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2300141 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1544497 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1544497 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 855 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 279 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 466 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1600 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 147374 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 66889 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 87022 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 301285 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 20178 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 11169 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 364400 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 689173 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4903 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 155633 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 298140 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 46813 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 8794 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 327515 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 647713 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2576860 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 20178 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 11169 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 364400 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 689173 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4903 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 155633 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 298140 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 46813 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 8794 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 327515 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 647713 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2576860 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000448 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018216 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.025048 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015164 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020588 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000662 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000114 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.017755 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.025907 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020965 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.832749 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870968 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.836910 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.840625 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.517981 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.355395 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.344786 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.431860 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000448 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018216 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.130458 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015164 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.095703 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000662 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000114 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.017755 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.068750 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.069007 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000448 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018216 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.130458 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015164 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.095703 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000662 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000114 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.017755 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.068750 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.069007 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78468.855932 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77527.146188 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 99919.322581 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 90155.373173 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 83023.422208 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 47952.779785 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10059.263374 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11814.887179 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5243.276580 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70410.491713 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74410.051293 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 30023.113663 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 78468.855932 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71597.972593 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 99919.322581 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 90155.373173 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 77219.793622 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 34833.504513 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78468.855932 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71597.972593 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 99919.322581 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 90155.373173 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 77219.793622 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 34833.504513 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1543820 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1543820 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 534 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 357 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 739 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1630 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 131974 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 59964 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 105053 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296991 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 17952 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 9705 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 340587 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 647060 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 11245 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6309 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 158821 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 291642 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 54489 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 10230 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 353363 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 695731 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2597134 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 17952 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 9705 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 340587 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 647060 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 11245 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6309 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 158821 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 291642 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 54489 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 10230 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 353363 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 695731 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2597134 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000515 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.019152 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.025701 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.015118 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.019605 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000624 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.017226 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.025642 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020858 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.840824 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829132 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.836265 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.836196 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.547608 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.353796 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.344302 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000515 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.132148 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.015118 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.088317 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000624 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.017226 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.073758 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.068395 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000515 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.132148 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.015118 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.088317 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000624 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.017226 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.073758 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.068395 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79456.892961 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78614.264421 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 107963.235294 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 87911.491704 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 83547.800541 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 49025.449725 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12769.763514 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11192.090615 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 7847.807777 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68578.655668 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74517.001382 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 32009.379661 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 79456.892961 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 70348.339053 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 107963.235294 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 87911.491704 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 77182.456290 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 36605.215846 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 79456.892961 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 70348.339053 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 107963.235294 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 87911.491704 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 77182.456290 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 36605.215846 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -688,134 +685,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95604 # number of writebacks -system.l2c.writebacks::total 95604 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker 1 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 95322 # number of writebacks +system.l2c.writebacks::total 95322 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.dtb.walker 1 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.dtb.walker 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.inst 2360 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4761 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 30 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 5813 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 14526 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 27491 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 243 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 390 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 633 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 23772 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 30004 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 53776 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2360 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 28533 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 30 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5813 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 44530 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 81267 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2360 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 28533 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 30 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5813 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 44530 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 81267 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 155365000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 308892757 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2656751 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 450701255 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1022394749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1940086762 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2530241 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3952388 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 6482629 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1375043791 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1855159821 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 3230203612 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 155365000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1683936548 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2656751 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 450701255 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2877554570 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5170290374 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 155365000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1683936548 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2656751 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 450701255 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2877554570 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5170290374 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28552490000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30418768500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58971258500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 380243500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 689742500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1069986000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28932733500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31108511000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60041244500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015164 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020588 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000641 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000114 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017749 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.025907 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.012081 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870968 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.836910 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.395625 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.355395 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344786 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.178489 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015164 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.095703 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000114 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017749 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.068750 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.031537 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015164 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.095703 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000114 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017749 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.068750 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.031537 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65832.627119 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64879.806133 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 88558.366667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77533.331326 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70383.777296 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 70571.705722 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10412.514403 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10134.328205 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10241.120063 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57842.999790 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61830.416644 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60067.755356 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65832.627119 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59017.157257 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 88558.366667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77533.331326 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64620.583202 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63621.031587 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65832.627119 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59017.157257 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 88558.366667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77533.331326 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64620.583202 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63621.031587 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.inst 2401 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4542 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 34 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 6085 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 15146 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 28208 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 296 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 618 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 914 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 21215 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 36170 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 57385 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2401 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 25757 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 34 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 6085 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 51316 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 85593 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2401 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 25757 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 34 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 6085 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 51316 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 85593 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 160439500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 299438011 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3240750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 458127750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1073760993 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1995007004 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3160292 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 6338615 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 9498907 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1188287320 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2240519524 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3428806844 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 160439500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1487725331 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3240750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 458127750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 3314280517 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5423813848 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 160439500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1487725331 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3240750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 458127750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3314280517 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5423813848 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28206379000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30385404000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58591783000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 459404000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 643945000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1103349000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28665783000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31029349000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59695132000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015118 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019605 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000624 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017220 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.025642 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.012264 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829132 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.836265 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.560736 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.353796 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344302 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.193221 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015118 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.088317 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000624 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017220 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.073758 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.032957 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015118 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.088317 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000624 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.073758 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.032957 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66821.949188 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65926.466535 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 95316.176471 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 75288.044371 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70894.030965 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 70724.865428 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10676.662162 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10256.658576 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10392.677243 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56011.657789 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61944.139453 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 59750.925224 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66821.949188 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57760.039251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 95316.176471 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75288.044371 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64585.714339 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63367.493230 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66821.949188 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57760.039251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 95316.176471 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75288.044371 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64585.714339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63367.493230 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -826,39 +808,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47579 # number of replacements -system.iocache.tags.tagsinuse 0.100447 # Cycle average of tags in use +system.iocache.tags.replacements 47572 # number of replacements +system.iocache.tags.tagsinuse 0.081746 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4999807573509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.100447 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006278 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006278 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses -system.iocache.ReadReq_misses::total 914 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5000166717509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081746 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005109 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005109 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses +system.iocache.ReadReq_misses::total 907 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47634 # number of demand (read+write) misses -system.iocache.demand_misses::total 47634 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47634 # number of overall misses -system.iocache.overall_misses::total 47634 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 16928907 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 16928907 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 4287176010 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4287176010 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 4304104917 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4304104917 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 4304104917 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4304104917 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses +system.iocache.demand_misses::total 47627 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses +system.iocache.overall_misses::total 47627 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 17254172 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 17254172 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6526811791 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6526811791 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6544065963 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6544065963 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6544065963 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6544065963 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47634 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47634 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47634 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47634 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -867,56 +849,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 18521.780088 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 18521.780088 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 91763.185146 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 91763.185146 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 90357.830898 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 90357.830898 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 90357.830898 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 90357.830898 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 61504 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 19023.342889 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 19023.342889 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 139700.594842 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 139700.594842 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 137402.439016 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137402.439016 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 137402.439016 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137402.439016 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 93815 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5648 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9015 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.889518 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.406545 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 149 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 149 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 19296 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 19296 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 19445 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 19445 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 19445 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 19445 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 9180907 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 9180907 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3283180510 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3283180510 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3292361417 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3292361417 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3292361417 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3292361417 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.163020 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.163020 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.413014 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.413014 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.408217 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.408217 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.408217 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.408217 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61616.825503 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 61616.825503 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 170148.243677 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 170148.243677 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169316.606686 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 169316.606686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169316.606686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 169316.606686 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 152 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 29424 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 29424 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 29576 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 29576 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 29576 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 29576 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 9350172 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 9350172 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4995875791 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4995875791 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5005225963 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5005225963 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5005225963 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5005225963 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.167585 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.167585 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.629795 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.629795 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.620992 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.620992 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.620992 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.620992 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61514.289474 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 61514.289474 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169789.144610 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 169789.144610 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169232.687415 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 169232.687415 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169232.687415 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 169232.687415 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -930,456 +912,456 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52172743 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1753367 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1753366 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 5661 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 5661 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 894976 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 745 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 745 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 173207 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 153920 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 966317 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3599461 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 26176 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 114965 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4706919 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 30921472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118979348 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 89784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 413728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 150404332 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 267998065 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 148408 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4987080585 # Layer occupancy (ticks) +system.toL2Bus.throughput 52334793 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1839633 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1839631 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 6051 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 6051 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 932295 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1096 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1096 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 194441 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 165022 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1024400 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3716860 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 38970 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 150527 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4930757 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32779776 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 124023122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 132312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 525872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 157461082 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268452219 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 226296 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5204318000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 706500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 697500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2176927347 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2307741753 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4676438168 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4862432158 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 14970214 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 22450957 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 63358037 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 84915011 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1260736 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 151186 # Transaction distribution -system.iobus.trans_dist::ReadResp 151186 # Transaction distribution -system.iobus.trans_dist::WriteReq 24735 # Transaction distribution -system.iobus.trans_dist::WriteResp 24735 # Transaction distribution -system.iobus.trans_dist::MessageReq 216 # Transaction distribution -system.iobus.trans_dist::MessageResp 216 # Transaction distribution +system.iobus.throughput 1275830 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 149760 # Transaction distribution +system.iobus.trans_dist::ReadResp 149760 # Transaction distribution +system.iobus.trans_dist::WriteReq 34632 # Transaction distribution +system.iobus.trans_dist::WriteResp 34632 # Transaction distribution +system.iobus.trans_dist::MessageReq 839 # Transaction distribution +system.iobus.trans_dist::MessageResp 839 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 3660 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287488 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 432 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14654 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 312952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 38890 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 432 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 352274 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 309632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 59152 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 59152 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1678 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1678 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 370462 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2064 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 864 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7327 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 159887 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1236136 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1396887 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6479664 # Total data (bytes) -system.iobus.reqLayer0.occupancy 492564 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 158773 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1884352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1884352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3356 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3356 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2046481 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6549906 # Total data (bytes) +system.iobus.reqLayer0.occupancy 1995988 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3525000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 3028000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 24000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 145313000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143745000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 31000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 340000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11833000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10951000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 175039167 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 266780963 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 307513000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 304424000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 20042250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 30398000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 216000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 839000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1821353005 # number of cpu cycles simulated +system.cpu0.numCycles 1216058379 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 73292155 # Number of instructions committed -system.cpu0.committedOps 148692338 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 136997121 # Number of integer alu accesses +system.cpu0.committedInsts 70973751 # Number of instructions committed +system.cpu0.committedOps 144754752 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 132876215 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1072392 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14299557 # number of instructions that are conditional controls -system.cpu0.num_int_insts 136997121 # number of integer instructions +system.cpu0.num_func_calls 954469 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14058767 # number of instructions that are conditional controls +system.cpu0.num_int_insts 132876215 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 337067923 # number of times the integer registers were read -system.cpu0.num_int_register_writes 173978676 # number of times the integer registers were written +system.cpu0.num_int_register_reads 326195357 # number of times the integer registers were read +system.cpu0.num_int_register_writes 169360741 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 14736464 # number of memory refs -system.cpu0.num_load_insts 10677140 # Number of load instructions -system.cpu0.num_store_insts 4059324 # Number of store instructions -system.cpu0.num_idle_cycles 1727957342.597034 # Number of idle cycles -system.cpu0.num_busy_cycles 93395662.402966 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051278 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948722 # Percentage of idle cycles +system.cpu0.num_mem_refs 13502778 # number of memory refs +system.cpu0.num_load_insts 9976335 # Number of load instructions +system.cpu0.num_store_insts 3526443 # Number of store instructions +system.cpu0.num_idle_cycles 1154763739.944412 # Number of idle cycles +system.cpu0.num_busy_cycles 61294639.055587 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050404 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949596 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 847048 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.566465 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 97.238420 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 93.012763 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.626106 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.189919 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.181666 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 89325030 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38126450 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2543925 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129995405 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 89325030 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38126450 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2543925 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129995405 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 89325030 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38126450 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2543925 # number of overall hits -system.cpu0.icache.overall_hits::total 129995405 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 364401 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 155633 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 345614 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 865648 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 364401 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 155633 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 345614 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 865648 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 364401 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 155633 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 345614 # number of overall misses -system.cpu0.icache.overall_misses::total 865648 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2193404000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5014378720 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7207782720 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2193404000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5014378720 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7207782720 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2193404000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5014378720 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7207782720 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 89689431 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 38282083 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2889539 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130861053 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 89689431 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 38282083 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2889539 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130861053 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 89689431 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 38282083 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2889539 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130861053 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004063 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004065 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.119609 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006615 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004063 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004065 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.119609 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006615 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004063 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004065 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.119609 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006615 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14093.437767 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14508.609952 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8326.459161 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14093.437767 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14508.609952 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8326.459161 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14093.437767 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14508.609952 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8326.459161 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6927 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 852277 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.807193 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128191488 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 852789 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 150.320288 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147441059000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 310.064023 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 127.526237 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 73.216933 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.605594 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.249075 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.143002 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997670 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 86216719 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 39136583 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2838186 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 128191488 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 86216719 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 39136583 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2838186 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 128191488 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 86216719 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 39136583 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2838186 # number of overall hits +system.cpu0.icache.overall_hits::total 128191488 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 340588 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 158821 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 373273 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 872682 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 340588 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 158821 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 373273 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 872682 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 340588 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 158821 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 373273 # number of overall misses +system.cpu0.icache.overall_misses::total 872682 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2239882500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5368625144 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7608507644 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2239882500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5368625144 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7608507644 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2239882500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5368625144 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7608507644 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 86557307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39295404 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3211459 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 129064170 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 86557307 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39295404 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3211459 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 129064170 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 86557307 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39295404 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3211459 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 129064170 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003935 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004042 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116232 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006762 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003935 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004042 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116232 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006762 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003935 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004042 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116232 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006762 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14103.188495 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14382.570248 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8718.533949 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14103.188495 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14382.570248 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8718.533949 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14103.188495 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14382.570248 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8718.533949 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3629 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 238 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 204 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.105042 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.789216 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 18078 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 18078 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 18078 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 18078 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 18078 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 18078 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 155633 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 327536 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 483169 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 155633 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 327536 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 483169 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 155633 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 327536 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 483169 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1880996000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4143986636 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6024982636 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1880996000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4143986636 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6024982636 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1880996000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4143986636 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6024982636 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004065 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.113352 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003692 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004065 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.113352 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.003692 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004065 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.113352 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.003692 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12086.099992 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12469.721021 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12086.099992 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12469.721021 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12086.099992 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12469.721021 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 19878 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 19878 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 19878 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 19878 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 19878 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 19878 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 158821 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 353395 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 512216 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 158821 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 353395 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 512216 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 158821 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 353395 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 512216 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1921073500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4443772241 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6364845741 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1921073500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4443772241 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6364845741 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1921073500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4443772241 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6364845741 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004042 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110042 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003969 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004042 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110042 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.003969 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004042 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110042 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.003969 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12095.840600 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12574.519280 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12426.097078 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12095.840600 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12574.519280 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12426.097078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12095.840600 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12574.519280 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12426.097078 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1634474 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999389 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19647501 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1634986 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.016923 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1633907 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999457 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19585249 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1634419 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.983004 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 379.364018 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 126.391213 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.244158 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.740945 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.246858 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012196 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 202.365565 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 302.948237 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.685655 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.395245 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.591696 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013058 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5614384 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2225977 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3715968 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11556329 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3907488 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1533784 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2648186 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8089458 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9521872 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3759761 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6364154 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19645787 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9521872 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3759761 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6364154 # number of overall hits -system.cpu0.dcache.overall_hits::total 19645787 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 541799 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 231251 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 917589 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1690639 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 148229 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 67168 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 99931 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 315328 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 690028 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 298419 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1017520 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2005967 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 690028 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 298419 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1017520 # number of overall misses -system.cpu0.dcache.overall_misses::total 2005967 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3337683757 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15521474368 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 18859158125 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2326474532 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3256971146 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5583445678 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5664158289 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 18778445514 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24442603803 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5664158289 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 18778445514 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24442603803 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6156183 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2457228 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4633557 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13246968 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4055717 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1600952 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2748117 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8404786 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10211900 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4058180 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7381674 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21651754 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10211900 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4058180 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7381674 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21651754 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.088009 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.094111 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.198031 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127625 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036548 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.041955 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.036363 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037518 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.067571 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.073535 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137844 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092647 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067571 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.073535 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137844 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092647 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14433.164644 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16915.497426 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11155.047367 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34636.650369 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32592.200078 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17706.786831 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18980.555156 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18455.111953 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12184.948109 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18980.555156 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18455.111953 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12184.948109 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 172601 # number of cycles access was blocked +system.cpu0.dcache.ReadReq_hits::cpu0.data 4859041 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2539484 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4098776 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11497301 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3389758 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1674537 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3021878 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8086173 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8248799 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4214021 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7120654 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19583474 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8248799 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4214021 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7120654 # number of overall hits +system.cpu0.dcache.overall_hits::total 19583474 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 515086 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 231678 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 978230 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1724994 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 132508 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 60321 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 122659 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 315488 # number of WriteReq misses +system.cpu0.dcache.demand_misses::cpu0.data 647594 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 291999 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1100889 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2040482 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 647594 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 291999 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1100889 # number of overall misses +system.cpu0.dcache.overall_misses::total 2040482 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3333147011 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 16401267335 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 19734414346 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2044900112 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3952716068 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5997616180 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 5378047123 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 20353983403 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 25732030526 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 5378047123 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 20353983403 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 25732030526 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5374127 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2771162 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 5077006 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13222295 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3522266 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1734858 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3144537 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8401661 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8896393 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4506020 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 8221543 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21623956 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8896393 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4506020 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8221543 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21623956 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.095846 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083603 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.192679 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.130461 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037620 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034770 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.039007 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037551 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.072793 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.064802 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.133903 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.094362 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072793 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064802 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133903 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.094362 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14386.981116 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16766.269011 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11440.279993 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 33900.301918 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32225.242893 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19010.600023 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18418.032675 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18488.679061 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12610.760853 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18418.032675 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18488.679061 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12610.760853 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 185998 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11703 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11819 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.748441 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.737203 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1544497 # number of writebacks -system.cpu0.dcache.writebacks::total 1544497 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 356856 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 356856 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 12485 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 12485 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 369341 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 369341 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 369341 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 369341 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231251 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 560733 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 791984 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 67168 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 87446 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 154614 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 298419 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 648179 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 946598 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 298419 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 648179 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 946598 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2872959243 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8335143522 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11208102765 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2180545468 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2931248595 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5111794063 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 5053504711 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11266392117 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16319896828 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5053504711 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11266392117 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16319896828 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31052633000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33182784500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64235417500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 405522500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 732474500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1137997000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31458155500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33915259000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65373414500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.094111 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121016 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.059786 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.041955 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031820 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018396 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.073535 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087809 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.043719 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.073535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087809 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.043719 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12423.553814 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14864.727994 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14151.930803 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32464.052346 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33520.670986 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33061.650711 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16934.259250 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17381.606187 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17240.578184 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16934.259250 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17381.606187 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17240.578184 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1543820 # number of writebacks +system.cpu0.dcache.writebacks::total 1543820 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 387497 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 387497 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 16923 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 16923 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 404420 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 404420 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 404420 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 404420 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231678 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 590733 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 822411 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60321 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 105736 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 166057 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 291999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 696469 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 988468 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 291999 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 696469 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 988468 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2867647989 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8746594786 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11614242775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1913927888 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3540253677 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5454181565 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4781575877 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 12286848463 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17068424340 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4781575877 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12286848463 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17068424340 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30680226500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33146860500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63827087000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 492961500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 683134500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1176096000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31173188000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33829995000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65003183000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083603 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.116355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.062199 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034770 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.033625 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019765 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.064802 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.084713 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.045712 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.064802 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.084713 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045712 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12377.731114 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14806.341928 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14122.188024 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31729.047728 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33482.008748 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32845.237268 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16375.315933 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17641.630084 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17267.553770 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16375.315933 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17641.630084 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17267.553770 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1390,303 +1372,303 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606005785 # number of cpu cycles simulated +system.cpu1.numCycles 2604006231 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34706075 # Number of instructions committed -system.cpu1.committedOps 67513326 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62627092 # Number of integer alu accesses +system.cpu1.committedInsts 35468286 # Number of instructions committed +system.cpu1.committedOps 68966826 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64112699 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 413647 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6441517 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62627092 # number of integer instructions +system.cpu1.num_func_calls 467397 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6516733 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64112699 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 150899030 # number of times the integer registers were read -system.cpu1.num_int_register_writes 80614256 # number of times the integer registers were written +system.cpu1.num_int_register_reads 154768017 # number of times the integer registers were read +system.cpu1.num_int_register_writes 82365610 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 4252332 # number of memory refs -system.cpu1.num_load_insts 2649427 # Number of load instructions -system.cpu1.num_store_insts 1602905 # Number of store instructions -system.cpu1.num_idle_cycles 2479239642.942777 # Number of idle cycles -system.cpu1.num_busy_cycles 126766142.057223 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048644 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951356 # Percentage of idle cycles +system.cpu1.num_mem_refs 4696856 # number of memory refs +system.cpu1.num_load_insts 2960322 # Number of load instructions +system.cpu1.num_store_insts 1736534 # Number of store instructions +system.cpu1.num_idle_cycles 2474842610.831012 # Number of idle cycles +system.cpu1.num_busy_cycles 129163620.168988 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049602 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950398 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28549199 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28549199 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 285864 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26202333 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25707724 # Number of BTB hits +system.cpu2.branchPred.lookups 28951326 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28951326 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 314609 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26444223 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25831001 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.112347 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 509000 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 57796 # Number of incorrect RAS predictions. -system.cpu2.numCycles 153739924 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.681074 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 549086 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 62360 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157333790 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8861182 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 140768018 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28549199 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26216724 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54013734 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1344784 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 58192 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24037963 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 3706 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6519 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 19114 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 569 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2889543 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 128346 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1609 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 88045773 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.152898 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.410636 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9628033 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142779184 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28951326 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26380087 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54597571 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1466251 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 74094 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 26092625 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 3700 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8528 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 28165 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 264 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3211459 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 142418 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1960 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 91566528 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.070894 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.405285 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 34147694 38.78% 38.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 547423 0.62% 39.41% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23764633 26.99% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 284582 0.32% 66.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 557969 0.63% 67.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 795617 0.90% 68.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 319692 0.36% 68.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 484471 0.55% 69.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27143692 30.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 37107042 40.52% 40.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 606936 0.66% 41.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23738841 25.93% 67.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 323417 0.35% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 617037 0.67% 68.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 822992 0.90% 69.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 354044 0.39% 69.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 540920 0.59% 70.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27455299 29.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 88045773 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185698 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.915624 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10285454 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 22943626 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 41627806 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1270133 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1048147 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 276853450 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 7 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1048147 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11254615 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13961054 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 3963789 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 41762702 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5184927 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 275944284 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6769 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2459328 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2061675 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 2717 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 329857779 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 599690764 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 599690564 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 200 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320509391 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9348388 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 136043 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 137064 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11288733 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 5902057 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3230740 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 354441 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 291130 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 274390669 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 398438 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 272978735 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 57079 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6609909 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10125547 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 50893 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 88045773 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.100418 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.393656 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 91566528 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184012 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.907492 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 11182494 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 24930048 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 34120224 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1336422 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1136839 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 280365996 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 12 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1136839 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12213242 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 15294999 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4292193 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 34251970 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5516857 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 279357990 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 7057 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2496977 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2317195 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 3859 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 333649845 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 608867337 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 608867129 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 208 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 323590484 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10059359 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 155930 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 156830 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11908821 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6436780 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3659466 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 346383 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 291566 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 277678174 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 418845 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 276116383 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 64009 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7123201 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10899779 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 56873 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 91566528 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.015473 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.405372 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 25312226 28.75% 28.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5904467 6.71% 35.46% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3803238 4.32% 39.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2580509 2.93% 42.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25019730 28.42% 71.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1259471 1.43% 72.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23861754 27.10% 99.65% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 255558 0.29% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 48820 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 27610803 30.15% 30.15% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6353978 6.94% 37.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 4055937 4.43% 41.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2815603 3.07% 44.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25104677 27.42% 72.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1385023 1.51% 73.53% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23879782 26.08% 99.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 304593 0.33% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 56132 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 88045773 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 91566528 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 115953 32.52% 32.52% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 120 0.03% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 32.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 188030 52.73% 85.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 52485 14.72% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 137927 34.75% 34.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 241 0.06% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 196105 49.41% 84.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 62645 15.78% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 70354 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 263570476 96.55% 96.58% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 51118 0.02% 96.60% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 46597 0.02% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6213747 2.28% 98.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3026443 1.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 83641 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 265753381 96.25% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56758 0.02% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49344 0.02% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6728768 2.44% 98.75% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3444491 1.25% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 272978735 # Type of FU issued -system.cpu2.iq.rate 1.775588 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 356588 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001306 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 634455588 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 281402142 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 271688146 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 29 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 273264957 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 12 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 613124 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 276116383 # Type of FU issued +system.cpu2.iq.rate 1.754972 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 396918 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001438 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 644304824 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 285224158 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 274754060 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 88 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 276429621 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 39 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 673179 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 928259 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6814 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3642 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 478181 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1005768 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 7012 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4597 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 510812 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656152 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10356 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656130 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10580 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1048147 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9348181 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 808638 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 274789107 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 65396 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 5902057 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3230758 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 220588 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 626855 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4558 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3642 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 161804 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 161245 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 323049 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 272529284 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6113028 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 449451 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1136839 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10403399 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 827340 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 278097019 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 73172 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6436780 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3659466 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 241606 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 635543 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 5914 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4597 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 175933 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 181620 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 357553 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 275617670 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6616724 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 498712 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9080043 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27720555 # Number of branches executed -system.cpu2.iew.exec_stores 2967015 # Number of stores executed -system.cpu2.iew.exec_rate 1.772664 # Inst execution rate -system.cpu2.iew.wb_sent 272391201 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 271688152 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212092617 # num instructions producing a value -system.cpu2.iew.wb_consumers 346983399 # num instructions consuming a value +system.cpu2.iew.exec_refs 9995202 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28042459 # Number of branches executed +system.cpu2.iew.exec_stores 3378478 # Number of stores executed +system.cpu2.iew.exec_rate 1.751802 # Inst execution rate +system.cpu2.iew.wb_sent 275465212 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 274754080 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 213963670 # num instructions producing a value +system.cpu2.iew.wb_consumers 349997640 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.767193 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611247 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.746313 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611329 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 6884729 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 347545 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 288057 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 86997626 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.079430 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.871941 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7423416 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 361972 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 317845 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 90429689 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 2.993166 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.871852 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 29972174 34.45% 34.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4215922 4.85% 39.30% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1166731 1.34% 40.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24592469 28.27% 68.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 801811 0.92% 69.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 544306 0.63% 70.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 310409 0.36% 70.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23365384 26.86% 97.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2028420 2.33% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 32465154 35.90% 35.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4609597 5.10% 41.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1298624 1.44% 42.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24718633 27.33% 69.77% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 888931 0.98% 70.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 601938 0.67% 71.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 359938 0.40% 71.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23311721 25.78% 97.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2175153 2.41% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 86997626 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135649483 # Number of instructions committed -system.cpu2.commit.committedOps 267903067 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 90429689 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137262623 # Number of instructions committed +system.cpu2.commit.committedOps 270671057 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7726375 # Number of memory references committed -system.cpu2.commit.loads 4973798 # Number of loads committed -system.cpu2.commit.membars 163952 # Number of memory barriers committed -system.cpu2.commit.branches 27408076 # Number of branches committed +system.cpu2.commit.refs 8579665 # Number of memory references committed +system.cpu2.commit.loads 5431011 # Number of loads committed +system.cpu2.commit.membars 163136 # Number of memory barriers committed +system.cpu2.commit.branches 27702153 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244468826 # Number of committed integer instructions. -system.cpu2.commit.function_calls 411685 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2028420 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 247298072 # Number of committed integer instructions. +system.cpu2.commit.function_calls 442677 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2175153 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 359731311 # The number of ROB reads -system.cpu2.rob.rob_writes 550627170 # The number of ROB writes -system.cpu2.timesIdled 462650 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65694151 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4912523731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135649483 # Number of Instructions Simulated -system.cpu2.committedOps 267903067 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 135649483 # Number of Instructions Simulated -system.cpu2.cpi 1.133362 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.133362 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882331 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882331 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 500765277 # number of integer regfile reads -system.cpu2.int_regfile_writes 324464285 # number of integer regfile writes -system.cpu2.fp_regfile_reads 62550 # number of floating regfile reads -system.cpu2.fp_regfile_writes 62544 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88091146 # number of misc regfile reads -system.cpu2.misc_regfile_writes 122333 # number of misc regfile writes +system.cpu2.rob.rob_reads 366318021 # The number of ROB reads +system.cpu2.rob.rob_writes 557330113 # The number of ROB writes +system.cpu2.timesIdled 474514 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65767262 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4902343932 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137262623 # Number of Instructions Simulated +system.cpu2.committedOps 270671057 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 137262623 # Number of Instructions Simulated +system.cpu2.cpi 1.146225 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.146225 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.872429 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.872429 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 507419768 # number of integer regfile reads +system.cpu2.int_regfile_writes 327840306 # number of integer regfile writes +system.cpu2.fp_regfile_reads 62468 # number of floating regfile reads +system.cpu2.fp_regfile_writes 62496 # number of floating regfile writes +system.cpu2.misc_regfile_reads 89605766 # number of misc regfile reads +system.cpu2.misc_regfile_writes 140916 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal index 3b61c4c39..ff5b8aa75 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal @@ -4,8 +4,9 @@ BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
-end_pfn_map = 32768
-kernel direct mapping tables up to 8000000 @ 8000-a000
+ BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
+end_pfn_map = 1048576
+kernel direct mapping tables up to 100000000 @ 8000-d000
DMI 2.5 present.
Zone PFN ranges:
DMA 0 -> 4096
@@ -22,8 +23,8 @@ Setting APIC routing to flat Processors: 1
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
-Built 1 zonelists. Total pages: 30613
+Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
+Built 1 zonelists. Total pages: 30612
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
@@ -33,7 +34,7 @@ console handover: boot [earlyser0] -> real [ttyS0] Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
-Memory: 122188k/131072k available (3742k kernel code, 8460k reserved, 1874k data, 232k init)
+Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
@@ -43,7 +44,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812464
+result 7812463
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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