diff options
Diffstat (limited to 'tests/long/fs')
77 files changed, 30549 insertions, 30550 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini index a7c751a3c..db58f5ad6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini @@ -141,7 +141,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -564,7 +564,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -613,7 +613,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -747,7 +747,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index b894ed506..96524a9ce 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.886196 # Number of seconds simulated -sim_ticks 1886195993000 # Number of ticks simulated -final_tick 1886195993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.887168 # Number of seconds simulated +sim_ticks 1887168480000 # Number of ticks simulated +final_tick 1887168480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 256659 # Simulator instruction rate (inst/s) -host_op_rate 256659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8626071053 # Simulator tick rate (ticks/s) -host_mem_usage 374008 # Number of bytes of host memory used -host_seconds 218.66 # Real time elapsed on the host -sim_insts 56121694 # Number of instructions simulated -sim_ops 56121694 # Number of ops (including micro ops) simulated +host_inst_rate 181674 # Simulator instruction rate (inst/s) +host_op_rate 181674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6108559174 # Simulator tick rate (ticks/s) +host_mem_usage 367844 # Number of bytes of host memory used +host_seconds 308.94 # Real time elapsed on the host +sim_insts 56125948 # Number of instructions simulated +sim_ops 56125948 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1049728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24850240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1049920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24850048 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 25900928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1049728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1049728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7553600 # Number of bytes written to this memory -system.physmem.bytes_written::total 7553600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388285 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 1049920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1049920 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7553472 # Number of bytes written to this memory +system.physmem.bytes_written::total 7553472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388282 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 404702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118025 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118025 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 556532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13174792 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::writebacks 118023 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118023 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 556347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13167901 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13731833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 556532 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 556532 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4004674 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4004674 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4004674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 556532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13174792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13724757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 556347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 556347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4002542 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4002542 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4002542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 556347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13167901 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17736507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17727299 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 404702 # Number of read requests accepted -system.physmem.writeReqs 118025 # Number of write requests accepted +system.physmem.writeReqs 118023 # Number of write requests accepted system.physmem.readBursts 404702 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118025 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25894272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 7551808 # Total number of bytes written to DRAM +system.physmem.writeBursts 118023 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25893824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 7551936 # Total number of bytes written to DRAM system.physmem.bytesReadSys 25900928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7553600 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesWrittenSys 7553472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41706 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25487 # Per bank write bursts -system.physmem.perBankRdBursts::1 25728 # Per bank write bursts -system.physmem.perBankRdBursts::2 25822 # Per bank write bursts -system.physmem.perBankRdBursts::3 25769 # Per bank write bursts -system.physmem.perBankRdBursts::4 25085 # Per bank write bursts -system.physmem.perBankRdBursts::5 25016 # Per bank write bursts -system.physmem.perBankRdBursts::6 24650 # Per bank write bursts -system.physmem.perBankRdBursts::7 24524 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 41707 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25482 # Per bank write bursts +system.physmem.perBankRdBursts::1 25721 # Per bank write bursts +system.physmem.perBankRdBursts::2 25818 # Per bank write bursts +system.physmem.perBankRdBursts::3 25768 # Per bank write bursts +system.physmem.perBankRdBursts::4 25084 # Per bank write bursts +system.physmem.perBankRdBursts::5 25019 # Per bank write bursts +system.physmem.perBankRdBursts::6 24651 # Per bank write bursts +system.physmem.perBankRdBursts::7 24525 # Per bank write bursts system.physmem.perBankRdBursts::8 25293 # Per bank write bursts -system.physmem.perBankRdBursts::9 25190 # Per bank write bursts -system.physmem.perBankRdBursts::10 25398 # Per bank write bursts -system.physmem.perBankRdBursts::11 24986 # Per bank write bursts -system.physmem.perBankRdBursts::12 24522 # Per bank write bursts -system.physmem.perBankRdBursts::13 25563 # Per bank write bursts -system.physmem.perBankRdBursts::14 25828 # Per bank write bursts -system.physmem.perBankRdBursts::15 25737 # Per bank write bursts -system.physmem.perBankWrBursts::0 7820 # Per bank write bursts -system.physmem.perBankWrBursts::1 7688 # Per bank write bursts -system.physmem.perBankWrBursts::2 8067 # Per bank write bursts +system.physmem.perBankRdBursts::9 25189 # Per bank write bursts +system.physmem.perBankRdBursts::10 25397 # Per bank write bursts +system.physmem.perBankRdBursts::11 24988 # Per bank write bursts +system.physmem.perBankRdBursts::12 24521 # Per bank write bursts +system.physmem.perBankRdBursts::13 25565 # Per bank write bursts +system.physmem.perBankRdBursts::14 25830 # Per bank write bursts +system.physmem.perBankRdBursts::15 25740 # Per bank write bursts +system.physmem.perBankWrBursts::0 7815 # Per bank write bursts +system.physmem.perBankWrBursts::1 7682 # Per bank write bursts +system.physmem.perBankWrBursts::2 8062 # Per bank write bursts system.physmem.perBankWrBursts::3 7737 # Per bank write bursts system.physmem.perBankWrBursts::4 7196 # Per bank write bursts -system.physmem.perBankWrBursts::5 7011 # Per bank write bursts -system.physmem.perBankWrBursts::6 6646 # Per bank write bursts -system.physmem.perBankWrBursts::7 6392 # Per bank write bursts -system.physmem.perBankWrBursts::8 7401 # Per bank write bursts -system.physmem.perBankWrBursts::9 6804 # Per bank write bursts -system.physmem.perBankWrBursts::10 7278 # Per bank write bursts -system.physmem.perBankWrBursts::11 6972 # Per bank write bursts +system.physmem.perBankWrBursts::5 7012 # Per bank write bursts +system.physmem.perBankWrBursts::6 6647 # Per bank write bursts +system.physmem.perBankWrBursts::7 6398 # Per bank write bursts +system.physmem.perBankWrBursts::8 7404 # Per bank write bursts +system.physmem.perBankWrBursts::9 6806 # Per bank write bursts +system.physmem.perBankWrBursts::10 7277 # Per bank write bursts +system.physmem.perBankWrBursts::11 6969 # Per bank write bursts system.physmem.perBankWrBursts::12 7052 # Per bank write bursts -system.physmem.perBankWrBursts::13 8008 # Per bank write bursts -system.physmem.perBankWrBursts::14 7983 # Per bank write bursts -system.physmem.perBankWrBursts::15 7942 # Per bank write bursts +system.physmem.perBankWrBursts::13 8011 # Per bank write bursts +system.physmem.perBankWrBursts::14 7982 # Per bank write bursts +system.physmem.perBankWrBursts::15 7949 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 1886187226500 # Total gap between requests +system.physmem.numWrRetry 29 # Number of times write queue was full causing retry +system.physmem.totGap 1887159671500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -100,10 +100,10 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118025 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402327 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118023 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402323 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,188 +148,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63594 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 525.931377 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 320.890659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 414.200803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14460 22.74% 22.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10997 17.29% 40.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4933 7.76% 47.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3625 5.70% 53.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2479 3.90% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1827 2.87% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1418 2.23% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1367 2.15% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22488 35.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63594 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5295 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.408121 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2902.928186 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5292 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 94 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.182842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.768050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 414.563237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14483 22.79% 22.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10991 17.29% 40.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4893 7.70% 47.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3583 5.64% 53.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2419 3.81% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1815 2.86% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1455 2.29% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1407 2.21% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22517 35.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63563 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.639515 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2907.321691 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5276 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5295 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5295 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.284608 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.797942 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.673735 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4676 88.31% 88.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 227 4.29% 92.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 77 1.45% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 16 0.30% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 14 0.26% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.11% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 7 0.13% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 9 0.17% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 7 0.13% 95.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 34 0.64% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 171 3.23% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 10 0.19% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.09% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.08% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 8 0.15% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5295 # Writes before turning the bus around for reads -system.physmem.totQLat 2213284250 # Total ticks spent queuing -system.physmem.totMemAccLat 9799496750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2022990000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5470.33 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5279 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5279 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.352529 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.833418 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.552708 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4665 88.37% 88.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 223 4.22% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 69 1.31% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 13 0.25% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 7 0.13% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 8 0.15% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 11 0.21% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 9 0.17% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 33 0.63% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 187 3.54% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 5 0.09% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 7 0.13% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.06% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 9 0.17% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5279 # Writes before turning the bus around for reads +system.physmem.totQLat 2194493000 # Total ticks spent queuing +system.physmem.totMemAccLat 9780574250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2022955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5423.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24220.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24173.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.72 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.72 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing -system.physmem.readRowHits 363516 # Number of row buffer hits during reads -system.physmem.writeRowHits 95485 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes -system.physmem.avgGap 3608360.06 # Average gap between requests +system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing +system.physmem.readRowHits 363582 # Number of row buffer hits during reads +system.physmem.writeRowHits 95445 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes +system.physmem.avgGap 3610234.20 # Average gap between requests system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 233845920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127594500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1576231800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 379449360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60326866845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1078799265750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1264640388495 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.471373 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1794467110750 # Time in different power states -system.physmem_0.memoryStateTime::REF 62984220000 # Time in different power states +system.physmem_0.actEnergy 233596440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127458375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1576130400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 379397520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 60352481790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1079356093500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1265285353785 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.470116 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1795392967750 # Time in different power states +system.physmem_0.memoryStateTime::REF 63016460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28744633000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28752031000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246924720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134730750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579632600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385171200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61494025635 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1077775442250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1264813061475 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.562919 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1792762379750 # Time in different power states -system.physmem_1.memoryStateTime::REF 62984220000 # Time in different power states +system.physmem_1.actEnergy 246939840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134739000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579679400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385236000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61300664820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1078524362250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1265431817070 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.547722 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1794008459000 # Time in different power states +system.physmem_1.memoryStateTime::REF 63016460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30449364000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30136553500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15004879 # Number of BP lookups -system.cpu.branchPred.condPredicted 13013312 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 375549 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10036322 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5207234 # Number of BTB hits +system.cpu.branchPred.lookups 14997890 # Number of BP lookups +system.cpu.branchPred.condPredicted 13009268 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 370594 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9393435 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5198350 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 51.883887 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808293 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 31321 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 55.340246 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32049 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9242647 # DTB read hits -system.cpu.dtb.read_misses 17811 # DTB read misses +system.cpu.dtb.read_hits 9241004 # DTB read hits +system.cpu.dtb.read_misses 17472 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766734 # DTB read accesses -system.cpu.dtb.write_hits 6385782 # DTB write hits -system.cpu.dtb.write_misses 2309 # DTB write misses +system.cpu.dtb.read_accesses 766036 # DTB read accesses +system.cpu.dtb.write_hits 6386411 # DTB write hits +system.cpu.dtb.write_misses 2301 # DTB write misses system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298407 # DTB write accesses -system.cpu.dtb.data_hits 15628429 # DTB hits -system.cpu.dtb.data_misses 20120 # DTB misses +system.cpu.dtb.write_accesses 298419 # DTB write accesses +system.cpu.dtb.data_hits 15627415 # DTB hits +system.cpu.dtb.data_misses 19773 # DTB misses system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1065141 # DTB accesses -system.cpu.itb.fetch_hits 4016387 # ITB hits -system.cpu.itb.fetch_misses 6834 # ITB misses -system.cpu.itb.fetch_acv 689 # ITB acv -system.cpu.itb.fetch_accesses 4023221 # ITB accesses +system.cpu.dtb.data_accesses 1064455 # DTB accesses +system.cpu.itb.fetch_hits 4013195 # ITB hits +system.cpu.itb.fetch_misses 6857 # ITB misses +system.cpu.itb.fetch_acv 677 # ITB acv +system.cpu.itb.fetch_accesses 4020052 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -342,39 +341,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 180216793 # number of cpu cycles simulated +system.cpu.numCycles 182043546 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56121694 # Number of instructions committed -system.cpu.committedOps 56121694 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2519198 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5577 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3592175193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.211179 # CPI: cycles per instruction -system.cpu.ipc 0.311412 # IPC: instructions per cycle +system.cpu.committedInsts 56125948 # Number of instructions committed +system.cpu.committedOps 56125948 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2502558 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5565 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3594204473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.243483 # CPI: cycles per instruction +system.cpu.ipc 0.308311 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211471 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74788 40.94% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73421 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73422 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148877 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833775262000 97.22% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 81341000 0.00% 97.23% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 679703500 0.04% 97.26% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 51658703500 2.74% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1886195010000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211461 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74782 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1902 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105860 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73415 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1902 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73415 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1834747397000 97.22% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80828500 0.00% 97.23% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 680298500 0.04% 97.26% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51658959000 2.74% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1887167483000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693550 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814934 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693510 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814906 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -413,8 +412,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175525 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175514 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed @@ -422,7 +421,7 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5127 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192408 # number of callpals executed +system.cpu.kern.callpal::total 192398 # number of callpals executed system.cpu.kern.mode_switch::kernel 5868 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches @@ -433,92 +432,92 @@ system.cpu.kern.mode_switch_good::kernel 0.324983 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080114 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.393034 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36513483500 1.94% 1.94% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4123557000 0.22% 2.15% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1845557959500 97.85% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 36501486500 1.93% 1.93% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4115911000 0.22% 2.15% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1846550075500 97.85% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4173 # number of times the context was actually changed -system.cpu.tickCycles 84408299 # Number of cycles that the object actually ticked -system.cpu.idleCycles 95808494 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395428 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.981685 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13773051 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395940 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.866506 # Average number of references to valid blocks. +system.cpu.tickCycles 86269078 # Number of cycles that the object actually ticked +system.cpu.idleCycles 95774468 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395484 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.981722 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13771544 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395996 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.865031 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 90850500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.981685 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.981722 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63660654 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63660654 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7815445 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815445 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5575784 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5575784 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182800 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182800 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198989 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198989 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13391229 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13391229 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13391229 # number of overall hits -system.cpu.dcache.overall_hits::total 13391229 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201797 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201797 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 574153 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 574153 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17210 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17210 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1775950 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775950 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1775950 # number of overall misses -system.cpu.dcache.overall_misses::total 1775950 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32866409500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32866409500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22318082000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22318082000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230873000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 230873000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55184491500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55184491500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55184491500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55184491500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9017242 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9017242 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6149937 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149937 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200010 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200010 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198989 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198989 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15167179 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15167179 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15167179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15167179 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133278 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133278 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093359 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093359 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086046 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086046 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117092 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117092 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117092 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117092 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27347.721371 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27347.721371 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38871.314789 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38871.314789 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13415.049390 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13415.049390 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31073.223627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31073.223627 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63656757 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63656757 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7813939 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7813939 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5575873 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5575873 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182717 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182717 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198981 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198981 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13389812 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13389812 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13389812 # number of overall hits +system.cpu.dcache.overall_hits::total 13389812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201834 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201834 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 574561 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 574561 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17285 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17285 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1776395 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1776395 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1776395 # number of overall misses +system.cpu.dcache.overall_misses::total 1776395 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32870602000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32870602000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22298477500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22298477500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232185000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232185000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55169079500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55169079500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55169079500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55169079500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9015773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9015773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6150434 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150434 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198981 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198981 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15166207 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15166207 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15166207 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15166207 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133303 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133303 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093418 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093418 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086424 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086424 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117128 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27350.367854 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27350.367854 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38809.591149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38809.591149 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13432.745155 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13432.745155 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31056.763558 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31056.763558 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -527,129 +526,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838228 # number of writebacks -system.cpu.dcache.writebacks::total 838228 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127318 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127318 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269861 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269861 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838310 # number of writebacks +system.cpu.dcache.writebacks::total 838310 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127379 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127379 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270264 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 270264 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 397179 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 397179 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 397179 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 397179 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074479 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074479 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304292 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304292 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17207 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17207 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378771 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378771 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378771 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378771 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29864669500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29864669500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11367980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11367980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 213500500 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3493554500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3493554500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119158 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119158 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049479 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049479 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086031 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086031 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090905 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090905 # 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number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272179 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272179 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16403 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388713 # number of demand (read+write) MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16406 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16406 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272166 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272166 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16406 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388710 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 405116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16403 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388713 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16406 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388710 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 405116 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 431000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 431000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7770532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7770532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1160467500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1160467500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17006826000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17006826000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1160467500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24777358000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25937825500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1160467500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24777358000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25937825500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364748500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364748500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931469000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931469000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3296217500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3296217500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 453499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 453499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7758089500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7758089500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1150653000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1150653000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17010167000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17010167000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1150653000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24768256500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25918909500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1150653000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24768256500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25918909500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363977000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363977000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1930958000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1930958000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3294935000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3294935000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011238 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249327 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249327 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141868 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141868 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26937.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26937.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66680.385124 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66680.385124 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70747.271841 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70747.271841 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62483.975619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62483.975619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196819.800981 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196819.800981 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200755.534768 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200755.534768 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199107.067351 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199107.067351 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382982 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382982 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011239 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249303 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249303 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141862 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141862 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26676.411765 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26676.411765 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66567.901393 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66567.901393 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70136.108741 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70136.108741 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62499.235761 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62499.235761 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196822.077922 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196822.077922 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200723.284823 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200723.284823 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199089.728097 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199089.728097 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 956270 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2277118 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 956362 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2277135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304307 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304307 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459755 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091879 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377747 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219297 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8597044 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93416704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041221 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236457925 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422839 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6149292 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219455 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8597358 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93420352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143049956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236470308 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422854 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6149527 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.068727 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.252990 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.252989 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5726669 93.13% 93.13% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 422623 6.87% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5726891 93.13% 93.13% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 422636 6.87% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6149292 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3706373000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6149527 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3706565999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2189771045 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2189850563 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105677995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105755497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -934,43 +933,43 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7107 # Transaction distribution -system.iobus.trans_dist::ReadResp 7107 # Transaction distribution -system.iobus.trans_dist::WriteReq 51173 # Transaction distribution -system.iobus.trans_dist::WriteResp 51173 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5104 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7103 # Transaction distribution +system.iobus.trans_dist::ReadResp 7103 # Transaction distribution +system.iobus.trans_dist::WriteReq 51172 # Transaction distribution +system.iobus.trans_dist::WriteResp 51172 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5096 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33100 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20416 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20384 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44357 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44324 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705965 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4712000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705932 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4707000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -984,7 +983,7 @@ system.iobus.reqLayer23.occupancy 13484000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -992,23 +991,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216063756 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216043265 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23489000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23480000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.294607 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.302220 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1729988854000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.294607 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080913 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080913 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1729987199000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.302220 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081389 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081389 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1024,8 +1023,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907200873 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907200873 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908791382 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4908791382 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles @@ -1048,17 +1047,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118097.826170 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118097.826170 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118136.103725 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118136.103725 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1074,8 +1073,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829600873 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829600873 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831191382 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2831191382 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles @@ -1090,61 +1089,61 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68097.826170 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68097.826170 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68136.103725 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68136.103725 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 6934 # Transaction distribution -system.membus.trans_dist::ReadResp 295673 # Transaction distribution -system.membus.trans_dist::WriteReq 9621 # Transaction distribution -system.membus.trans_dist::WriteResp 9621 # Transaction distribution -system.membus.trans_dist::Writeback 118025 # Transaction distribution -system.membus.trans_dist::CleanEvict 262175 # Transaction distribution -system.membus.trans_dist::UpgradeReq 156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 156 # Transaction distribution -system.membus.trans_dist::ReadExReq 116394 # Transaction distribution -system.membus.trans_dist::ReadExResp 116394 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288755 # Transaction distribution +system.membus.trans_dist::ReadReq 6930 # Transaction distribution +system.membus.trans_dist::ReadResp 295659 # Transaction distribution +system.membus.trans_dist::WriteReq 9620 # Transaction distribution +system.membus.trans_dist::WriteResp 9620 # Transaction distribution +system.membus.trans_dist::Writeback 118023 # Transaction distribution +system.membus.trans_dist::CleanEvict 262178 # Transaction distribution +system.membus.trans_dist::UpgradeReq 157 # Transaction distribution +system.membus.trans_dist::UpgradeResp 157 # Transaction distribution +system.membus.trans_dist::ReadExReq 116404 # Transaction distribution +system.membus.trans_dist::ReadExResp 116404 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148635 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181774 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181767 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306591 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44357 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30841157 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1306584 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44324 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30840996 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33498885 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33498724 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 843789 # Request fanout histogram +system.membus.snoop_fanout::samples 843798 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843789 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843798 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843789 # Request fanout histogram -system.membus.reqLayer0.occupancy 29576000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843798 # Request fanout histogram +system.membus.reqLayer0.occupancy 29290000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1318697936 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1318757186 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160007596 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160035845 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72031934 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72019946 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 2b4d92c81..08ac5b1cf 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -166,7 +166,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -513,7 +513,7 @@ opLat=3 pipelined=false [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -671,7 +671,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu1.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -1018,7 +1018,7 @@ opLat=3 pipelined=false [system.cpu1.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -1151,7 +1151,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 @@ -1186,7 +1186,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index e5b1b4540..7571a76a8 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.907980 # Number of seconds simulated -sim_ticks 1907980084000 # Number of ticks simulated -final_tick 1907980084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906957 # Number of seconds simulated +sim_ticks 1906956794000 # Number of ticks simulated +final_tick 1906956794000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 144634 # Simulator instruction rate (inst/s) -host_op_rate 144633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4918211693 # Simulator tick rate (ticks/s) -host_mem_usage 381420 # Number of bytes of host memory used -host_seconds 387.94 # Real time elapsed on the host -sim_insts 56109384 # Number of instructions simulated -sim_ops 56109384 # Number of ops (including micro ops) simulated +host_inst_rate 101212 # Simulator instruction rate (inst/s) +host_op_rate 101212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3411514986 # Simulator tick rate (ticks/s) +host_mem_usage 375140 # Number of bytes of host memory used +host_seconds 558.98 # Real time elapsed on the host +sim_insts 56575230 # Number of instructions simulated +sim_ops 56575230 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 744000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24138496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 236608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1227584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 862400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24773696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 117248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 514752 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26347648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 744000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 236608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 980608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7952896 # Number of bytes written to this memory -system.physmem.bytes_written::total 7952896 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3697 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 19181 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26269056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 862400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 117248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 979648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7861568 # Number of bytes written to this memory +system.physmem.bytes_written::total 7861568 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1832 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8043 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411682 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124264 # Number of write requests responded to by this memory -system.physmem.num_writes::total 124264 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 389941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12651335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 124010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 643395 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 410454 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122837 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122837 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 452239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12991220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 61484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 269934 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13809184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 124010 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4168228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4168228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4168228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12651335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 124010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 643395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13775381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 452239 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 61484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4122573 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4122573 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4122573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 452239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12991220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 61484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 269934 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17977412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411682 # Number of read requests accepted -system.physmem.writeReqs 124264 # Number of write requests accepted -system.physmem.readBursts 411682 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 124264 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26340672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 7951552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26347648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7952896 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17897953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410454 # Number of read requests accepted +system.physmem.writeReqs 122837 # Number of write requests accepted +system.physmem.readBursts 410454 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122837 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue +system.physmem.bytesWritten 7860160 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26269056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7861568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 45002 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25908 # Per bank write bursts -system.physmem.perBankRdBursts::1 25789 # Per bank write bursts -system.physmem.perBankRdBursts::2 26010 # Per bank write bursts -system.physmem.perBankRdBursts::3 25614 # Per bank write bursts -system.physmem.perBankRdBursts::4 25643 # Per bank write bursts -system.physmem.perBankRdBursts::5 25797 # Per bank write bursts -system.physmem.perBankRdBursts::6 25922 # Per bank write bursts -system.physmem.perBankRdBursts::7 25550 # Per bank write bursts -system.physmem.perBankRdBursts::8 25897 # Per bank write bursts -system.physmem.perBankRdBursts::9 25701 # Per bank write bursts -system.physmem.perBankRdBursts::10 25484 # Per bank write bursts -system.physmem.perBankRdBursts::11 25508 # Per bank write bursts -system.physmem.perBankRdBursts::12 25696 # Per bank write bursts -system.physmem.perBankRdBursts::13 25817 # Per bank write bursts -system.physmem.perBankRdBursts::14 25547 # Per bank write bursts -system.physmem.perBankRdBursts::15 25690 # Per bank write bursts -system.physmem.perBankWrBursts::0 7970 # Per bank write bursts -system.physmem.perBankWrBursts::1 7556 # Per bank write bursts -system.physmem.perBankWrBursts::2 7711 # Per bank write bursts -system.physmem.perBankWrBursts::3 7606 # Per bank write bursts -system.physmem.perBankWrBursts::4 7633 # Per bank write bursts -system.physmem.perBankWrBursts::5 7951 # Per bank write bursts -system.physmem.perBankWrBursts::6 7934 # Per bank write bursts -system.physmem.perBankWrBursts::7 7815 # Per bank write bursts -system.physmem.perBankWrBursts::8 8060 # Per bank write bursts -system.physmem.perBankWrBursts::9 8044 # Per bank write bursts -system.physmem.perBankWrBursts::10 7565 # Per bank write bursts -system.physmem.perBankWrBursts::11 7446 # Per bank write bursts -system.physmem.perBankWrBursts::12 7634 # Per bank write bursts -system.physmem.perBankWrBursts::13 8000 # Per bank write bursts -system.physmem.perBankWrBursts::14 7754 # Per bank write bursts -system.physmem.perBankWrBursts::15 7564 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 46373 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26161 # Per bank write bursts +system.physmem.perBankRdBursts::1 25973 # Per bank write bursts +system.physmem.perBankRdBursts::2 26108 # Per bank write bursts +system.physmem.perBankRdBursts::3 25765 # Per bank write bursts +system.physmem.perBankRdBursts::4 25066 # Per bank write bursts +system.physmem.perBankRdBursts::5 25574 # Per bank write bursts +system.physmem.perBankRdBursts::6 25905 # Per bank write bursts +system.physmem.perBankRdBursts::7 25241 # Per bank write bursts +system.physmem.perBankRdBursts::8 25825 # Per bank write bursts +system.physmem.perBankRdBursts::9 26325 # Per bank write bursts +system.physmem.perBankRdBursts::10 25290 # Per bank write bursts +system.physmem.perBankRdBursts::11 25205 # Per bank write bursts +system.physmem.perBankRdBursts::12 25472 # Per bank write bursts +system.physmem.perBankRdBursts::13 25390 # Per bank write bursts +system.physmem.perBankRdBursts::14 25632 # Per bank write bursts +system.physmem.perBankRdBursts::15 25396 # Per bank write bursts +system.physmem.perBankWrBursts::0 8442 # Per bank write bursts +system.physmem.perBankWrBursts::1 7958 # Per bank write bursts +system.physmem.perBankWrBursts::2 8052 # Per bank write bursts +system.physmem.perBankWrBursts::3 7723 # Per bank write bursts +system.physmem.perBankWrBursts::4 7027 # Per bank write bursts +system.physmem.perBankWrBursts::5 7199 # Per bank write bursts +system.physmem.perBankWrBursts::6 7428 # Per bank write bursts +system.physmem.perBankWrBursts::7 6815 # Per bank write bursts +system.physmem.perBankWrBursts::8 7536 # Per bank write bursts +system.physmem.perBankWrBursts::9 7897 # Per bank write bursts +system.physmem.perBankWrBursts::10 7294 # Per bank write bursts +system.physmem.perBankWrBursts::11 7366 # Per bank write bursts +system.physmem.perBankWrBursts::12 7733 # Per bank write bursts +system.physmem.perBankWrBursts::13 8096 # Per bank write bursts +system.physmem.perBankWrBursts::14 8387 # Per bank write bursts +system.physmem.perBankWrBursts::15 7862 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 1907975777500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 1906952476500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411682 # Read request sizes (log2) +system.physmem.readPktSize::6 410454 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124264 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122837 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,204 +158,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 46 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65129 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.524774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 320.940318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.518091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14691 22.56% 22.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11476 17.62% 40.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5283 8.11% 48.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3332 5.12% 53.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2563 3.94% 57.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1696 2.60% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1442 2.21% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1386 2.13% 64.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23260 35.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65129 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.233096 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2814.761745 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5617 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.098216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.146393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.677441 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14983 23.10% 23.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11330 17.47% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5177 7.98% 48.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3304 5.09% 53.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2428 3.74% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1616 2.49% 59.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1474 2.27% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1311 2.02% 64.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23234 35.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64857 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5518 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.361182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2842.300525 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5515 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5620 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.107295 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.769658 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.265728 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4863 86.53% 86.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 151 2.69% 89.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 190 3.38% 92.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 20 0.36% 92.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 26 0.46% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 52 0.93% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.25% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 94.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.04% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.04% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.11% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.12% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.14% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.09% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.05% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.14% 95.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 8 0.14% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 26 0.46% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 16 0.28% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 144 2.56% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.21% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.04% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.04% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.05% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 6 0.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 7 0.12% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 5 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5620 # Writes before turning the bus around for reads -system.physmem.totQLat 4128600500 # Total ticks spent queuing -system.physmem.totMemAccLat 11845594250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2057865000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10031.27 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5518 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5518 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.257158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.834122 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.444866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4906 88.91% 88.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 212 3.84% 92.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 76 1.38% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 18 0.33% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 9 0.16% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 6 0.11% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 17 0.31% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 11 0.20% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 35 0.63% 95.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 173 3.14% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.14% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.09% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.09% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 6 0.11% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 4 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5518 # Writes before turning the bus around for reads +system.physmem.totQLat 4043689250 # Total ticks spent queuing +system.physmem.totMemAccLat 11737339250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9854.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28781.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28604.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.21 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.72 # Average write queue length when enqueuing -system.physmem.readRowHits 370844 # Number of row buffer hits during reads -system.physmem.writeRowHits 99842 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.35 # Row buffer hit rate for writes -system.physmem.avgGap 3560014.96 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1608188400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 402589440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57486510675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1094357699250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278853275255 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.267627 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1820391723000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63711440000 # Time in different power states +system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing +system.physmem.readRowHits 369741 # Number of row buffer hits during reads +system.physmem.writeRowHits 98545 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.22 # Row buffer hit rate for writes +system.physmem.avgGap 3575819.72 # Average gap between requests +system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 242910360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132540375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1605185400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392973120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57318973425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1093892654250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278138192210 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.251160 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1819616623000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63677380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23872193000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23660103250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247287600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134928750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1601652000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 402194160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57648050955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1094215997250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278869687355 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.276229 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1820158780750 # Time in different power states -system.physmem_1.memoryStateTime::REF 63711440000 # Time in different power states +system.physmem_1.actEnergy 247408560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134994750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1595373000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 402868080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57679570530 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1093576349250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278189519450 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.278071 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1819088073250 # Time in different power states +system.physmem_1.memoryStateTime::REF 63677380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24103898000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24188666750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 11788808 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10301623 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 235567 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7623393 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4144660 # Number of BTB hits +system.cpu0.branchPred.lookups 16421216 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14369135 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 322041 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10416019 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5388507 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 54.367655 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 590548 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 12472 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 51.732884 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 814349 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 18392 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7021210 # DTB read hits -system.cpu0.dtb.read_misses 28922 # DTB read misses +system.cpu0.dtb.read_hits 9282981 # DTB read hits +system.cpu0.dtb.read_misses 32197 # DTB read misses system.cpu0.dtb.read_acv 549 # DTB read access violations -system.cpu0.dtb.read_accesses 680178 # DTB read accesses -system.cpu0.dtb.write_hits 4516223 # DTB write hits -system.cpu0.dtb.write_misses 6969 # DTB write misses -system.cpu0.dtb.write_acv 383 # DTB write access violations -system.cpu0.dtb.write_accesses 234540 # DTB write accesses -system.cpu0.dtb.data_hits 11537433 # DTB hits -system.cpu0.dtb.data_misses 35891 # DTB misses -system.cpu0.dtb.data_acv 932 # DTB access violations -system.cpu0.dtb.data_accesses 914718 # DTB accesses -system.cpu0.itb.fetch_hits 1192769 # ITB hits -system.cpu0.itb.fetch_misses 29243 # ITB misses -system.cpu0.itb.fetch_acv 632 # ITB acv -system.cpu0.itb.fetch_accesses 1222012 # ITB accesses +system.cpu0.dtb.read_accesses 681404 # DTB read accesses +system.cpu0.dtb.write_hits 5956980 # DTB write hits +system.cpu0.dtb.write_misses 7300 # DTB write misses +system.cpu0.dtb.write_acv 382 # DTB write access violations +system.cpu0.dtb.write_accesses 235779 # DTB write accesses +system.cpu0.dtb.data_hits 15239961 # DTB hits +system.cpu0.dtb.data_misses 39497 # DTB misses +system.cpu0.dtb.data_acv 931 # DTB access violations +system.cpu0.dtb.data_accesses 917183 # DTB accesses +system.cpu0.itb.fetch_hits 1451467 # ITB hits +system.cpu0.itb.fetch_misses 20802 # ITB misses +system.cpu0.itb.fetch_acv 603 # ITB acv +system.cpu0.itb.fetch_accesses 1472269 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -368,598 +351,598 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 94258709 # number of cpu cycles simulated +system.cpu0.numCycles 115722397 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18560589 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 53027757 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 11788808 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4735208 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 69979824 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 806070 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 422 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1456351 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 296845 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 178 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6342869 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 170274 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 90723047 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.584501 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.854201 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26666578 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 71121267 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16421216 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6202856 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 81967119 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1079386 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 563 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 29093 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 971886 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 464461 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8198819 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 234916 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 110639677 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.642819 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.946891 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 80634947 88.88% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 672953 0.74% 89.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1448081 1.60% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 584574 0.64% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2111688 2.33% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 463915 0.51% 94.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 450869 0.50% 95.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 614781 0.68% 95.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3741239 4.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 97354556 87.99% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 847860 0.77% 88.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1824694 1.65% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 789927 0.71% 91.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2609447 2.36% 93.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576925 0.52% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 654110 0.59% 94.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 850099 0.77% 95.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5132059 4.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 90723047 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.125069 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.562577 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 14977569 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 67686915 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6257157 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1423439 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 377966 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 370983 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 25389 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 46677806 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 79994 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 377966 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 15660908 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 46083028 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14369152 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6948168 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7283823 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 45068314 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 191995 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1547824 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 115834 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4229403 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 30289226 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 55138176 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 55047778 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 82793 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 26689501 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 3599717 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1126936 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 168790 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10038208 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7066684 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4739993 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1073845 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 760534 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 40346624 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1418133 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 39715880 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 51531 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 4979263 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2318512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 978590 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 90723047 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.437771 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.168840 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 110639677 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.141902 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.614585 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21680681 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78105435 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8575313 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1774700 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 503547 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 522363 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 36577 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62219552 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 111460 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 503547 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22526069 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 50558199 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19082823 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9419071 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8549966 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 60053732 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 197896 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2013708 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 145060 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4631346 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 40115150 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72965738 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72822559 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 133404 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 35357429 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4757713 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1490349 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 215164 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12632454 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9363221 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6214194 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1348186 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 960020 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53527289 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1914294 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52757497 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 50335 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6507909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2851663 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1318911 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 110639677 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.476841 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.213091 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74240349 81.83% 81.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7278177 8.02% 89.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3014429 3.32% 93.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2002130 2.21% 95.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2057446 2.27% 97.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1059416 1.17% 98.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 709655 0.78% 99.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 273899 0.30% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 87546 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 88942477 80.39% 80.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9398072 8.49% 88.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3917958 3.54% 92.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2747278 2.48% 94.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2855598 2.58% 97.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1392573 1.26% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 913992 0.83% 99.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 361366 0.33% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 110363 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 90723047 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 110639677 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 128942 17.20% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 362987 48.42% 65.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 257779 34.38% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 181613 18.32% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 474655 47.88% 66.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 334992 33.79% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3788 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 27155018 68.37% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 40485 0.10% 68.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.48% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25259 0.06% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7282480 18.34% 86.89% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4576355 11.52% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 630612 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36170574 68.56% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57549 0.11% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28793 0.05% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9634233 18.26% 87.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6027526 11.42% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 833151 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 39715880 # Type of FU issued -system.cpu0.iq.rate 0.421350 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 749708 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018877 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 170597233 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 46586090 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 38643243 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 358812 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 172505 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 165745 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 40269961 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 191839 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 469267 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52757497 # Type of FU issued +system.cpu0.iq.rate 0.455897 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 991260 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018789 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 216609620 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61691492 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51347656 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 586645 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 275208 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 269627 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53428897 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 316072 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 584424 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 864378 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3380 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 14864 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 401917 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1070558 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2876 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17548 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 473318 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 11804 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 365714 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 412098 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 377966 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 43619498 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 675796 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 44202753 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 88904 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7066684 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4739993 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1257449 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 23012 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 538948 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 14864 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 117466 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 265776 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 383242 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 39342618 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7067139 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 373261 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 503547 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 47448039 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 802619 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58859222 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 120684 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9363221 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6214194 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1691778 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39350 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 562336 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17548 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 158131 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 358107 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 516238 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 52248436 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9338690 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 509060 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2437996 # number of nop insts executed -system.cpu0.iew.exec_refs 11599884 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6171265 # Number of branches executed -system.cpu0.iew.exec_stores 4532745 # Number of stores executed -system.cpu0.iew.exec_rate 0.417390 # Inst execution rate -system.cpu0.iew.wb_sent 38908729 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 38808988 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 20149850 # num instructions producing a value -system.cpu0.iew.wb_consumers 27578035 # num instructions consuming a value +system.cpu0.iew.exec_nop 3417639 # number of nop insts executed +system.cpu0.iew.exec_refs 15316719 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8298030 # Number of branches executed +system.cpu0.iew.exec_stores 5978029 # Number of stores executed +system.cpu0.iew.exec_rate 0.451498 # Inst execution rate +system.cpu0.iew.wb_sent 51729756 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51617283 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26562977 # num instructions producing a value +system.cpu0.iew.wb_consumers 36791821 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.411728 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.730649 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.446044 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.721980 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5183738 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 439543 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 349838 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 89803768 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.433386 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.354442 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6839384 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 595383 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 473671 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 109429659 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.474443 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.410223 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 76032999 84.67% 84.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5542678 6.17% 90.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2869062 3.19% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1578965 1.76% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1284314 1.43% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 412798 0.46% 97.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 324191 0.36% 98.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 314453 0.35% 98.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1444308 1.61% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 91094862 83.25% 83.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7261881 6.64% 89.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3995871 3.65% 93.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2069124 1.89% 95.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1633444 1.49% 96.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 582030 0.53% 97.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 441609 0.40% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 443115 0.40% 98.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1907723 1.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 89803768 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 38919724 # Number of instructions committed -system.cpu0.commit.committedOps 38919724 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 109429659 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51918164 # Number of instructions committed +system.cpu0.commit.committedOps 51918164 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10540382 # Number of memory references committed -system.cpu0.commit.loads 6202306 # Number of loads committed -system.cpu0.commit.membars 144405 # Number of memory barriers committed -system.cpu0.commit.branches 5839773 # Number of branches committed -system.cpu0.commit.fp_insts 162063 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 36166381 # Number of committed integer instructions. -system.cpu0.commit.function_calls 471449 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2138002 5.49% 5.49% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 25394964 65.25% 70.74% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 39484 0.10% 70.84% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.84% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 24801 0.06% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6346711 16.31% 87.22% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 4343267 11.16% 98.38% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 630612 1.62% 100.00% # Class of committed instruction +system.cpu0.commit.refs 14033539 # Number of memory references committed +system.cpu0.commit.loads 8292663 # Number of loads committed +system.cpu0.commit.membars 202804 # Number of memory barriers committed +system.cpu0.commit.branches 7846921 # Number of branches committed +system.cpu0.commit.fp_insts 266538 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 48077974 # Number of committed integer instructions. +system.cpu0.commit.function_calls 666824 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2988262 5.76% 5.76% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33767854 65.04% 70.80% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 56339 0.11% 70.90% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.90% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28331 0.05% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8495467 16.36% 87.33% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5746879 11.07% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 833149 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 38919724 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1444308 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 132264444 # The number of ROB reads -system.cpu0.rob.rob_writes 89122078 # The number of ROB writes -system.cpu0.timesIdled 337516 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3535662 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3721701460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 36785489 # Number of Instructions Simulated -system.cpu0.committedOps 36785489 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.562388 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.562388 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.390261 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.390261 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 51878765 # number of integer regfile reads -system.cpu0.int_regfile_writes 28204778 # number of integer regfile writes -system.cpu0.fp_regfile_reads 81728 # number of floating regfile reads -system.cpu0.fp_regfile_writes 81429 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1387632 # number of misc regfile reads -system.cpu0.misc_regfile_writes 636485 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 898491 # number of replacements -system.cpu0.dcache.tags.tagsinuse 481.994698 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 8012262 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 899003 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.912386 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.994698 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941396 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.941396 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 51918164 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1907723 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 166079481 # The number of ROB reads +system.cpu0.rob.rob_writes 118719518 # The number of ROB writes +system.cpu0.timesIdled 511712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5082720 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3698191192 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48933669 # Number of Instructions Simulated +system.cpu0.committedOps 48933669 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.364883 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.364883 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.422854 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.422854 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68649325 # number of integer regfile reads +system.cpu0.int_regfile_writes 37335516 # number of integer regfile writes +system.cpu0.fp_regfile_reads 132501 # number of floating regfile reads +system.cpu0.fp_regfile_writes 134063 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1824055 # number of misc regfile reads +system.cpu0.misc_regfile_writes 833586 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1296864 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.135915 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10665502 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1297376 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.220826 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26097500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.135915 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988547 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988547 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 43230678 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 43230678 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5046736 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5046736 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2679789 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2679789 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129628 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 129628 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149296 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149296 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7726525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7726525 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7726525 # number of overall hits -system.cpu0.dcache.overall_hits::total 7726525 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1067598 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1067598 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1496200 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1496200 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12202 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12202 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 769 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 769 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2563798 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2563798 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2563798 # number of overall misses -system.cpu0.dcache.overall_misses::total 2563798 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 32014122500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 32014122500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69455032918 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 69455032918 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 190587000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 190587000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5445000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5445000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 101469155418 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 101469155418 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 101469155418 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 101469155418 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6114334 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6114334 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4175989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4175989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 141830 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 141830 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150065 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 150065 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10290323 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10290323 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10290323 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10290323 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.174606 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.174606 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358286 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.358286 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086033 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086033 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005124 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005124 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249147 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249147 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249147 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249147 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29987.057394 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29987.057394 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46420.955031 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46420.955031 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15619.324701 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15619.324701 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7080.624187 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7080.624187 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39577.671649 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39577.671649 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4094264 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5021 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 103728 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 39.471155 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 53.414894 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 57664711 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 57664711 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6558537 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6558537 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3738792 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3738792 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165967 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 165967 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191452 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191452 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10297329 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10297329 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10297329 # number of overall hits +system.cpu0.dcache.overall_hits::total 10297329 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1618045 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1618045 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1793563 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1793563 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21339 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21339 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2425 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2425 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3411608 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3411608 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3411608 # number of overall misses +system.cpu0.dcache.overall_misses::total 3411608 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39371994500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39371994500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77781772548 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77781772548 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331348500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 331348500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20480000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20480000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117153767048 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117153767048 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117153767048 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117153767048 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8176582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8176582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5532355 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5532355 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 187306 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 187306 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193877 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 193877 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13708937 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13708937 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13708937 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13708937 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197888 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197888 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324195 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324195 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113926 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113926 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012508 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012508 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248860 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248860 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248860 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248860 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24333.065211 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24333.065211 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43367.181720 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43367.181720 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15527.836356 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15527.836356 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8445.360825 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8445.360825 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34339.750361 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34339.750361 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4364063 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4809 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 121083 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 97 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.041913 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 49.577320 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 426068 # number of writebacks -system.cpu0.dcache.writebacks::total 426068 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 384761 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 384761 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1282051 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1282051 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3514 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3514 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1666812 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1666812 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1666812 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1666812 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 682837 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 682837 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 214149 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 214149 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8688 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8688 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 769 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 769 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 896986 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 896986 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 896986 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 896986 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4777 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8020 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 12797 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25205904500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25205904500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10851652245 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10851652245 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107603000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107603000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36057556745 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 36057556745 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36057556745 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 36057556745 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1013290500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1013290500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1707574498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1707574498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2720864998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2720864998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111678 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111678 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051281 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051281 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005124 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005124 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.087168 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.087168 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36913.501319 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36913.501319 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50673.373422 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50673.373422 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12385.244015 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12385.244015 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6080.624187 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6080.624187 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212118.589073 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212118.589073 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212914.525935 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212914.525935 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212617.410174 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212617.410174 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 766891 # number of writebacks +system.cpu0.dcache.writebacks::total 766891 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 594303 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 594303 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523628 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1523628 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5200 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5200 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2117931 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2117931 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2117931 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2117931 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1023742 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1023742 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 269935 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 269935 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16139 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16139 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1293677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1293677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1293677 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1293677 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7035 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7035 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10024 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10024 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17059 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17059 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29563027500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29563027500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12280270109 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12280270109 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188351000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188351000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18055000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18055000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41843297609 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 41843297609 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41843297609 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 41843297609 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1480741500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1480741500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2153066498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2153066498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3633807998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3633807998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048792 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048792 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012508 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012508 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094367 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094367 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28877.419799 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28877.419799 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45493.434008 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45493.434008 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11670.549600 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11670.549600 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7445.360825 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7445.360825 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210482.089552 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210482.089552 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214791.151038 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214791.151038 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 213014.127323 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 213014.127323 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 615978 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.684225 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5692804 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 616490 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.234220 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28149663500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.684225 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993524 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993524 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 927295 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.382377 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7224199 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 927807 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.786317 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28149280500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.382377 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994887 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994887 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 6959538 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 6959538 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5692804 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5692804 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5692804 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5692804 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5692804 # number of overall hits -system.cpu0.icache.overall_hits::total 5692804 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 650065 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 650065 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 650065 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 650065 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 650065 # number of overall misses -system.cpu0.icache.overall_misses::total 650065 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9309214992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9309214992 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9309214992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9309214992 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9309214992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9309214992 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6342869 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6342869 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6342869 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6342869 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6342869 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6342869 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102488 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.102488 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102488 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.102488 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102488 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.102488 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14320.437175 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14320.437175 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14320.437175 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14320.437175 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3481 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9126911 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9126911 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7224199 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7224199 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7224199 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7224199 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7224199 # number of overall hits +system.cpu0.icache.overall_hits::total 7224199 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 974618 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 974618 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 974618 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 974618 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 974618 # number of overall misses +system.cpu0.icache.overall_misses::total 974618 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13621983991 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13621983991 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13621983991 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13621983991 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13621983991 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13621983991 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8198817 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8198817 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8198817 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8198817 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8198817 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8198817 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118873 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118873 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118873 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118873 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118873 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118873 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13976.741647 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13976.741647 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13976.741647 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13976.741647 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5225 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 166 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.969880 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.738916 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33396 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33396 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33396 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33396 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33396 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33396 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 616669 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 616669 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 616669 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 616669 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 616669 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 616669 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8251915495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8251915495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8251915495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8251915495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8251915495 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8251915495 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097222 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.097222 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.097222 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13381.433954 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 46524 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 46524 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 46524 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 46524 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 46524 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 46524 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 928094 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 928094 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 928094 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 928094 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 928094 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 928094 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12135046494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12135046494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12135046494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12135046494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12135046494 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12135046494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113199 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113199 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113199 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13075.234291 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7710185 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6710334 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 163097 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4502045 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2070765 # Number of BTB hits +system.cpu1.branchPred.lookups 3314305 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2896651 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 61906 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1740825 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 779195 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 45.996097 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 394984 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 11166 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 44.760099 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 157645 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4636 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 4026297 # DTB read hits -system.cpu1.dtb.read_misses 14233 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 293572 # DTB read accesses -system.cpu1.dtb.write_hits 2497972 # DTB write hits -system.cpu1.dtb.write_misses 2408 # DTB write misses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_accesses 109195 # DTB write accesses -system.cpu1.dtb.data_hits 6524269 # DTB hits -system.cpu1.dtb.data_misses 16641 # DTB misses -system.cpu1.dtb.data_acv 43 # DTB access violations -system.cpu1.dtb.data_accesses 402767 # DTB accesses -system.cpu1.itb.fetch_hits 750930 # ITB hits -system.cpu1.itb.fetch_misses 5383 # ITB misses -system.cpu1.itb.fetch_acv 53 # ITB acv -system.cpu1.itb.fetch_accesses 756313 # ITB accesses +system.cpu1.dtb.read_hits 1755656 # DTB read hits +system.cpu1.dtb.read_misses 9508 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 286377 # DTB read accesses +system.cpu1.dtb.write_hits 1073642 # DTB write hits +system.cpu1.dtb.write_misses 1995 # DTB write misses +system.cpu1.dtb.write_acv 40 # DTB write access violations +system.cpu1.dtb.write_accesses 108795 # DTB write accesses +system.cpu1.dtb.data_hits 2829298 # DTB hits +system.cpu1.dtb.data_misses 11503 # DTB misses +system.cpu1.dtb.data_acv 45 # DTB access violations +system.cpu1.dtb.data_accesses 395172 # DTB accesses +system.cpu1.itb.fetch_hits 497795 # ITB hits +system.cpu1.itb.fetch_misses 4809 # ITB misses +system.cpu1.itb.fetch_acv 84 # ITB acv +system.cpu1.itb.fetch_accesses 502604 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -972,564 +955,563 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 34369930 # number of cpu cycles simulated +system.cpu1.numCycles 13378620 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 13361598 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 30714280 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7710185 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2465749 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 18120966 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 547594 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 46 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 23797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 211021 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 198154 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 3304195 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 117193 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 32189433 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.954173 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.349586 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5528968 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12732566 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3314305 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 936840 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 6841586 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 246622 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 24765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 177717 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 60433 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1438917 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 48462 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 12756788 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.998101 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.406721 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 26750456 83.10% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 307184 0.95% 84.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 618506 1.92% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 382121 1.19% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 801179 2.49% 89.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 249293 0.77% 90.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 334783 1.04% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 403446 1.25% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 2342465 7.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 10526481 82.52% 82.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 138708 1.09% 83.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 230541 1.81% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 169879 1.33% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 284565 2.23% 88.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 115144 0.90% 89.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 131557 1.03% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 159487 1.25% 92.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1000426 7.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 32189433 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.224329 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.893638 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 11124412 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16339992 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3934359 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 534571 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 256098 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 250042 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 17822 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 25897409 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 55799 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 256098 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 11423416 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 4918911 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 9329125 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 4131002 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2130879 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 24789451 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 5724 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 540758 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 43054 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 820253 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 16289258 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 29487961 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 29391972 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 88964 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 13777657 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2511601 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 753305 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 82405 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4252225 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4127805 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2629581 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 507300 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 331297 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 21789875 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 948507 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 21283611 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 28389 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3414486 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1484281 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 680406 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 32189433 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.661199 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.387208 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 12756788 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.247731 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.951710 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 4581654 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6264793 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1608431 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 184437 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 117472 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 99495 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5921 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 10317942 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 18589 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 117472 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 4714026 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 446929 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4987547 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1661018 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 829794 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 9788331 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3632 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 64825 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 14992 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 371131 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6443318 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 11674537 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 11622438 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 46696 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5463726 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 979592 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 407944 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 36440 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1686696 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1800249 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1144526 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 213224 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 121752 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 8623787 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 466284 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 8415044 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20175 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1448509 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 669329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 345933 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 12756788 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.659652 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.379213 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 23533399 73.11% 73.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3630192 11.28% 84.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1573878 4.89% 89.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1186258 3.69% 92.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 1178148 3.66% 96.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 546160 1.70% 98.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 337865 1.05% 99.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 151957 0.47% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 51576 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9236176 72.40% 72.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1557417 12.21% 84.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 656816 5.15% 89.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 459502 3.60% 93.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 405096 3.18% 96.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 217416 1.70% 98.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 137120 1.07% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 62655 0.49% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 24590 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 32189433 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 12756788 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 80499 16.46% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 246874 50.47% 66.92% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 161807 33.08% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22931 9.91% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 125391 54.21% 64.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 82988 35.88% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 14071465 66.11% 66.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 30174 0.14% 66.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 13456 0.06% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4194422 19.71% 86.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 2532925 11.90% 97.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 435892 2.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5217804 62.01% 62.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 14291 0.17% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10471 0.12% 62.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1829208 21.74% 84.10% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1094853 13.01% 97.11% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 243140 2.89% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 21283611 # Type of FU issued -system.cpu1.iq.rate 0.619251 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 489180 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.022984 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 74907239 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 25989017 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20583813 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 366985 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 171482 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 168729 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 21571772 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 197501 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 207443 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 8415044 # Type of FU issued +system.cpu1.iq.rate 0.628992 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 231310 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027488 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 29661025 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 10457474 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8106737 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 177336 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 85037 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 82464 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 8548271 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 94565 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 87834 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 572592 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 7837 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 247159 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 257024 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 716 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4046 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 124034 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 7441 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 131088 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 425 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 63290 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 256098 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4050515 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 319306 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 24169619 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 59065 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4127805 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2629581 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 846465 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33159 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 202940 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 7837 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 80858 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 187737 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 268595 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 21021510 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4051663 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 262101 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 117472 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 288545 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 130999 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 9554579 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 24166 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1800249 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1144526 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 424658 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4139 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 125975 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4046 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28597 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 88577 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 117174 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8309020 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1771054 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 106024 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1431237 # number of nop insts executed -system.cpu1.iew.exec_refs 6560061 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3322997 # Number of branches executed -system.cpu1.iew.exec_stores 2508398 # Number of stores executed -system.cpu1.iew.exec_rate 0.611625 # Inst execution rate -system.cpu1.iew.wb_sent 20805592 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 20752542 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10210202 # num instructions producing a value -system.cpu1.iew.wb_consumers 14612629 # num instructions consuming a value +system.cpu1.iew.exec_nop 464508 # number of nop insts executed +system.cpu1.iew.exec_refs 2851870 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1230259 # Number of branches executed +system.cpu1.iew.exec_stores 1080816 # Number of stores executed +system.cpu1.iew.exec_rate 0.621067 # Inst execution rate +system.cpu1.iew.wb_sent 8217653 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8189201 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 3916216 # num instructions producing a value +system.cpu1.iew.wb_consumers 5553340 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.603799 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.698725 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.612111 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.705200 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3582987 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 268101 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 243613 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31565232 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.650241 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.623237 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1470840 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 120351 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 107539 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 12487025 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.642311 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.620138 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 24282945 76.93% 76.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2976975 9.43% 86.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1587723 5.03% 91.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 771361 2.44% 93.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 532421 1.69% 95.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 258990 0.82% 96.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 207817 0.66% 97.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 189047 0.60% 97.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 757953 2.40% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 9576588 76.69% 76.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1351659 10.82% 87.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 487280 3.90% 91.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 294734 2.36% 93.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 217151 1.74% 95.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 92181 0.74% 96.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 81385 0.65% 96.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 96065 0.77% 97.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 289982 2.32% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31565232 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 20524993 # Number of instructions committed -system.cpu1.commit.committedOps 20524993 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 12487025 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8020551 # Number of instructions committed +system.cpu1.commit.committedOps 8020551 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 5937635 # Number of memory references committed -system.cpu1.commit.loads 3555213 # Number of loads committed -system.cpu1.commit.membars 92415 # Number of memory barriers committed -system.cpu1.commit.branches 3082130 # Number of branches committed -system.cpu1.commit.fp_insts 166998 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 18893824 # Number of committed integer instructions. -system.cpu1.commit.function_calls 318960 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 1204616 5.87% 5.87% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 12808497 62.40% 68.27% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 29745 0.14% 68.42% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13451 0.07% 68.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 3647628 17.77% 86.26% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 2383405 11.61% 97.88% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 435892 2.12% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2563717 # Number of memory references committed +system.cpu1.commit.loads 1543225 # Number of loads committed +system.cpu1.commit.membars 37500 # Number of memory barriers committed +system.cpu1.commit.branches 1142801 # Number of branches committed +system.cpu1.commit.fp_insts 80747 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7435629 # Number of committed integer instructions. +system.cpu1.commit.function_calls 128494 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 382508 4.77% 4.77% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 4766897 59.43% 64.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 14118 0.18% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10465 0.13% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1580725 19.71% 84.24% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1020940 12.73% 96.97% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 243139 3.03% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 20524993 # Class of committed instruction -system.cpu1.commit.bw_lim_events 757953 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 54833276 # The number of ROB reads -system.cpu1.rob.rob_writes 48835744 # The number of ROB writes -system.cpu1.timesIdled 276866 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2180497 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3780899978 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 19323895 # Number of Instructions Simulated -system.cpu1.committedOps 19323895 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.778623 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.778623 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.562233 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.562233 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 27142723 # number of integer regfile reads -system.cpu1.int_regfile_writes 14810250 # number of integer regfile writes -system.cpu1.fp_regfile_reads 88193 # number of floating regfile reads -system.cpu1.fp_regfile_writes 88824 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1272248 # number of misc regfile reads -system.cpu1.misc_regfile_writes 377130 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 561653 # number of replacements -system.cpu1.dcache.tags.tagsinuse 496.197725 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4717582 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 561970 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 8.394722 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 37149185000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.197725 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.969136 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.969136 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 317 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.619141 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24916279 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24916279 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2844065 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2844065 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1751257 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1751257 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 62172 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 62172 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69860 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 69860 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4595322 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4595322 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4595322 # number of overall hits -system.cpu1.dcache.overall_hits::total 4595322 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 792097 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 792097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 552973 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 552973 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14160 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14160 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1345070 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1345070 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1345070 # number of overall misses -system.cpu1.dcache.overall_misses::total 1345070 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10154789500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 10154789500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16820667860 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 16820667860 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 217520000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 217520000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6395000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 6395000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 26975457360 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 26975457360 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 26975457360 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 26975457360 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3636162 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3636162 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2304230 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2304230 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 76332 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 76332 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70646 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 70646 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5940392 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5940392 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5940392 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5940392 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.217839 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.217839 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.239982 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.239982 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.185505 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.185505 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.011126 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.011126 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.226428 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.226428 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.226428 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.226428 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12820.133771 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12820.133771 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30418.606080 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30418.606080 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15361.581921 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15361.581921 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8136.132316 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8136.132316 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20055.058369 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20055.058369 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 765854 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 810 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 36939 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.732938 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 45 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 8020551 # Class of committed instruction +system.cpu1.commit.bw_lim_events 289982 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 21604416 # The number of ROB reads +system.cpu1.rob.rob_writes 19248787 # The number of ROB writes +system.cpu1.timesIdled 107122 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 621832 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3799884834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 7641561 # Number of Instructions Simulated +system.cpu1.committedOps 7641561 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.750771 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.750771 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.571177 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.571177 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 10694286 # number of integer regfile reads +system.cpu1.int_regfile_writes 5846668 # number of integer regfile writes +system.cpu1.fp_regfile_reads 46070 # number of floating regfile reads +system.cpu1.fp_regfile_writes 45105 # number of floating regfile writes +system.cpu1.misc_regfile_reads 889333 # number of misc regfile reads +system.cpu1.misc_regfile_writes 191018 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 88757 # number of replacements +system.cpu1.dcache.tags.tagsinuse 491.801602 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2280391 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 89062 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 25.604534 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1034185237500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.801602 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960550 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.960550 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 10633162 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 10633162 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1420631 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1420631 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 810208 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 810208 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 27933 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 27933 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 26395 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 26395 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2230839 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2230839 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2230839 # number of overall hits +system.cpu1.dcache.overall_hits::total 2230839 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 166361 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 166361 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 175617 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 175617 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4254 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4254 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2523 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2523 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 341978 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 341978 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 341978 # number of overall misses +system.cpu1.dcache.overall_misses::total 341978 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2085855500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2085855500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6615792667 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6615792667 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 40341500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 40341500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21053500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 21053500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8701648167 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8701648167 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8701648167 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8701648167 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1586992 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1586992 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 985825 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 985825 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 32187 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 32187 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 28918 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 28918 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2572817 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2572817 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2572817 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2572817 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.104828 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.104828 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178142 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.178142 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.132165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.132165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087247 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087247 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132920 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.132920 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132920 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.132920 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12538.127927 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12538.127927 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37671.709840 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37671.709840 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9483.192290 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9483.192290 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8344.629409 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8344.629409 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25445.052509 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 25445.052509 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 379425 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 575 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 15060 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.194223 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 47.916667 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 435263 # number of writebacks -system.cpu1.dcache.writebacks::total 435263 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332265 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 332265 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 455576 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 455576 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2707 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2707 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 787841 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 787841 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 787841 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 787841 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 459832 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 459832 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 97397 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 97397 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11453 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 557229 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 557229 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 557229 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 557229 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2425 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4340 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6765 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5761115500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5761115500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2818212839 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2818212839 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 135759000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 135759000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5609000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5609000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8579328339 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8579328339 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8579328339 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8579328339 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 499447000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 499447000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 957710500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 957710500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1457157500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1457157500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.126461 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.126461 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042269 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042269 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.150042 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.150042 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.011126 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.093803 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.093803 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12528.739844 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12528.739844 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28935.314630 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28935.314630 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11853.575482 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11853.575482 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7136.132316 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7136.132316 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205957.525773 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205957.525773 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220670.622120 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220670.622120 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 215396.526238 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 215396.526238 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 56462 # number of writebacks +system.cpu1.dcache.writebacks::total 56462 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 100117 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 100117 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 144305 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 144305 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 244422 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 244422 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 244422 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 244422 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 66244 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 66244 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 31312 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 31312 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3781 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3781 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2522 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2522 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 97556 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 97556 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 97556 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 97556 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2884 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2884 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3042 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3042 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 801271000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 801271000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1099670460 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1099670460 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31948000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31948000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18531500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18531500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1900941460 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1900941460 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1900941460 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1900941460 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29727000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29727000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 636171000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 636171000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 665898000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 665898000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.041742 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041742 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031762 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117470 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117470 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087212 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087212 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.037918 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.037918 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12095.752068 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12095.752068 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35119.777082 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35119.777082 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8449.616504 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8449.616504 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7347.938144 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7347.938144 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188145.569620 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188145.569620 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220586.338419 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220586.338419 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 218901.380671 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 218901.380671 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 499853 # number of replacements -system.cpu1.icache.tags.tagsinuse 504.618896 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 2783346 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 500364 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.562642 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 48744804500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.618896 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985584 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.985584 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 3804626 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 3804626 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 2783351 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2783351 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2783351 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2783351 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2783351 # number of overall hits -system.cpu1.icache.overall_hits::total 2783351 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 520843 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 520843 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 520843 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 520843 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 520843 # number of overall misses -system.cpu1.icache.overall_misses::total 520843 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7005360499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7005360499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7005360499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7005360499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7005360499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7005360499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 3304194 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 3304194 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 3304194 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 3304194 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 3304194 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 3304194 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.157631 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.157631 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.157631 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.157631 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.157631 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.157631 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13450.042525 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13450.042525 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13450.042525 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13450.042525 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 200477 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.242239 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1230816 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 200989 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.123798 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1882066156500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.242239 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918442 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.918442 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1639971 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1639971 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1230816 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1230816 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1230816 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1230816 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1230816 # number of overall hits +system.cpu1.icache.overall_hits::total 1230816 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 208101 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 208101 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 208101 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 208101 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 208101 # number of overall misses +system.cpu1.icache.overall_misses::total 208101 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2838828500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2838828500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2838828500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2838828500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2838828500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2838828500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1438917 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1438917 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1438917 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1438917 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1438917 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1438917 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.144623 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.144623 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.144623 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.144623 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.144623 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.144623 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13641.589901 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13641.589901 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13641.589901 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13641.589901 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 462 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 65 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.461538 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.400000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 20411 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 20411 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 20411 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 20411 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 20411 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 20411 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500432 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 500432 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 500432 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 500432 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 500432 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 500432 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6297993499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6297993499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6297993499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6297993499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6297993499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6297993499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151454 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.151454 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.151454 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.113460 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7047 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7047 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7047 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7047 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7047 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7047 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 201054 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 201054 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 201054 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 201054 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 201054 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 201054 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2552554500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2552554500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2552554500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2552554500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2552554500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2552554500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.139726 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.139726 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.139726 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12695.865290 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1543,45 +1525,45 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 53912 # Transaction distribution -system.iobus.trans_dist::WriteResp 53912 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7371 # Transaction distribution +system.iobus.trans_dist::ReadResp 7371 # Transaction distribution +system.iobus.trans_dist::WriteReq 54460 # Transaction distribution +system.iobus.trans_dist::WriteResp 54460 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11610 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122578 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123662 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 68315 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2729939 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 9868000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 72634 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2734282 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 10965000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1593,7 +1575,7 @@ system.iobus.reqLayer23.occupancy 13505000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1601,52 +1583,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216085248 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216128229 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26764000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27294000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41701 # number of replacements -system.iocache.tags.tagsinuse 0.804902 # Cycle average of tags in use +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.504095 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711319254000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.804902 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.050306 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.050306 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711315950000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.504095 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031506 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031506 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375570 # Number of tag accesses +system.iocache.tags.data_accesses 375570 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 25392883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 25392883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907312365 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907312365 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 25392883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 25392883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 25392883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 25392883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses +system.iocache.demand_misses::total 178 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 178 # number of overall misses +system.iocache.overall_misses::total 178 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22218883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22218883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907321346 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4907321346 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22218883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22218883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22218883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22218883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1655,14 +1637,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 145102.188571 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145102.188571 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.509362 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118100.509362 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145102.188571 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145102.188571 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124825.185393 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124825.185393 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.725501 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118100.725501 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124825.185393 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124825.185393 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1671,24 +1653,24 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41526 # 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number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 16642883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16642883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829712365 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829712365 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 16642883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16642883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 16642883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16642883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 178 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1697,195 +1679,195 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 95102.188571 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.509362 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.509362 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1375.831057 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 575.898345 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.815486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.064295 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.086796 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.020994 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996358 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5965 # 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average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 203974.959547 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200730.913495 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 203265.262380 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 201607.350987 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941541 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.813312 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.903382 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.877805 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.933673 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.905422 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.417765 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.271097 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.404665 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014525 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009113 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013561 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267774 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.013890 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253541 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014525 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.299603 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.093081 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163785 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014525 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.299603 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.093081 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163785 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20846.420745 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20682.634731 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20802.540107 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20803.977273 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.885246 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20795.264624 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78686.950306 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99977.129554 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 79960.958820 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73391.363993 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63027.600114 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81423.900119 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63084.099931 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67661.174174 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98060.972615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68476.578575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67661.174174 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98060.972615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68476.578575 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197982.089552 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175645.569620 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197491.450021 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203275.039904 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208450.589459 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204431.399132 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201092.268011 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 206746.712689 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 201947.987662 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7202 # Transaction distribution -system.membus.trans_dist::ReadResp 296546 # Transaction distribution -system.membus.trans_dist::WriteReq 12360 # Transaction distribution -system.membus.trans_dist::WriteResp 12360 # Transaction distribution -system.membus.trans_dist::Writeback 124264 # Transaction distribution -system.membus.trans_dist::CleanEvict 262871 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5279 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1481 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3452 # Transaction distribution -system.membus.trans_dist::ReadExReq 122900 # Transaction distribution -system.membus.trans_dist::ReadExResp 122774 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289774 # Transaction distribution -system.membus.trans_dist::BadAddressError 430 # Transaction distribution +system.membus.trans_dist::ReadReq 7193 # Transaction distribution +system.membus.trans_dist::ReadResp 296434 # Transaction distribution +system.membus.trans_dist::WriteReq 12908 # Transaction distribution +system.membus.trans_dist::WriteResp 12908 # Transaction distribution +system.membus.trans_dist::Writeback 122837 # Transaction distribution +system.membus.trans_dist::CleanEvict 263082 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9353 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4872 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4824 # Transaction distribution +system.membus.trans_dist::ReadExReq 122000 # Transaction distribution +system.membus.trans_dist::ReadExResp 121659 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289315 # Transaction distribution +system.membus.trans_dist::BadAddressError 74 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1219526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1344359 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68315 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31641920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31710235 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34368859 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3872 # Total snoops (count) -system.membus.snoop_fanout::samples 867863 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1184934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1225284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1350114 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72634 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31472384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31545018 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34203258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 10191 # Total snoops (count) +system.membus.snoop_fanout::samples 873294 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 867863 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 873294 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 867863 # Request fanout histogram -system.membus.reqLayer0.occupancy 35224999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 873294 # Request fanout histogram +system.membus.reqLayer0.occupancy 36159500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1361324691 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1354680439 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 531000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 95500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2190703579 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2187139696 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72073655 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72110882 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 7202 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2275897 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12360 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12360 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 985613 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1602095 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5338 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1555 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6893 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 317171 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 317171 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1117101 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1152039 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 430 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2235424 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12908 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12908 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 946207 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1643079 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9387 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4947 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 14334 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302784 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302784 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1129148 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1099173 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1728214 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2704934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1334787 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1622621 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7390556 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39458944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84672718 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32025024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 62527373 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 218684059 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 464381 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5618153 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.076464 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.265739 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2591178 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3901537 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 531442 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 279415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7303572 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59378176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131958120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 12865536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9234898 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213436730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 458492 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5507130 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.077786 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.267834 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 5188566 92.35% 92.35% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 429587 7.65% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 5078755 92.22% 92.22% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 428375 7.78% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5618153 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3461836914 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5507130 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3369225418 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 240000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 925515973 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1363977262 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1393343588 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1972546779 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 751744303 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 301679801 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 856189885 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 151036436 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2174,32 +2152,32 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4815 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 139340 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 45519 38.89% 38.89% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.11% 39.01% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.65% 40.65% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 40.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 69446 59.33% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 117041 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 44932 48.88% 48.88% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.14% 49.02% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 2.10% 51.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 44917 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 91925 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1870471244000 98.03% 98.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61392000 0.00% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 548913500 0.03% 98.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8511500 0.00% 98.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 36889187000 1.93% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907979248000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.987104 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6502 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 187776 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 66469 40.53% 40.53% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.17% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 149 0.09% 41.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 95308 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 163983 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 65388 49.23% 49.23% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.45% 50.77% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 149 0.11% 50.89% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 65239 49.11% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 132833 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864137851500 97.75% 97.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61127000 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 545976000 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 68164000 0.00% 97.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42142829000 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1906955947500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983737 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.646790 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.785409 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684507 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810041 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed @@ -2231,60 +2209,60 @@ system.cpu0.kern.syscall::144 2 0.89% 99.11% # nu system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 104 0.08% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2293 1.85% 1.93% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.04% 1.97% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed -system.cpu0.kern.callpal::swpipl 110963 89.30% 91.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6296 5.07% 96.35% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.35% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.35% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.36% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.36% # number of callpals executed -system.cpu0.kern.callpal::rti 4002 3.22% 99.58% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.31% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 124254 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5723 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches +system.cpu0.kern.callpal::wripir 249 0.14% 0.14% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3603 2.09% 2.23% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.26% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 157157 91.07% 93.34% # number of callpals executed +system.cpu0.kern.callpal::rdps 6335 3.67% 97.01% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.01% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 97.02% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rti 4619 2.68% 99.70% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.22% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 172559 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7164 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1341 -system.cpu0.kern.mode_good::user 1342 +system.cpu0.kern.mode_good::kernel 1342 +system.cpu0.kern.mode_good::user 1343 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.234318 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.187326 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.379759 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905987592000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1991648000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.315622 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1904989354500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1966585000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2294 # number of times the context was actually changed +system.cpu0.kern.swap_context 3604 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3855 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 98215 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 36112 40.36% 40.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 2.15% 42.52% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 104 0.12% 42.63% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 51325 57.37% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 89466 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 35322 48.67% 48.67% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 2.65% 51.33% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 104 0.14% 51.47% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 35218 48.53% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 72569 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870768654000 98.07% 98.07% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 540231000 0.03% 98.10% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 48911000 0.00% 98.10% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 36277143500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907634939500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978124 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2444 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 51472 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 15731 36.02% 36.02% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 4.41% 40.43% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 249 0.57% 41.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 25763 59.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 43668 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 15435 47.07% 47.07% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.87% 52.93% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 249 0.76% 53.69% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15186 46.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 32795 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874760769500 98.33% 98.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 538410500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 114320500 0.01% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31218212000 1.64% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1906631712500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981184 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.686176 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.811135 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.589450 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.751008 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed @@ -2300,35 +2278,35 @@ system.cpu1.kern.syscall::74 10 9.90% 97.03% # nu system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1949 2.12% 2.14% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 2.14% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.15% # number of callpals executed -system.cpu1.kern.callpal::swpipl 84230 91.49% 93.64% # number of callpals executed -system.cpu1.kern.callpal::rdps 2466 2.68% 96.32% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.32% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 96.32% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.33% # number of callpals executed -system.cpu1.kern.callpal::rti 3206 3.48% 99.81% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.14% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 149 0.33% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu1.kern.callpal::swpctx 911 2.02% 2.35% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.36% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 2.38% # number of callpals executed +system.cpu1.kern.callpal::swpipl 38628 85.51% 87.88% # number of callpals executed +system.cpu1.kern.callpal::rdps 2426 5.37% 93.25% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.25% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.26% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.27% # number of callpals executed +system.cpu1.kern.callpal::rti 2865 6.34% 99.61% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.29% 99.90% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 92064 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2331 # number of protection mode switches +system.cpu1.kern.callpal::total 45176 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1151 # number of protection mode switches system.cpu1.kern.mode_switch::user 395 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 461 +system.cpu1.kern.mode_switch::idle 2341 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 568 system.cpu1.kern.mode_good::user 395 -system.cpu1.kern.mode_good::idle 66 -system.cpu1.kern.mode_switch_good::kernel 0.197769 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 173 +system.cpu1.kern.mode_switch_good::kernel 0.493484 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.192887 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 42837305000 2.25% 2.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 697376000 0.04% 2.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1863790118000 97.72% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1950 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.073900 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.292256 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3648998000 0.19% 0.19% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 689386500 0.04% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1901995153000 99.77% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 912 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 3eacf4507..2be1ffca4 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -166,7 +166,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -513,7 +513,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -562,7 +562,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -696,7 +696,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 156f5647f..275b5ad07 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.861005 # Number of seconds simulated -sim_ticks 1861005347500 # Number of ticks simulated -final_tick 1861005347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860990 # Number of seconds simulated +sim_ticks 1860990273000 # Number of ticks simulated +final_tick 1860990273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149955 # Simulator instruction rate (inst/s) -host_op_rate 149955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5267476367 # Simulator tick rate (ticks/s) -host_mem_usage 376564 # Number of bytes of host memory used -host_seconds 353.30 # Real time elapsed on the host -sim_insts 52979113 # Number of instructions simulated -sim_ops 52979113 # Number of ops (including micro ops) simulated +host_inst_rate 102674 # Simulator instruction rate (inst/s) +host_op_rate 102674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3606509618 # Simulator tick rate (ticks/s) +host_mem_usage 370916 # Number of bytes of host memory used +host_seconds 516.01 # Real time elapsed on the host +sim_insts 52980740 # Number of instructions simulated +sim_ops 52980740 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 965824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 964096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25846272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 965824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 965824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7524416 # Number of bytes written to this memory -system.physmem.bytes_written::total 7524416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15091 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25845056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964096 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7523456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7523456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403848 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117569 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13368843 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403829 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13369226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13888338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518980 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518980 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4043200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4043200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4043200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13368843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13887797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4042716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4042716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4042716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13369226 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17931538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403848 # Number of read requests accepted -system.physmem.writeReqs 117569 # Number of write requests accepted -system.physmem.readBursts 403848 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117569 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue -system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25846272 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7524416 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17930514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403829 # Number of read requests accepted +system.physmem.writeReqs 117554 # Number of write requests accepted +system.physmem.readBursts 403829 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117554 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25837696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 7522048 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25845056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7523456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41759 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25651 # Per bank write bursts -system.physmem.perBankRdBursts::1 25422 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25640 # Per bank write bursts +system.physmem.perBankRdBursts::1 25420 # Per bank write bursts system.physmem.perBankRdBursts::2 25567 # Per bank write bursts -system.physmem.perBankRdBursts::3 25497 # Per bank write bursts -system.physmem.perBankRdBursts::4 25384 # Per bank write bursts -system.physmem.perBankRdBursts::5 24734 # Per bank write bursts -system.physmem.perBankRdBursts::6 24943 # Per bank write bursts -system.physmem.perBankRdBursts::7 25079 # Per bank write bursts -system.physmem.perBankRdBursts::8 24928 # Per bank write bursts -system.physmem.perBankRdBursts::9 25027 # Per bank write bursts -system.physmem.perBankRdBursts::10 25572 # Per bank write bursts -system.physmem.perBankRdBursts::11 24872 # Per bank write bursts -system.physmem.perBankRdBursts::12 24489 # Per bank write bursts +system.physmem.perBankRdBursts::3 25490 # Per bank write bursts +system.physmem.perBankRdBursts::4 25392 # Per bank write bursts +system.physmem.perBankRdBursts::5 24736 # Per bank write bursts +system.physmem.perBankRdBursts::6 24946 # Per bank write bursts +system.physmem.perBankRdBursts::7 25069 # Per bank write bursts +system.physmem.perBankRdBursts::8 24934 # Per bank write bursts +system.physmem.perBankRdBursts::9 25024 # Per bank write bursts +system.physmem.perBankRdBursts::10 25571 # Per bank write bursts +system.physmem.perBankRdBursts::11 24874 # Per bank write bursts +system.physmem.perBankRdBursts::12 24488 # Per bank write bursts system.physmem.perBankRdBursts::13 25240 # Per bank write bursts system.physmem.perBankRdBursts::14 25741 # Per bank write bursts -system.physmem.perBankRdBursts::15 25596 # Per bank write bursts -system.physmem.perBankWrBursts::0 7944 # Per bank write bursts -system.physmem.perBankWrBursts::1 7514 # Per bank write bursts -system.physmem.perBankWrBursts::2 7965 # Per bank write bursts -system.physmem.perBankWrBursts::3 7518 # Per bank write bursts -system.physmem.perBankWrBursts::4 7330 # Per bank write bursts -system.physmem.perBankWrBursts::5 6666 # Per bank write bursts -system.physmem.perBankWrBursts::6 6776 # Per bank write bursts -system.physmem.perBankWrBursts::7 6716 # Per bank write bursts -system.physmem.perBankWrBursts::8 7141 # Per bank write bursts -system.physmem.perBankWrBursts::9 6711 # Per bank write bursts -system.physmem.perBankWrBursts::10 7422 # Per bank write bursts -system.physmem.perBankWrBursts::11 6968 # Per bank write bursts -system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankRdBursts::15 25582 # Per bank write bursts +system.physmem.perBankWrBursts::0 7942 # Per bank write bursts +system.physmem.perBankWrBursts::1 7515 # Per bank write bursts +system.physmem.perBankWrBursts::2 7958 # Per bank write bursts +system.physmem.perBankWrBursts::3 7515 # Per bank write bursts +system.physmem.perBankWrBursts::4 7335 # Per bank write bursts +system.physmem.perBankWrBursts::5 6671 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 6705 # Per bank write bursts +system.physmem.perBankWrBursts::8 7147 # Per bank write bursts +system.physmem.perBankWrBursts::9 6708 # Per bank write bursts +system.physmem.perBankWrBursts::10 7414 # Per bank write bursts +system.physmem.perBankWrBursts::11 6974 # Per bank write bursts +system.physmem.perBankWrBursts::12 7148 # Per bank write bursts system.physmem.perBankWrBursts::13 7857 # Per bank write bursts -system.physmem.perBankWrBursts::14 8054 # Per bank write bursts -system.physmem.perBankWrBursts::15 7825 # Per bank write bursts +system.physmem.perBankWrBursts::14 8057 # Per bank write bursts +system.physmem.perBankWrBursts::15 7814 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 23 # Number of times write queue was full causing retry -system.physmem.totGap 1860999975500 # Total gap between requests +system.physmem.numWrRetry 22 # Number of times write queue was full causing retry +system.physmem.totGap 1860985018500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403848 # Read request sizes (log2) +system.physmem.readPktSize::6 403829 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117569 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28364 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117554 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28406 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -148,116 +148,128 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61779 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 540.028683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 331.823835 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.833229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13638 22.08% 22.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10412 16.85% 38.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4989 8.08% 47.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3229 5.23% 52.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2263 3.66% 55.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1516 2.45% 58.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1526 2.47% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1289 2.09% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22917 37.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61779 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5213 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.447919 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2924.392219 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5210 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61694 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 540.722923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.893410 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.338201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13637 22.10% 22.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10472 16.97% 39.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4852 7.86% 46.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3164 5.13% 52.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2278 3.69% 55.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1550 2.51% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1469 2.38% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1300 2.11% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22972 37.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61694 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5210 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.486564 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2926.418549 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5207 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5213 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.549779 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.928650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.456391 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4618 88.59% 88.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 208 3.99% 92.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 74 1.42% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 17 0.33% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 8 0.15% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 5 0.10% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 10 0.19% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 10 0.19% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 7 0.13% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 32 0.61% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 168 3.22% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 10 0.19% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.10% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.04% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.10% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.08% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 12 0.23% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5213 # Writes before turning the bus around for reads -system.physmem.totQLat 3805918000 # Total ticks spent queuing -system.physmem.totMemAccLat 11376080500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9426.61 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5210 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5210 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.558925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.942347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.343325 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4470 85.80% 85.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 144 2.76% 88.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 197 3.78% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 15 0.29% 92.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.42% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 47 0.90% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 16 0.31% 94.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.02% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 3 0.06% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.12% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.10% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 4 0.08% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.06% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.19% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 6 0.12% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 10 0.19% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 18 0.35% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 17 0.33% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 156 2.99% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 8 0.15% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.13% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.06% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.06% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.06% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 3 0.06% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.04% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 4 0.08% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 11 0.21% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5210 # Writes before turning the bus around for reads +system.physmem.totQLat 3803541750 # Total ticks spent queuing +system.physmem.totMemAccLat 11373179250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9421.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28176.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28171.38 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s @@ -266,72 +278,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.30 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 364169 # Number of row buffer hits during reads -system.physmem.writeRowHits 95345 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads +system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing +system.physmem.readRowHits 364213 # Number of row buffer hits during reads +system.physmem.writeRowHits 95338 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes -system.physmem.avgGap 3569120.25 # Average gap between requests -system.physmem.pageHitRate 88.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 232515360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126868500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577760600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378619920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56250477360 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1067257263000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1247374938900 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.271455 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1775312455750 # Time in different power states -system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states +system.physmem.avgGap 3569324.31 # Average gap between requests +system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 231343560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126229125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577628000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378516240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56189479095 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067301426750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1247355039810 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.266370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1775383293000 # Time in different power states +system.physmem_0.memoryStateTime::REF 62142340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23544343000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23458453250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 234533880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 127969875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1571380200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383117040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 55982569095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1067492278500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1247343282750 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.254439 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1775708219250 # Time in different power states -system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states +system.physmem_1.actEnergy 235063080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 128258625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571294400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383091120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 55921872645 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067536177500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1247326174410 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.250855 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1775778508500 # Time in different power states +system.physmem_1.memoryStateTime::REF 62142340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23148593250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23063881500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17721018 # Number of BP lookups -system.cpu.branchPred.condPredicted 15408782 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 378784 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12470436 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5897235 # Number of BTB hits +system.cpu.branchPred.lookups 17952495 # Number of BP lookups +system.cpu.branchPred.condPredicted 15650737 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 369298 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11540660 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5852648 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 47.289726 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 918220 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21032 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.713287 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 911814 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21176 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10294388 # DTB read hits -system.cpu.dtb.read_misses 42024 # DTB read misses -system.cpu.dtb.read_acv 506 # DTB read access violations -system.cpu.dtb.read_accesses 968687 # DTB read accesses -system.cpu.dtb.write_hits 6648521 # DTB write hits -system.cpu.dtb.write_misses 9456 # DTB write misses -system.cpu.dtb.write_acv 408 # DTB write access violations -system.cpu.dtb.write_accesses 343243 # DTB write accesses -system.cpu.dtb.data_hits 16942909 # DTB hits -system.cpu.dtb.data_misses 51480 # DTB misses -system.cpu.dtb.data_acv 914 # DTB access violations -system.cpu.dtb.data_accesses 1311930 # DTB accesses -system.cpu.itb.fetch_hits 1769476 # ITB hits -system.cpu.itb.fetch_misses 36155 # ITB misses -system.cpu.itb.fetch_acv 662 # ITB acv -system.cpu.itb.fetch_accesses 1805631 # ITB accesses +system.cpu.dtb.read_hits 10266725 # DTB read hits +system.cpu.dtb.read_misses 41420 # DTB read misses +system.cpu.dtb.read_acv 529 # DTB read access violations +system.cpu.dtb.read_accesses 965767 # DTB read accesses +system.cpu.dtb.write_hits 6642195 # DTB write hits +system.cpu.dtb.write_misses 9809 # DTB write misses +system.cpu.dtb.write_acv 405 # DTB write access violations +system.cpu.dtb.write_accesses 342270 # DTB write accesses +system.cpu.dtb.data_hits 16908920 # DTB hits +system.cpu.dtb.data_misses 51229 # DTB misses +system.cpu.dtb.data_acv 934 # DTB access violations +system.cpu.dtb.data_accesses 1308037 # DTB accesses +system.cpu.itb.fetch_hits 1768997 # ITB hits +system.cpu.itb.fetch_misses 27603 # ITB misses +system.cpu.itb.fetch_acv 655 # ITB acv +system.cpu.itb.fetch_accesses 1796600 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,691 +356,692 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122272854 # number of cpu cycles simulated +system.cpu.numCycles 122250725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29542399 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 77951342 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17721018 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6815455 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 84318662 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1251172 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1032 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27002 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1751503 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 450615 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9037094 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 274713 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116717019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.667866 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.979948 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29590872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78035312 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17952495 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6764462 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 84736015 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1230846 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3604 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1246103 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 463506 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 270 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8988072 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 271207 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 116683770 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.668776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.983888 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102159840 87.53% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 935001 0.80% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1975635 1.69% 90.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 907890 0.78% 90.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2798283 2.40% 93.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 634657 0.54% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 731012 0.63% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1008696 0.86% 95.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5566005 4.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102162821 87.56% 87.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 926771 0.79% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1955000 1.68% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 905545 0.78% 90.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2771139 2.37% 93.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 614884 0.53% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 724459 0.62% 94.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009032 0.86% 95.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5614119 4.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116717019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144930 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.637520 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24051579 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80690981 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9487535 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1903773 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 583150 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586842 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42848 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68182155 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 134674 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 583150 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24974215 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50913599 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20868972 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10381558 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8995523 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65764072 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 201455 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2078667 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 157006 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4811107 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43858088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79749030 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79568293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168286 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179356 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5678724 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1691117 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 241700 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13523739 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10414999 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6951257 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1489090 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1076371 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58557437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2137330 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57550552 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 58383 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7715649 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3482179 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1476201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116717019 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.493078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.231262 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 116683770 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.146850 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.638322 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24065548 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80700938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9436968 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1906955 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 573360 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 582340 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42404 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68029803 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 132508 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 573360 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24987085 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50897393 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20868454 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10337136 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9020340 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65614260 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 203152 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2087104 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 150571 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4833262 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43733220 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79561709 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79380946 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168313 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180223 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5552989 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1689330 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239361 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13544094 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10376074 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6949198 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1492318 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1087072 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58452380 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2137932 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57496742 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7609567 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3401604 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1476871 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116683770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.492757 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.231576 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 93076852 79.75% 79.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10193735 8.73% 88.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4312708 3.70% 92.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3021195 2.59% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3081764 2.64% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1495449 1.28% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1007889 0.86% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 403235 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124192 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93080109 79.77% 79.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10182698 8.73% 88.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4288903 3.68% 92.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3018996 2.59% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3082938 2.64% 97.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1488362 1.28% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1011835 0.87% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 404754 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125175 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116717019 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116683770 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 208462 18.43% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547266 48.38% 66.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375475 33.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 209669 18.63% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 542046 48.17% 66.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373622 33.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39056911 67.87% 67.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61891 0.11% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38552 0.07% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10704988 18.60% 86.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6728388 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948900 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39037181 67.89% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61834 0.11% 68.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38554 0.07% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10676723 18.57% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722717 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948811 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57550552 # Type of FU issued -system.cpu.iq.rate 0.470673 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1131203 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019656 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 232294841 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68093775 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55871823 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712867 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336544 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329026 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58291729 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382740 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 634925 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57496742 # Type of FU issued +system.cpu.iq.rate 0.470318 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1125337 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 232146820 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67882277 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55834928 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712827 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336508 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328971 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58232105 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382688 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 634703 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1322411 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3516 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20331 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 573217 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1283936 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3373 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19308 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 571381 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18302 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 483316 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18194 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 477327 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 583150 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 47678109 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 871068 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64398227 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 142430 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10414999 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6951257 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1888726 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 44438 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 623782 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20331 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 186400 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411798 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 598198 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56961347 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10364061 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 589204 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 573360 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 47668673 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 853294 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64278853 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140556 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10376074 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6949198 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1890343 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43583 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 606693 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19308 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 178271 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409117 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 587388 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56911436 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10335818 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 585305 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3703460 # number of nop insts executed -system.cpu.iew.exec_refs 17037134 # number of memory reference insts executed -system.cpu.iew.exec_branches 8968929 # Number of branches executed -system.cpu.iew.exec_stores 6673073 # Number of stores executed -system.cpu.iew.exec_rate 0.465854 # Inst execution rate -system.cpu.iew.wb_sent 56337909 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56200849 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28756133 # num instructions producing a value -system.cpu.iew.wb_consumers 39912635 # num instructions consuming a value +system.cpu.iew.exec_nop 3688541 # number of nop insts executed +system.cpu.iew.exec_refs 17002933 # number of memory reference insts executed +system.cpu.iew.exec_branches 8971597 # Number of branches executed +system.cpu.iew.exec_stores 6667115 # Number of stores executed +system.cpu.iew.exec_rate 0.465530 # Inst execution rate +system.cpu.iew.wb_sent 56299831 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56163899 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28741573 # num instructions producing a value +system.cpu.iew.wb_consumers 39917507 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.459635 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.720477 # average fanout of values written-back +system.cpu.iew.wb_rate 0.459416 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.720024 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8112704 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661129 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 547326 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 115294268 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487187 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.430320 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7990103 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661061 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 538190 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 115283305 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.430050 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95501177 82.83% 82.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7867272 6.82% 89.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4280982 3.71% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2233083 1.94% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1745854 1.51% 96.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611445 0.53% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 482985 0.42% 97.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 468960 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2102510 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95489644 82.83% 82.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7861367 6.82% 89.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4279666 3.71% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2238986 1.94% 95.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1753667 1.52% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 610357 0.53% 97.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475106 0.41% 97.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 479497 0.42% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2095015 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 115294268 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56169836 # Number of instructions committed -system.cpu.commit.committedOps 56169836 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 115283305 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56171345 # Number of instructions committed +system.cpu.commit.committedOps 56171345 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470628 # Number of memory references committed -system.cpu.commit.loads 9092588 # Number of loads committed -system.cpu.commit.membars 226333 # Number of memory barriers committed -system.cpu.commit.branches 8440353 # Number of branches committed +system.cpu.commit.refs 15469955 # Number of memory references committed +system.cpu.commit.loads 9092138 # Number of loads committed +system.cpu.commit.membars 226307 # Number of memory barriers committed +system.cpu.commit.branches 8441356 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019375 # Number of committed integer instructions. -system.cpu.commit.function_calls 740552 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197996 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36217639 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60667 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52021098 # Number of committed integer instructions. +system.cpu.commit.function_calls 740502 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197878 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36220066 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60657 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9318921 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6383992 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 948900 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9318445 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383767 11.36% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948811 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56169836 # Class of committed instruction -system.cpu.commit.bw_lim_events 2102510 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 177224791 # The number of ROB reads -system.cpu.rob.rob_writes 129983616 # The number of ROB writes -system.cpu.timesIdled 573073 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5555835 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599737842 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979113 # Number of Instructions Simulated -system.cpu.committedOps 52979113 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.307945 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.307945 # CPI: Total CPI of All Threads -system.cpu.ipc 0.433286 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433286 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74622251 # number of integer regfile reads -system.cpu.int_regfile_writes 40551917 # number of integer regfile writes -system.cpu.fp_regfile_reads 167069 # number of floating regfile reads -system.cpu.fp_regfile_writes 167545 # number of floating regfile writes -system.cpu.misc_regfile_reads 2028916 # number of misc regfile reads -system.cpu.misc_regfile_writes 939321 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1404299 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994455 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11844191 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1404811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.431163 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994455 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56171345 # Class of committed instruction +system.cpu.commit.bw_lim_events 2095015 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 177100105 # The number of ROB reads +system.cpu.rob.rob_writes 129718981 # The number of ROB writes +system.cpu.timesIdled 575678 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5566955 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599729822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52980740 # Number of Instructions Simulated +system.cpu.committedOps 52980740 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.307456 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.307456 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433378 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433378 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74560962 # number of integer regfile reads +system.cpu.int_regfile_writes 40515010 # number of integer regfile writes +system.cpu.fp_regfile_reads 167029 # number of floating regfile reads +system.cpu.fp_regfile_writes 167528 # number of floating regfile writes +system.cpu.misc_regfile_reads 2030483 # number of misc regfile reads +system.cpu.misc_regfile_writes 939256 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1402429 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994497 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11825966 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1402941 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.429411 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26175500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994497 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63926076 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63926076 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7252822 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7252822 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4188714 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4188714 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186644 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186644 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215706 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215706 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11441536 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11441536 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11441536 # number of overall hits -system.cpu.dcache.overall_hits::total 11441536 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1804157 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1804157 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1958890 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1958890 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23354 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23354 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3763047 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3763047 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3763047 # number of overall misses -system.cpu.dcache.overall_misses::total 3763047 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41750233000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41750233000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 80527676066 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 80527676066 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 377889000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 377889000 # 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number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30575992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30575992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12635842717 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12635842717 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226273500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226273500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 469500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 469500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43211834717 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 43211834717 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43211834717 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 43211834717 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1451037500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1451037500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035928998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035928998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486966498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486966498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047305 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047305 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086682 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086682 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091208 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091208 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27898.770213 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27898.770213 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43450.061438 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43450.061438 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12430.560897 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12430.560897 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16189.655172 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16189.655172 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209384.920635 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209384.920635 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.231739 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.231739 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210986.053004 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210986.053004 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30550296500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30550296500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12634151241 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12634151241 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226327000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226327000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 457000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 457000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43184447741 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43184447741 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43184447741 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43184447741 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450758000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450758000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035709998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035709998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486467998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486467998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047291 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047291 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086658 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086658 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091219 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091219 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27918.094771 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27918.094771 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43458.441655 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43458.441655 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12471.181397 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12471.181397 # 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average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212141.517090 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210968.655331 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210968.655331 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1035158 # number of replacements -system.cpu.icache.tags.tagsinuse 509.238634 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7947846 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1035666 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.674140 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 28148361500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.238634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994607 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994607 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1038549 # number of replacements +system.cpu.icache.tags.tagsinuse 509.170339 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7895321 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1039057 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.598545 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28146856500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.170339 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10073023 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10073023 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7947847 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7947847 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7947847 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7947847 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7947847 # number of overall hits -system.cpu.icache.overall_hits::total 7947847 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1089244 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1089244 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1089244 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1089244 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1089244 # number of overall misses -system.cpu.icache.overall_misses::total 1089244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15223822993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15223822993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15223822993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15223822993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15223822993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15223822993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9037091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9037091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9037091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9037091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9037091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9037091 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120530 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120530 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120530 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120530 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120530 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.503881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13976.503881 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.503881 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13976.503881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.503881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13976.503881 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5247 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10027494 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10027494 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7895322 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7895322 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7895322 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7895322 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7895322 # number of overall hits +system.cpu.icache.overall_hits::total 7895322 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1092746 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1092746 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1092746 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1092746 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1092746 # number of overall misses +system.cpu.icache.overall_misses::total 1092746 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15273300993 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15273300993 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15273300993 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15273300993 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15273300993 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15273300993 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8988068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8988068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8988068 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8988068 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8988068 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8988068 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121577 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121577 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121577 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.121577 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.121577 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.121577 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.990987 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13976.990987 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13976.990987 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13976.990987 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6859 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 220 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 27.328125 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.177273 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53312 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53312 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53312 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53312 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53312 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53312 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035932 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1035932 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1035932 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1035932 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1035932 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1035932 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13551519997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13551519997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13551519997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13551519997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13551519997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13551519997 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114631 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114631 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114631 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13081.476387 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13081.476387 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13081.476387 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13081.476387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13081.476387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13081.476387 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53320 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53320 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53320 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53320 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53320 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53320 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039426 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1039426 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1039426 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1039426 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1039426 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1039426 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13594657497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13594657497 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364412500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364412500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925547500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925547500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289960000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289960000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2195000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2195000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 124000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 124000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9147908500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9147908500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1108373500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1108373500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17263967500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17263967500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1108373500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26411876000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27520249500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1108373500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26411876000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27520249500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364133000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364133000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925339500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925339500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289472500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289472500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.646341 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.646341 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.206897 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.206897 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014571 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248213 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248213 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165671 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165671 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23594.339623 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23594.339623 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20750 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79278.696764 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79278.696764 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73289.027299 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73289.027299 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63057.724049 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63057.724049 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196884.920635 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196884.920635 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200640.564760 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200640.564760 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199065.771162 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199065.771162 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.771654 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.771654 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383114 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383114 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014498 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248597 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248597 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165595 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165595 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22397.959184 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22397.959184 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79200.613837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79200.613837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73572.751411 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73572.751411 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63044.224891 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63044.224891 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196844.588745 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196844.588745 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.797832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.797832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199048.317802 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199048.317802 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2146205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 960354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1857372 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035932 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1103445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2147969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 959201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1860011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101712 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 82 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106451 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4246137 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7352588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66287680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143898860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210186540 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422109 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5318690 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.079299 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.270205 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3116681 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240614 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7357295 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66503296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143706404 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210209700 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422216 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5321857 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.079248 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270126 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4896924 92.07% 92.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 421766 7.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4900109 92.08% 92.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 421748 7.92% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5318690 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3296022500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5321857 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3296477500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1555343104 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1560615042 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2119169250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2116394230 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1187,9 +1200,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51149 # Transaction distribution -system.iobus.trans_dist::WriteResp 51149 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51148 # Transaction distribution +system.iobus.trans_dist::WriteResp 51148 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5048 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1201,11 +1214,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20192 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1217,11 +1230,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44132 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705740 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4659000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1243,23 +1256,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216065006 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216075504 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23456000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.259177 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.259061 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711311931000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.259177 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711310965000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.259061 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078691 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078691 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1275,8 +1288,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4909206123 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4909206123 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908771621 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4908771621 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles @@ -1299,17 +1312,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118146.084978 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118146.084978 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118135.628153 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118135.628153 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1325,8 +1338,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831606123 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2831606123 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831171621 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2831171621 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles @@ -1341,60 +1354,60 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68146.084978 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68146.084978 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68135.628153 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68135.628153 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295956 # Transaction distribution -system.membus.trans_dist::WriteReq 9597 # Transaction distribution -system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117569 # Transaction distribution -system.membus.trans_dist::CleanEvict 261797 # Transaction distribution -system.membus.trans_dist::UpgradeReq 204 # Transaction distribution +system.membus.trans_dist::ReadResp 295925 # Transaction distribution +system.membus.trans_dist::WriteReq 9596 # Transaction distribution +system.membus.trans_dist::WriteResp 9596 # Transaction distribution +system.membus.trans_dist::Writeback 117554 # Transaction distribution +system.membus.trans_dist::CleanEvict 261799 # Transaction distribution +system.membus.trans_dist::UpgradeReq 335 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 210 # Transaction distribution -system.membus.trans_dist::ReadExReq 115254 # Transaction distribution -system.membus.trans_dist::ReadExResp 115254 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289111 # Transaction distribution -system.membus.trans_dist::BadAddressError 85 # Transaction distribution +system.membus.trans_dist::UpgradeResp 341 # Transaction distribution +system.membus.trans_dist::ReadExReq 115266 # Transaction distribution +system.membus.trans_dist::ReadExResp 115266 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289077 # Transaction distribution +system.membus.trans_dist::BadAddressError 82 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179422 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33052 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146409 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179625 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1304239 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30712960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1304442 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754916 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33414828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33412644 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 842203 # Request fanout histogram +system.membus.snoop_fanout::samples 842297 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842203 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842297 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842203 # Request fanout histogram -system.membus.reqLayer0.occupancy 29160500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842297 # Request fanout histogram +system.membus.reqLayer0.occupancy 28891000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313577675 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313747676 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 109500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 109000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139558790 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139659662 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1430,28 +1443,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210978 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74652 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210955 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74645 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105547 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182209 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73285 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105533 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182187 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73278 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73285 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148580 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817522630000 97.66% 97.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 62579500 0.00% 97.67% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 533633500 0.03% 97.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42885651500 2.30% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1861004494500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73278 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148565 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817526707500 97.66% 97.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62603000 0.00% 97.67% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 536431500 0.03% 97.70% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42863705000 2.30% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860989447000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981687 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694335 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815437 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694361 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815453 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1490,29 +1503,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175094 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175074 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191938 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.callpal::total 191916 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325983 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393886 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29174464500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2684090500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1829145931500 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29189899500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2667621500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829131918000 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index d49d26c09..df18f1206 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -98,7 +98,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -138,7 +138,7 @@ eventq_index=0 size=64 [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -750,7 +750,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 @@ -785,7 +785,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr index ae9247519..1b889d7a1 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr @@ -7,10 +7,6 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8155, Bank: 7 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -19,8 +15,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11185, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -54,6 +48,6 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 11369, Bank: 3 +Command: 0, Timestamp: 11394, Bank: 3 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index 29e1e9099..930df34c1 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:35:45 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 20:54:31 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 8b67c053c..296ab434c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841548 # Number of seconds simulated -sim_ticks 1841548033500 # Number of ticks simulated -final_tick 1841548033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841535 # Number of seconds simulated +sim_ticks 1841535479500 # Number of ticks simulated +final_tick 1841535479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 218310 # Simulator instruction rate (inst/s) -host_op_rate 218310 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5702515722 # Simulator tick rate (ticks/s) -host_mem_usage 375536 # Number of bytes of host memory used -host_seconds 322.94 # Real time elapsed on the host -sim_insts 70500110 # Number of instructions simulated -sim_ops 70500110 # Number of ops (including micro ops) simulated +host_inst_rate 156573 # Simulator instruction rate (inst/s) +host_op_rate 156573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3970842510 # Simulator tick rate (ticks/s) +host_mem_usage 369896 # Number of bytes of host memory used +host_seconds 463.76 # Real time elapsed on the host +sim_insts 72613172 # Number of instructions simulated +sim_ops 72613172 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 465600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20057408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2156416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 307456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2656704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 466112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20058112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2156288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 305728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2656832 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25791680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 465600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 307456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 920192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7484672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7484672 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2299 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41511 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25791040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 466112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 305728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918848 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7482432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7482432 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33692 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41513 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402995 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116948 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116948 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 252831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10891602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1170980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 166955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1442647 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402985 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116913 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116913 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 253111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10892058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1170919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 166018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1442726 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14005434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 252831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79898 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 166955 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4064337 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4064337 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4064337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 252831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10891602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1170980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 166955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1442647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14005182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 253111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 166018 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4063148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4063148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4063148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 253111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10892058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1170919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 166018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1442726 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18069771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 82323 # Number of read requests accepted -system.physmem.writeReqs 47461 # Number of write requests accepted -system.physmem.readBursts 82323 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 47461 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5267264 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue -system.physmem.bytesWritten 3035584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5268672 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3037504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 18068331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 82294 # Number of read requests accepted +system.physmem.writeReqs 47398 # Number of write requests accepted +system.physmem.readBursts 82294 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 47398 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5265472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue +system.physmem.bytesWritten 3032512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5266816 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3033472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 17348 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4998 # Per bank write bursts -system.physmem.perBankRdBursts::1 5047 # Per bank write bursts -system.physmem.perBankRdBursts::2 4951 # Per bank write bursts -system.physmem.perBankRdBursts::3 4902 # Per bank write bursts -system.physmem.perBankRdBursts::4 5135 # Per bank write bursts -system.physmem.perBankRdBursts::5 5137 # Per bank write bursts -system.physmem.perBankRdBursts::6 5321 # Per bank write bursts -system.physmem.perBankRdBursts::7 5238 # Per bank write bursts -system.physmem.perBankRdBursts::8 5355 # Per bank write bursts -system.physmem.perBankRdBursts::9 4827 # Per bank write bursts -system.physmem.perBankRdBursts::10 5539 # Per bank write bursts -system.physmem.perBankRdBursts::11 5124 # Per bank write bursts -system.physmem.perBankRdBursts::12 4881 # Per bank write bursts -system.physmem.perBankRdBursts::13 5044 # Per bank write bursts -system.physmem.perBankRdBursts::14 5631 # Per bank write bursts -system.physmem.perBankRdBursts::15 5171 # Per bank write bursts -system.physmem.perBankWrBursts::0 2712 # Per bank write bursts -system.physmem.perBankWrBursts::1 2869 # Per bank write bursts -system.physmem.perBankWrBursts::2 2967 # Per bank write bursts -system.physmem.perBankWrBursts::3 2927 # Per bank write bursts -system.physmem.perBankWrBursts::4 2992 # Per bank write bursts -system.physmem.perBankWrBursts::5 2769 # Per bank write bursts -system.physmem.perBankWrBursts::6 3293 # Per bank write bursts -system.physmem.perBankWrBursts::7 2918 # Per bank write bursts -system.physmem.perBankWrBursts::8 3398 # Per bank write bursts -system.physmem.perBankWrBursts::9 2634 # Per bank write bursts -system.physmem.perBankWrBursts::10 3325 # Per bank write bursts -system.physmem.perBankWrBursts::11 2913 # Per bank write bursts -system.physmem.perBankWrBursts::12 2642 # Per bank write bursts -system.physmem.perBankWrBursts::13 2800 # Per bank write bursts -system.physmem.perBankWrBursts::14 3388 # Per bank write bursts -system.physmem.perBankWrBursts::15 2884 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 17325 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5126 # Per bank write bursts +system.physmem.perBankRdBursts::1 5048 # Per bank write bursts +system.physmem.perBankRdBursts::2 4814 # Per bank write bursts +system.physmem.perBankRdBursts::3 4971 # Per bank write bursts +system.physmem.perBankRdBursts::4 5248 # Per bank write bursts +system.physmem.perBankRdBursts::5 5169 # Per bank write bursts +system.physmem.perBankRdBursts::6 5184 # Per bank write bursts +system.physmem.perBankRdBursts::7 5149 # Per bank write bursts +system.physmem.perBankRdBursts::8 5417 # Per bank write bursts +system.physmem.perBankRdBursts::9 4756 # Per bank write bursts +system.physmem.perBankRdBursts::10 5535 # Per bank write bursts +system.physmem.perBankRdBursts::11 5117 # Per bank write bursts +system.physmem.perBankRdBursts::12 4885 # Per bank write bursts +system.physmem.perBankRdBursts::13 5047 # Per bank write bursts +system.physmem.perBankRdBursts::14 5632 # Per bank write bursts +system.physmem.perBankRdBursts::15 5175 # Per bank write bursts +system.physmem.perBankWrBursts::0 2819 # Per bank write bursts +system.physmem.perBankWrBursts::1 2870 # Per bank write bursts +system.physmem.perBankWrBursts::2 2836 # Per bank write bursts +system.physmem.perBankWrBursts::3 2977 # Per bank write bursts +system.physmem.perBankWrBursts::4 3104 # Per bank write bursts +system.physmem.perBankWrBursts::5 2797 # Per bank write bursts +system.physmem.perBankWrBursts::6 3160 # Per bank write bursts +system.physmem.perBankWrBursts::7 2831 # Per bank write bursts +system.physmem.perBankWrBursts::8 3459 # Per bank write bursts +system.physmem.perBankWrBursts::9 2567 # Per bank write bursts +system.physmem.perBankWrBursts::10 3319 # Per bank write bursts +system.physmem.perBankWrBursts::11 2907 # Per bank write bursts +system.physmem.perBankWrBursts::12 2644 # Per bank write bursts +system.physmem.perBankWrBursts::13 2801 # Per bank write bursts +system.physmem.perBankWrBursts::14 3392 # Per bank write bursts +system.physmem.perBankWrBursts::15 2900 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1840536161000 # Total gap between requests +system.physmem.totGap 1840523607000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 82323 # Read request sizes (log2) +system.physmem.readPktSize::6 82294 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 47461 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 64278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5619 # What read queue length does an incoming req see +system.physmem.writePktSize::6 47398 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 64239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5630 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 4551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,140 +153,137 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21805 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.777253 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.097266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 378.211296 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7203 33.03% 33.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4880 22.38% 55.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2010 9.22% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1038 4.76% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 857 3.93% 73.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 538 2.47% 75.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 425 1.95% 77.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 372 1.71% 79.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4482 20.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21805 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 39.654458 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 980.113813 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2073 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2452 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::33 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.991001 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.949703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 378.684450 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7216 33.13% 33.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4887 22.44% 55.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1962 9.01% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1034 4.75% 69.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 848 3.89% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 523 2.40% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 452 2.08% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 368 1.69% 79.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4490 20.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21780 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 39.592397 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 979.363215 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2076 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2075 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.858313 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.353134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.870235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.64% 1.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.34% 1.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.10% 2.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.24% 2.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1736 83.66% 85.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 36 1.73% 87.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 80 3.86% 91.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 17 0.82% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 12 0.58% 92.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.82% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 5 0.24% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.05% 94.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.05% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.10% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.14% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.05% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.19% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.05% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.10% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.05% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.14% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.43% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.19% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 65 3.13% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.14% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.14% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.05% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 2 0.10% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.05% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.05% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.05% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.10% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.10% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.10% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.05% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.14% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 4 0.19% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2075 # Writes before turning the bus around for reads -system.physmem.totQLat 914891250 # Total ticks spent queuing -system.physmem.totMemAccLat 2458035000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 411505000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11116.41 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2078 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.802214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.584158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.825875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 29 1.40% 1.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.29% 1.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.05% 1.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 6 0.29% 2.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1724 82.96% 84.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 39 1.88% 86.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 91 4.38% 91.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 19 0.91% 92.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.43% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 19 0.91% 93.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 4 0.19% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.10% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.14% 93.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.05% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 2 0.10% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.14% 94.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.05% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.14% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.19% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 8 0.38% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.19% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 76 3.66% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 6 0.29% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.05% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.14% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.10% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.05% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.10% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2078 # Writes before turning the bus around for reads +system.physmem.totQLat 922774500 # Total ticks spent queuing +system.physmem.totMemAccLat 2465393250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 411365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11216.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29866.41 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29966.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.86 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.86 # Average system read bandwidth in MiByte/s @@ -295,63 +292,63 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 2.86 # Average write queue length when enqueuing -system.physmem.readRowHits 70476 # Number of row buffer hits during reads -system.physmem.writeRowHits 37451 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.91 # Row buffer hit rate for writes -system.physmem.avgGap 14181533.63 # Average gap between requests -system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 81194400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 44195250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 317686200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 151936560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35637705585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 799850646000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 925140356955 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.881529 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1309035077000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45530160000 # Time in different power states +system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgWrQLen 16.09 # Average write queue length when enqueuing +system.physmem.readRowHits 70442 # Number of row buffer hits during reads +system.physmem.writeRowHits 37434 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.98 # Row buffer hit rate for writes +system.physmem.avgGap 14191496.83 # Average gap between requests +system.physmem.pageHitRate 83.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 81065880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 44121000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 317530200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 151593120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35745647625 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 800947233750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 926343167415 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.792687 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1308857547000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9110965500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9287627500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 83651400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 45474000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 324261600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 155416320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35441943930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 803933138250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 929040878460 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.556246 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1309294919000 # Time in different power states -system.physmem_1.memoryStateTime::REF 45530160000 # Time in different power states +system.physmem_1.actEnergy 83590920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 45449250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 324199200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 155448720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35447161140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 801537520500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 926649345570 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.749891 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309278655250 # Time in different power states +system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8868165750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8857363000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4775602 # DTB read hits -system.cpu0.dtb.read_misses 5966 # DTB read misses +system.cpu0.dtb.read_hits 4774172 # DTB read hits +system.cpu0.dtb.read_misses 5959 # DTB read misses system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 428378 # DTB read accesses -system.cpu0.dtb.write_hits 3387346 # DTB write hits -system.cpu0.dtb.write_misses 667 # DTB write misses +system.cpu0.dtb.read_accesses 427834 # DTB read accesses +system.cpu0.dtb.write_hits 3388527 # DTB write hits +system.cpu0.dtb.write_misses 664 # DTB write misses system.cpu0.dtb.write_acv 80 # DTB write access violations -system.cpu0.dtb.write_accesses 163776 # DTB write accesses -system.cpu0.dtb.data_hits 8162948 # DTB hits -system.cpu0.dtb.data_misses 6633 # DTB misses +system.cpu0.dtb.write_accesses 164366 # DTB write accesses +system.cpu0.dtb.data_hits 8162699 # DTB hits +system.cpu0.dtb.data_misses 6623 # DTB misses system.cpu0.dtb.data_acv 189 # DTB access violations -system.cpu0.dtb.data_accesses 592154 # DTB accesses -system.cpu0.itb.fetch_hits 2717036 # ITB hits -system.cpu0.itb.fetch_misses 3019 # ITB misses +system.cpu0.dtb.data_accesses 592200 # DTB accesses +system.cpu0.itb.fetch_hits 2715643 # ITB hits +system.cpu0.itb.fetch_misses 3015 # ITB misses system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2720055 # ITB accesses +system.cpu0.itb.fetch_accesses 2718658 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -364,67 +361,67 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 930055234 # number of cpu cycles simulated +system.cpu0.numCycles 928469977 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31475732 # Number of instructions committed -system.cpu0.committedOps 31475732 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 29412106 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 162586 # Number of float alu accesses -system.cpu0.num_func_calls 792411 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4104277 # number of instructions that are conditional controls -system.cpu0.num_int_insts 29412106 # number of integer instructions -system.cpu0.num_fp_insts 162586 # number of float instructions -system.cpu0.num_int_register_reads 40967178 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21562005 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84110 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 85570 # number of times the floating registers were written -system.cpu0.num_mem_refs 8192042 # number of memory refs -system.cpu0.num_load_insts 4796241 # Number of load instructions -system.cpu0.num_store_insts 3395801 # Number of store instructions -system.cpu0.num_idle_cycles 907058327.289346 # Number of idle cycles -system.cpu0.num_busy_cycles 22996906.710654 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024726 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975274 # Percentage of idle cycles -system.cpu0.Branches 5151040 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1559860 4.95% 4.95% # Class of executed instruction -system.cpu0.op_class::IntAlu 21040910 66.83% 71.79% # Class of executed instruction -system.cpu0.op_class::IntMult 31347 0.10% 71.89% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.89% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12827 0.04% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1598 0.01% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::MemRead 4926196 15.65% 87.58% # Class of executed instruction -system.cpu0.op_class::MemWrite 3398883 10.80% 98.38% # Class of executed instruction -system.cpu0.op_class::IprAccess 510933 1.62% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30414467 # Number of instructions committed +system.cpu0.committedOps 30414467 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28351523 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 162419 # Number of float alu accesses +system.cpu0.num_func_calls 792250 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3751370 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28351523 # number of integer instructions +system.cpu0.num_fp_insts 162419 # number of float instructions +system.cpu0.num_int_register_reads 39201854 # number of times the integer registers were read +system.cpu0.num_int_register_writes 20853832 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84043 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 85470 # number of times the floating registers were written +system.cpu0.num_mem_refs 8191763 # number of memory refs +system.cpu0.num_load_insts 4794790 # Number of load instructions +system.cpu0.num_store_insts 3396973 # Number of store instructions +system.cpu0.num_idle_cycles 905786099.867998 # Number of idle cycles +system.cpu0.num_busy_cycles 22683877.132002 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024431 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975569 # Percentage of idle cycles +system.cpu0.Branches 4797930 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1559380 5.13% 5.13% # Class of executed instruction +system.cpu0.op_class::IntAlu 19980835 65.68% 70.81% # Class of executed instruction +system.cpu0.op_class::IntMult 31353 0.10% 70.91% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.91% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12822 0.04% 70.95% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.95% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.95% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.95% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1598 0.01% 70.96% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::MemRead 4924664 16.19% 87.15% # Class of executed instruction +system.cpu0.op_class::MemWrite 3400050 11.18% 98.32% # Class of executed instruction +system.cpu0.op_class::IprAccess 510577 1.68% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31482554 # Class of executed instruction +system.cpu0.op_class::total 30421279 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211358 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211362 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl @@ -435,11 +432,11 @@ system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # nu system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818800243000 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38808500 0.00% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357216000 0.02% 98.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22351032000 1.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841547299500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818807757000 98.77% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38797500 0.00% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357175000 0.02% 98.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22331016000 1.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841534745500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -503,429 +500,429 @@ system.cpu0.kern.mode_switch_good::kernel 0.321851 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29750547000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2575384000 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809221366500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 29743380000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2567925500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809223438000 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393348 # number of replacements +system.cpu0.dcache.tags.replacements 1392924 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13255372 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393860 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.509830 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13249026 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393436 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.508170 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.816582 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.221248 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.959986 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.347298 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.320745 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.331953 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.335991 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 163.453449 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 171.208376 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.346359 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.319245 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.334391 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63362265 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63362265 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 3956098 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1080024 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2536463 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7572585 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3101293 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 830391 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1367001 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5298685 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113681 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19703 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51298 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184682 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122268 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21809 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55240 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199317 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7057391 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1910415 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3903464 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12871270 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7057391 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1910415 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3903464 # number of overall hits -system.cpu0.dcache.overall_hits::total 12871270 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 706776 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 97332 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 562527 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1366635 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 162364 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 44132 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 644654 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 851150 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9134 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2235 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7668 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19037 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 10 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 869140 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 141464 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1207181 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2217785 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 869140 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 141464 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1207181 # number of overall misses -system.cpu0.dcache.overall_misses::total 2217785 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2268250000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8231829500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10500079500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1752940000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19634310548 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21387250548 # number of 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27866140048 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31887330048 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4662874 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1177356 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3098990 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8939220 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3263657 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 874523 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2011655 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149835 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 122815 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21938 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58966 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203719 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122268 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21809 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55250 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 63330121 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63330121 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 3955641 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1077876 # number of ReadReq hits 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+system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55320 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199316 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7058116 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1906395 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3900824 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12865335 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7058116 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1906395 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3900824 # number of overall hits +system.cpu0.dcache.overall_hits::total 12865335 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 705857 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 97562 # number of ReadReq misses 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misses +system.cpu0.dcache.demand_misses::cpu0.data 868286 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 141529 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1206130 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2215945 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 868286 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 141529 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1206130 # number of overall misses +system.cpu0.dcache.overall_misses::total 2215945 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2272668500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8215053500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 10487722000 # number of ReadReq miss cycles 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miss cycles +system.cpu0.dcache.demand_miss_latency::total 31865135277 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4023480000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27841655277 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31865135277 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4661498 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1175438 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 3094427 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8931363 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3264904 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 872486 # number of WriteReq accesses(hits+misses) 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# number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 7926531 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2051879 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5110645 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15089055 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 7926531 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2051879 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5110645 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15089055 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151575 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082670 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181519 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152881 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049749 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050464 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.320460 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.138402 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.074372 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101878 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093447 # miss rate for LoadLockedReq accesses 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miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14633.661140 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 7683.163025 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39720.384302 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30457.129791 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25127.475237 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13225.503356 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16297.861242 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8117.402952 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 17050 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17050 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28425.535825 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23083.646983 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14378.007809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28425.535825 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23083.646983 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14378.007809 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1019885 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1764 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 60259 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 7926402 # number of demand (read+write) accesses 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# miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049750 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050393 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.320316 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.138382 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075180 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102289 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.132584 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094707 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000199 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000055 # miss rate for StoreCondReq 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ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39821.036232 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30445.644072 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25119.163937 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13224.699064 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16277.727971 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8131.101198 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16727.272727 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16727.272727 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28428.661264 # average overall miss latency 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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 226454500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 334463500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 560918000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298425500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 450956500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 749382000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 524880000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 785420000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1310300000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082670 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087102 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041084 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050464 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047736 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022791 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101878 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.101380 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040315 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000181 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033628 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033628 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22304.257593 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16399.408733 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17964.319653 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38720.384302 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32351.624682 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34356.947881 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12225.503356 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12496.068919 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.440034 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16050 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16050 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204381.317690 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214537.203335 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210317.960255 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215158.976208 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211915.648496 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.448080 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210372.745491 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213024.138866 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211954.060175 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3514 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2493 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3686 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6179 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2175106500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4426228500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6601335000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1706844500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3108596312 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4815440812 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 27420000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77097500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104517500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 173000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 173000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3881951000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7534824812 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11416775812 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3881951000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7534824812 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11416775812 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 226227500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 334192500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 560420000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298200000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 450969000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 749169000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 524427500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 785161500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1309589000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083001 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087227 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041145 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050393 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047752 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022776 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102289 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.104719 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.041314 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000199 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069109 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071671 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033654 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069109 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071671 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033654 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22294.607532 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16398.419150 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17963.793948 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38821.036232 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32346.506477 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34378.816392 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12224.699064 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12501.621534 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12427.764566 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15727.272727 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15727.272727 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27428.661264 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.771887 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22493.893827 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27428.661264 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.771887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22493.893827 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204360.885276 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214500.962773 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210288.930582 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215151.515152 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211921.522556 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.503699 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210360.008022 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213011.801411 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211941.899984 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 965393 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.914113 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41264625 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 965904 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.721249 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10188445500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.904249 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 135.394605 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 228.615259 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286922 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.264443 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.446514 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997879 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 963177 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.919668 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 40183368 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 963688 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 41.697487 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10187899500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 148.948748 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 136.141622 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 225.829298 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.290916 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.265902 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.441073 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997890 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43213951 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43213951 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30975792 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7803098 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2485735 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41264625 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30975792 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7803098 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2485735 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41264625 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30975792 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7803098 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2485735 # number of overall hits -system.cpu0.icache.overall_hits::total 41264625 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 506762 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129019 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 347436 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 983217 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 506762 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129019 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 347436 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 983217 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 506762 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129019 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 347436 # number of overall misses -system.cpu0.icache.overall_misses::total 983217 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1839982500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4838575988 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6678558488 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1839982500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4838575988 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6678558488 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1839982500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4838575988 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6678558488 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 31482554 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7932117 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2833171 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42247842 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 31482554 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7932117 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2833171 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42247842 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 31482554 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7932117 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2833171 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42247842 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016097 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016265 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122631 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023273 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016097 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016265 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122631 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023273 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016097 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016265 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122631 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023273 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14261.329727 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13926.524563 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6792.557989 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14261.329727 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13926.524563 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6792.557989 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14261.329727 # average overall miss latency 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was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.312236 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 17108 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 17108 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 17108 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 17108 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 17108 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 17108 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129019 # number of ReadReq MSHR misses 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mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16698 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16698 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16698 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16698 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16698 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16698 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128884 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 328260 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 457144 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 128884 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 328260 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 457144 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 128884 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 328260 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 457144 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1711275000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4293223488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6004498488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1711275000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4293223488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6004498488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1711275000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4293223488 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6004498488 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011105 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011105 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011105 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13134.807605 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1196955 # DTB read hits +system.cpu1.dtb.read_hits 1195033 # DTB read hits system.cpu1.dtb.read_misses 1325 # DTB read misses system.cpu1.dtb.read_acv 35 # DTB read access violations system.cpu1.dtb.read_accesses 141268 # DTB read accesses -system.cpu1.dtb.write_hits 896481 # DTB write hits +system.cpu1.dtb.write_hits 894434 # DTB write hits system.cpu1.dtb.write_misses 169 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57742 # DTB write accesses -system.cpu1.dtb.data_hits 2093436 # DTB hits +system.cpu1.dtb.write_accesses 56923 # DTB write accesses +system.cpu1.dtb.data_hits 2089467 # DTB hits system.cpu1.dtb.data_misses 1494 # DTB misses system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 199010 # DTB accesses -system.cpu1.itb.fetch_hits 858438 # ITB hits +system.cpu1.dtb.data_accesses 198191 # DTB accesses +system.cpu1.itb.fetch_hits 856224 # ITB hits system.cpu1.itb.fetch_misses 659 # ITB misses system.cpu1.itb.fetch_acv 35 # ITB acv -system.cpu1.itb.fetch_accesses 859097 # ITB accesses +system.cpu1.itb.fetch_accesses 856883 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -938,64 +935,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953273349 # number of cpu cycles simulated +system.cpu1.numCycles 953248779 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7930565 # Number of instructions committed -system.cpu1.committedOps 7930565 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7389333 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45920 # Number of float alu accesses -system.cpu1.num_func_calls 207460 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1022605 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7389333 # number of integer instructions -system.cpu1.num_fp_insts 45920 # number of float instructions -system.cpu1.num_int_register_reads 10362144 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5369975 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24736 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 25085 # number of times the floating registers were written -system.cpu1.num_mem_refs 2100568 # number of memory refs -system.cpu1.num_load_insts 1201762 # Number of load instructions -system.cpu1.num_store_insts 898806 # Number of store instructions -system.cpu1.num_idle_cycles 922154358.750069 # Number of idle cycles -system.cpu1.num_busy_cycles 31118990.249931 # Number of busy cycles -system.cpu1.not_idle_fraction 0.032644 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.967356 # Percentage of idle cycles -system.cpu1.Branches 1296677 # Number of branches fetched -system.cpu1.op_class::No_OpClass 410840 5.18% 5.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 5240708 66.07% 71.25% # Class of executed instruction -system.cpu1.op_class::IntMult 8731 0.11% 71.36% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.36% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5176 0.07% 71.42% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.42% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.42% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.42% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 71.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::MemRead 1230901 15.52% 86.95% # Class of executed instruction -system.cpu1.op_class::MemWrite 900034 11.35% 98.30% # Class of executed instruction -system.cpu1.op_class::IprAccess 134916 1.70% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7920155 # Number of instructions committed +system.cpu1.committedOps 7920155 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7379126 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45865 # Number of float alu accesses +system.cpu1.num_func_calls 207333 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1021718 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7379126 # number of integer instructions +system.cpu1.num_fp_insts 45865 # number of float instructions +system.cpu1.num_int_register_reads 10346831 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5362502 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24725 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 25053 # number of times the floating registers were written +system.cpu1.num_mem_refs 2096589 # number of memory refs +system.cpu1.num_load_insts 1199833 # Number of load instructions +system.cpu1.num_store_insts 896756 # Number of store instructions +system.cpu1.num_idle_cycles 922000099.418594 # Number of idle cycles +system.cpu1.num_busy_cycles 31248679.581406 # Number of busy cycles +system.cpu1.not_idle_fraction 0.032781 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.967219 # Percentage of idle cycles +system.cpu1.Branches 1295631 # Number of branches fetched +system.cpu1.op_class::No_OpClass 410705 5.18% 5.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 5234650 66.08% 71.26% # Class of executed instruction +system.cpu1.op_class::IntMult 8605 0.11% 71.37% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.37% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5163 0.07% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::MemRead 1228944 15.51% 86.96% # Class of executed instruction +system.cpu1.op_class::MemWrite 897985 11.34% 98.30% # Class of executed instruction +system.cpu1.op_class::IprAccess 134844 1.70% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7932116 # Class of executed instruction +system.cpu1.op_class::total 7921706 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1013,35 +1010,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 10402334 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9657881 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 126933 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8330137 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6272162 # Number of BTB hits +system.cpu2.branchPred.lookups 11475270 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10735483 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 123474 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 9110272 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 7311084 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 75.294824 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 302639 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7723 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.250996 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 301261 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7742 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3549115 # DTB read hits -system.cpu2.dtb.read_misses 12776 # DTB read misses -system.cpu2.dtb.read_acv 157 # DTB read access violations -system.cpu2.dtb.read_accesses 225358 # DTB read accesses -system.cpu2.dtb.write_hits 2157791 # DTB write hits -system.cpu2.dtb.write_misses 2831 # DTB write misses -system.cpu2.dtb.write_acv 142 # DTB write access violations -system.cpu2.dtb.write_accesses 84650 # DTB write accesses -system.cpu2.dtb.data_hits 5706906 # DTB hits -system.cpu2.dtb.data_misses 15607 # DTB misses -system.cpu2.dtb.data_acv 299 # DTB access violations -system.cpu2.dtb.data_accesses 310008 # DTB accesses -system.cpu2.itb.fetch_hits 538598 # ITB hits -system.cpu2.itb.fetch_misses 5991 # ITB misses -system.cpu2.itb.fetch_acv 159 # ITB acv -system.cpu2.itb.fetch_accesses 544589 # ITB accesses +system.cpu2.dtb.read_hits 3542926 # DTB read hits +system.cpu2.dtb.read_misses 12527 # DTB read misses +system.cpu2.dtb.read_acv 162 # DTB read access violations +system.cpu2.dtb.read_accesses 225242 # DTB read accesses +system.cpu2.dtb.write_hits 2156991 # DTB write hits +system.cpu2.dtb.write_misses 2860 # DTB write misses +system.cpu2.dtb.write_acv 147 # DTB write access violations +system.cpu2.dtb.write_accesses 84372 # DTB write accesses +system.cpu2.dtb.data_hits 5699917 # DTB hits +system.cpu2.dtb.data_misses 15387 # DTB misses +system.cpu2.dtb.data_acv 309 # DTB access violations +system.cpu2.dtb.data_accesses 309614 # DTB accesses +system.cpu2.itb.fetch_hits 534150 # ITB hits +system.cpu2.itb.fetch_misses 5562 # ITB misses +system.cpu2.itb.fetch_acv 158 # ITB acv +system.cpu2.itb.fetch_accesses 539712 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1054,304 +1051,304 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30759536 # number of cpu cycles simulated +system.cpu2.numCycles 31796057 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9338114 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 39735788 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10402334 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6574801 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 19282744 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 413720 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 277 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1944 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 234903 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 108900 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 473 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2833173 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 93993 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 29183655 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.361577 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.367035 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9294739 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 42846452 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 11475270 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 7612345 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 20400927 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 406592 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 934 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9632 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1958 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 201207 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 109893 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2820959 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 91095 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 30222906 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.417681 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.345063 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20063773 68.75% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 307542 1.05% 69.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 477296 1.64% 71.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4654234 15.95% 87.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 859104 2.94% 90.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 198525 0.68% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 235442 0.81% 91.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 432653 1.48% 93.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1955086 6.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20065674 66.39% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 304778 1.01% 67.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 474119 1.57% 68.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5709833 18.89% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 849889 2.81% 90.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 195244 0.65% 91.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 232616 0.77% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433559 1.43% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1957194 6.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 29183655 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.338182 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.291820 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7672062 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13049396 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7739525 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 528158 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 193789 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 177139 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13443 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36353966 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42512 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 193789 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7950274 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4574250 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6325048 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7961138 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2178432 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35523870 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 60190 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 394243 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57916 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1115509 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 23763436 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44289897 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44229633 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56339 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21842362 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1921074 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 535035 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63809 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3839801 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3528507 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2250963 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 468940 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 330687 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32977065 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 683079 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32678030 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 15337 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2566331 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1147551 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 488786 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 29183655 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.119737 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.624192 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 30222906 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.360902 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.347540 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7641311 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13078900 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8781400 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 530431 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 190274 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 176731 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13389 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 39469462 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42545 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 190274 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7916618 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4614900 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6334560 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 9009266 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2156706 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 38654408 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 61763 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 395728 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57668 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1091797 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 25842385 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 48471958 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 48411597 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56430 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 23967156 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1875229 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 535043 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63361 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3828496 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3518120 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2250866 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 468779 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 334709 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 36116015 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 683906 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 35834403 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 15167 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2521371 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1120007 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 489344 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 30222906 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.185670 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.632890 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17436459 59.75% 59.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2753806 9.44% 69.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1377159 4.72% 73.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5375832 18.42% 92.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1030141 3.53% 95.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 601956 2.06% 97.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 392573 1.35% 99.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 169204 0.58% 99.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 46525 0.16% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17428882 57.67% 57.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2748935 9.10% 66.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1369590 4.53% 71.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 6435558 21.29% 92.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1033977 3.42% 96.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 595062 1.97% 97.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 394555 1.31% 99.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 169710 0.56% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 46637 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 29183655 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 30222906 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 85386 21.51% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 184726 46.54% 68.05% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126802 31.95% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 86081 21.74% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 183352 46.31% 68.05% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126504 31.95% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26465043 80.99% 80.99% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21101 0.06% 81.06% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20515 0.06% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3679518 11.26% 92.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2182790 6.68% 99.07% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 305379 0.93% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 29630335 82.69% 82.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21208 0.06% 82.75% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20533 0.06% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3671135 10.24% 93.06% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2181666 6.09% 99.15% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 305842 0.85% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32678030 # Type of FU issued -system.cpu2.iq.rate 1.062371 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 396914 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.012146 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 94697637 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 36112111 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32047154 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 254329 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 120282 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 117366 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32936079 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 136409 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206083 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 35834403 # Type of FU issued +system.cpu2.iq.rate 1.127008 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 395937 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011049 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 102047941 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39206340 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 35210799 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 254875 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 120668 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117568 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36091226 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136658 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206130 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 440040 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1257 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6058 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 180485 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 426126 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1149 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5847 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 179431 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5073 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 225988 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5057 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 224722 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 193789 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3993186 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 173385 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35054322 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 55127 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3528507 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2250963 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 608084 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 13021 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 119091 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6058 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 64339 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 136180 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 200519 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32475558 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3570784 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 202472 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 190274 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4003128 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 196899 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 38192826 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 53825 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3518120 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2250866 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 608609 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12914 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 142416 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5847 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 60692 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 135198 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195890 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 35634663 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3564372 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 199740 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1394178 # number of nop insts executed -system.cpu2.iew.exec_refs 5736169 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7344406 # Number of branches executed -system.cpu2.iew.exec_stores 2165385 # Number of stores executed -system.cpu2.iew.exec_rate 1.055788 # Inst execution rate -system.cpu2.iew.wb_sent 32207740 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32164520 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18733989 # num instructions producing a value -system.cpu2.iew.wb_consumers 22461298 # num instructions consuming a value +system.cpu2.iew.exec_nop 1392905 # number of nop insts executed +system.cpu2.iew.exec_refs 5729004 # number of memory reference insts executed +system.cpu2.iew.exec_branches 8402054 # Number of branches executed +system.cpu2.iew.exec_stores 2164632 # Number of stores executed +system.cpu2.iew.exec_rate 1.120726 # Inst execution rate +system.cpu2.iew.wb_sent 35371199 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 35328367 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 20848782 # num instructions producing a value +system.cpu2.iew.wb_consumers 24577214 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.045676 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.834056 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.111093 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.848297 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2690484 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 194293 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182480 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28713100 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.125605 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.869287 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2641573 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194562 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 179155 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 29759977 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.193046 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.869762 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18196306 63.37% 63.37% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2254505 7.85% 71.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1188955 4.14% 75.37% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5110402 17.80% 93.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 563606 1.96% 95.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 199238 0.69% 95.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 165515 0.58% 96.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 164290 0.57% 96.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 870283 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18187552 61.11% 61.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2254342 7.58% 68.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1186941 3.99% 72.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6165862 20.72% 93.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 562678 1.89% 95.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 198394 0.67% 95.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 165216 0.56% 96.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 166703 0.56% 97.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 872289 2.93% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28713100 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32319619 # Number of instructions committed -system.cpu2.commit.committedOps 32319619 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 29759977 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 35505021 # Number of instructions committed +system.cpu2.commit.committedOps 35505021 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5158945 # Number of memory references committed -system.cpu2.commit.loads 3088467 # Number of loads committed -system.cpu2.commit.membars 68233 # Number of memory barriers committed -system.cpu2.commit.branches 7171529 # Number of branches committed -system.cpu2.commit.fp_insts 115750 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30796114 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241665 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1228262 3.80% 3.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 25515212 78.95% 82.75% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20642 0.06% 82.81% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.81% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20078 0.06% 82.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3156700 9.77% 92.64% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2072118 6.41% 99.06% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 305379 0.94% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5163429 # Number of memory references committed +system.cpu2.commit.loads 3091994 # Number of loads committed +system.cpu2.commit.membars 68344 # Number of memory barriers committed +system.cpu2.commit.branches 8230032 # Number of branches committed +system.cpu2.commit.fp_insts 115972 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 33980571 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241816 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1228927 3.46% 3.46% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 28694755 80.82% 84.28% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20756 0.06% 84.34% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.34% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20096 0.06% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3160338 8.90% 93.30% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2073079 5.84% 99.14% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 305842 0.86% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 32319619 # Class of committed instruction -system.cpu2.commit.bw_lim_events 870283 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 62775514 # The number of ROB reads -system.cpu2.rob.rob_writes 70489103 # The number of ROB writes -system.cpu2.timesIdled 177769 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1575881 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745050657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31093813 # Number of Instructions Simulated -system.cpu2.committedOps 31093813 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.989249 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.989249 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.010867 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.010867 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42649325 # number of integer regfile reads -system.cpu2.int_regfile_writes 22654905 # number of integer regfile writes -system.cpu2.fp_regfile_reads 71051 # number of floating regfile reads -system.cpu2.fp_regfile_writes 71293 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5005090 # number of misc regfile reads -system.cpu2.misc_regfile_writes 273836 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 35505021 # Class of committed instruction +system.cpu2.commit.bw_lim_events 872289 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 66956679 # The number of ROB reads +system.cpu2.rob.rob_writes 76754434 # The number of ROB writes +system.cpu2.timesIdled 177058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1573151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1744013124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 34278550 # Number of Instructions Simulated +system.cpu2.committedOps 34278550 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.927579 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.927579 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.078075 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.078075 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 46864030 # number of integer regfile reads +system.cpu2.int_regfile_writes 24760821 # number of integer regfile writes +system.cpu2.fp_regfile_reads 71108 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71427 # number of floating regfile writes +system.cpu2.misc_regfile_reads 6062934 # number of misc regfile reads +system.cpu2.misc_regfile_writes 274246 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1406,7 +1403,7 @@ system.iobus.reqLayer1.occupancy 105000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5370000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5366000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) @@ -1416,21 +1413,21 @@ system.iobus.reqLayer27.occupancy 7000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 89820170 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 89821669 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 8849000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8844000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254241 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254132 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693892852000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254241 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078390 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078390 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693892766000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254132 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078383 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078383 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1446,8 +1443,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9418962 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9418962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040792208 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2040792208 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040972707 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2040972707 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 9418962 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 9418962 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 9418962 # number of overall miss cycles @@ -1470,8 +1467,8 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 54444.867052 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49114.175202 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 49114.175202 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49118.519133 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 49118.519133 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency system.iocache.demand_avg_miss_latency::total 54444.867052 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency @@ -1496,8 +1493,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 70 system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5918962 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5918962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176792208 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1176792208 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176972707 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1176972707 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 5918962 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 5918962 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 5918962 # number of overall MSHR miss cycles @@ -1512,219 +1509,219 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68101.400926 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68101.400926 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68111.846470 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68111.846470 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337481 # number of replacements -system.l2c.tags.tagsinuse 65419.198683 # Cycle average of tags in use -system.l2c.tags.total_refs 4010491 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402643 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.960414 # Average number of references to valid blocks. +system.l2c.tags.replacements 337470 # number of replacements +system.l2c.tags.tagsinuse 65419.393999 # Cycle average of tags in use +system.l2c.tags.total_refs 4005329 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402632 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.947866 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54563.896309 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2274.571035 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2764.017947 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 537.574504 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 599.716909 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2426.240023 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2253.181956 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.832579 # Average percentage of cache occupancy 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uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 527107500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 282261000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 426497000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 708758000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 494651000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 741214500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1235865500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.709677 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.511628 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407287 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255964 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.140765 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007353 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.158376 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061563 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030004 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034942 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034942 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 27590.909091 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 27590.909091 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 20750 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66107.210415 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 78998.458105 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73561.744762 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71836.547937 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64133.584882 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64582.773456 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64366.404985 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191881.317690 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202037.203335 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197817.960255 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203658.976208 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200415.648496 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.448080 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198428.657315 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201101.301871 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 200022.646393 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.523810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408930 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255830 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.140797 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007340 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.157938 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061492 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030003 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034964 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034964 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 34272.727273 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 34272.727273 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 21000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 21000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66089.882641 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79053.307630 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73584.633614 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72726.745830 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64248.429867 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64555.503154 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64407.596407 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191860.885276 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202000.962773 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197788.930582 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203651.515152 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200421.522556 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.503699 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198415.964701 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201089.120998 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 200010.600421 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294958 # Transaction distribution +system.membus.trans_dist::ReadResp 294907 # Transaction distribution system.membus.trans_dist::WriteReq 9810 # Transaction distribution system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 116948 # Transaction distribution -system.membus.trans_dist::CleanEvict 262295 # Transaction distribution -system.membus.trans_dist::UpgradeReq 165 # Transaction distribution +system.membus.trans_dist::Writeback 116913 # Transaction distribution +system.membus.trans_dist::CleanEvict 262319 # Transaction distribution +system.membus.trans_dist::UpgradeReq 141 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 167 # Transaction distribution -system.membus.trans_dist::ReadExReq 115610 # Transaction distribution -system.membus.trans_dist::ReadExResp 115610 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287819 # Transaction distribution -system.membus.trans_dist::BadAddressError 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 143 # Transaction distribution +system.membus.trans_dist::ReadExReq 115651 # Transaction distribution +system.membus.trans_dist::ReadExResp 115651 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287769 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144349 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1178267 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144270 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1178190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125023 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 125023 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1303213 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30629632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30675200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30626752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30672320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33339520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33336640 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 157 # Total snoops (count) -system.membus.snoop_fanout::samples 841413 # Request fanout histogram +system.membus.snoop_fanout::samples 841369 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 841413 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 841369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 841413 # Request fanout histogram -system.membus.reqLayer0.occupancy 11052000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 841369 # Request fanout histogram +system.membus.reqLayer0.occupancy 11017000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 394258327 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 393892331 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 441332932 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 441141955 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 29902743 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2064402 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2061814 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 883212 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1574760 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302767 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302767 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 966109 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1091169 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 883059 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1572257 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302698 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302698 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 963876 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1090815 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 17280 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2897413 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214892 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7112305 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61827200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142743552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204570752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 141567 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4877075 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.028983 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.167759 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2890767 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4213603 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7104370 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61685760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142710656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204396416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 141516 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4871742 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.029009 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.167832 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4735723 97.10% 97.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141352 2.90% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4730418 97.10% 97.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141324 2.90% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4877075 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1372572500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4871742 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1371248000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 689392754 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 686121188 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 777864461 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 778360963 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini index 1ce6d2d3e..d32706f99 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -179,7 +179,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -638,7 +638,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -748,7 +748,7 @@ sys=system port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -909,7 +909,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu1.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -1368,7 +1368,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu1.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -1478,7 +1478,7 @@ sys=system port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -1591,7 +1591,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1626,7 +1626,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -2041,9 +2041,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout index 7ec39e811..8e8bcf240 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 10:47:25 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:15:22 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2846057099000 because m5_exit instruction encountered +Exiting @ tick 2846117015000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 934713496..535c26a20 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,162 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846057 # Number of seconds simulated -sim_ticks 2846057099000 # Number of ticks simulated -final_tick 2846057099000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846117 # Number of seconds simulated +sim_ticks 2846117015000 # Number of ticks simulated +final_tick 2846117015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157157 # Simulator instruction rate (inst/s) -host_op_rate 190318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3507683540 # Simulator tick rate (ticks/s) -host_mem_usage 605024 # Number of bytes of host memory used -host_seconds 811.38 # Real time elapsed on the host -sim_insts 127513349 # Number of instructions simulated -sim_ops 154419501 # Number of ops (including micro ops) simulated +host_inst_rate 113156 # Simulator instruction rate (inst/s) +host_op_rate 137057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2513496102 # Simulator tick rate (ticks/s) +host_mem_usage 647580 # Number of bytes of host memory used +host_seconds 1132.33 # Real time elapsed on the host +sim_insts 128130877 # Number of instructions simulated +sim_ops 155193960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 7296 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1469184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1233972 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8227712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 2752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 383104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 711064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 574528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1474816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1242668 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8247680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 2432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 378112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 721620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 564672 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12611084 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1469184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 383104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1852288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8917568 # Number of bytes written to this memory +system.physmem.bytes_read::total 12640384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1474816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 378112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1852928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8933696 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8935132 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8951260 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 114 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 128558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 43 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5986 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11132 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 8977 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 23044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19938 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 128870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 38 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11296 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 8823 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197593 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 139337 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198048 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 139589 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143728 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2721 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 143980 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2563 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 516217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 433572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2890916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 134609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 249842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 201868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 518185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 436619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2897871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 132852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 253545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 198401 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4431072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 516217 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 134609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 650826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3133306 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4441273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 518185 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 132852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 651037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3138907 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3139477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3133306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3145078 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3138907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2563 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 516217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 439730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2890916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 134609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 249856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 201868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 518185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 442776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2897871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 132852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 253559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 198401 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7570549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197593 # Number of read requests accepted -system.physmem.writeReqs 143728 # Number of write requests accepted -system.physmem.readBursts 197593 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 143728 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12635520 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10432 # Total number of bytes read from write queue -system.physmem.bytesWritten 8947648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12611084 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8935132 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 163 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 51189 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12157 # Per bank write bursts -system.physmem.perBankRdBursts::1 12292 # Per bank write bursts -system.physmem.perBankRdBursts::2 12950 # Per bank write bursts -system.physmem.perBankRdBursts::3 12405 # Per bank write bursts -system.physmem.perBankRdBursts::4 15321 # Per bank write bursts -system.physmem.perBankRdBursts::5 12434 # Per bank write bursts -system.physmem.perBankRdBursts::6 12677 # Per bank write bursts -system.physmem.perBankRdBursts::7 13084 # Per bank write bursts -system.physmem.perBankRdBursts::8 12267 # Per bank write bursts -system.physmem.perBankRdBursts::9 12426 # Per bank write bursts -system.physmem.perBankRdBursts::10 11655 # Per bank write bursts -system.physmem.perBankRdBursts::11 11073 # Per bank write bursts -system.physmem.perBankRdBursts::12 11997 # Per bank write bursts -system.physmem.perBankRdBursts::13 11769 # Per bank write bursts -system.physmem.perBankRdBursts::14 11320 # Per bank write bursts -system.physmem.perBankRdBursts::15 11603 # Per bank write bursts -system.physmem.perBankWrBursts::0 8631 # Per bank write bursts -system.physmem.perBankWrBursts::1 8804 # Per bank write bursts -system.physmem.perBankWrBursts::2 9518 # Per bank write bursts -system.physmem.perBankWrBursts::3 8865 # Per bank write bursts -system.physmem.perBankWrBursts::4 8658 # Per bank write bursts -system.physmem.perBankWrBursts::5 8780 # Per bank write bursts -system.physmem.perBankWrBursts::6 9135 # Per bank write bursts -system.physmem.perBankWrBursts::7 9275 # Per bank write bursts -system.physmem.perBankWrBursts::8 8996 # Per bank write bursts -system.physmem.perBankWrBursts::9 8951 # Per bank write bursts -system.physmem.perBankWrBursts::10 8409 # Per bank write bursts -system.physmem.perBankWrBursts::11 8136 # Per bank write bursts -system.physmem.perBankWrBursts::12 8895 # Per bank write bursts -system.physmem.perBankWrBursts::13 8304 # Per bank write bursts -system.physmem.perBankWrBursts::14 8310 # Per bank write bursts -system.physmem.perBankWrBursts::15 8140 # Per bank write bursts +system.physmem.bw_total::total 7586351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198048 # Number of read requests accepted +system.physmem.writeReqs 143980 # Number of write requests accepted +system.physmem.readBursts 198048 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 143980 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12666176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue +system.physmem.bytesWritten 8963584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12640384 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8951260 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 51245 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12439 # Per bank write bursts +system.physmem.perBankRdBursts::1 12567 # Per bank write bursts +system.physmem.perBankRdBursts::2 12508 # Per bank write bursts +system.physmem.perBankRdBursts::3 12584 # Per bank write bursts +system.physmem.perBankRdBursts::4 14823 # Per bank write bursts +system.physmem.perBankRdBursts::5 11920 # Per bank write bursts +system.physmem.perBankRdBursts::6 13135 # Per bank write bursts +system.physmem.perBankRdBursts::7 13383 # Per bank write bursts +system.physmem.perBankRdBursts::8 12319 # Per bank write bursts +system.physmem.perBankRdBursts::9 12338 # Per bank write bursts +system.physmem.perBankRdBursts::10 11698 # Per bank write bursts +system.physmem.perBankRdBursts::11 11134 # Per bank write bursts +system.physmem.perBankRdBursts::12 11462 # Per bank write bursts +system.physmem.perBankRdBursts::13 11917 # Per bank write bursts +system.physmem.perBankRdBursts::14 11661 # Per bank write bursts +system.physmem.perBankRdBursts::15 12021 # Per bank write bursts +system.physmem.perBankWrBursts::0 8771 # Per bank write bursts +system.physmem.perBankWrBursts::1 9038 # Per bank write bursts +system.physmem.perBankWrBursts::2 9230 # Per bank write bursts +system.physmem.perBankWrBursts::3 8945 # Per bank write bursts +system.physmem.perBankWrBursts::4 8307 # Per bank write bursts +system.physmem.perBankWrBursts::5 8620 # Per bank write bursts +system.physmem.perBankWrBursts::6 9591 # Per bank write bursts +system.physmem.perBankWrBursts::7 9703 # Per bank write bursts +system.physmem.perBankWrBursts::8 8875 # Per bank write bursts +system.physmem.perBankWrBursts::9 8727 # Per bank write bursts +system.physmem.perBankWrBursts::10 8430 # Per bank write bursts +system.physmem.perBankWrBursts::11 8199 # Per bank write bursts +system.physmem.perBankWrBursts::12 8380 # Per bank write bursts +system.physmem.perBankWrBursts::13 8472 # Per bank write bursts +system.physmem.perBankWrBursts::14 8531 # Per bank write bursts +system.physmem.perBankWrBursts::15 8237 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 40 # Number of times write queue was full causing retry -system.physmem.totGap 2846056522500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 2846116455500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 555 # Read request sizes (log2) +system.physmem.readPktSize::2 552 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 197010 # Read request sizes (log2) +system.physmem.readPktSize::6 197468 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 139337 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9638 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 139589 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -184,159 +188,155 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10231 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 238.790065 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 135.540737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 300.321787 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48391 53.54% 53.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17645 19.52% 73.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6369 7.05% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3664 4.05% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2743 3.03% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1397 1.55% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 884 0.98% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1036 1.15% 90.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8256 9.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90385 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.264567 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 537.756673 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6984 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.015319 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.579154 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.029266 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5867 83.99% 83.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 359 5.14% 89.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 198 2.83% 91.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 50 0.72% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 72 1.03% 93.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 159 2.28% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.27% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.17% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.16% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.11% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.07% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 162 2.32% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.09% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.14% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.20% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads -system.physmem.totQLat 5478181174 # Total ticks spent queuing -system.physmem.totMemAccLat 9179993674 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 987150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27747.46 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 33 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 91138 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.329061 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.886171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 298.768529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 49038 53.81% 53.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17709 19.43% 73.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6298 6.91% 80.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3704 4.06% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2913 3.20% 87.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1386 1.52% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 897 0.98% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1023 1.12% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8170 8.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91138 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6991 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.308683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.324450 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6990 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6991 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6991 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.033758 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.625060 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.557866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5837 83.49% 83.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 357 5.11% 88.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 222 3.18% 91.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 60 0.86% 92.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 64 0.92% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 166 2.37% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 20 0.29% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.09% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.20% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.14% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 167 2.39% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.11% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.11% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 7 0.10% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.20% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6991 # Writes before turning the bus around for reads +system.physmem.totQLat 5451252873 # Total ticks spent queuing +system.physmem.totMemAccLat 9162046623 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 989545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27544.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46497.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46294.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.15 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.99 # Average write queue length when enqueuing -system.physmem.readRowHits 164056 # Number of row buffer hits during reads -system.physmem.writeRowHits 82794 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.21 # Row buffer hit rate for writes -system.physmem.avgGap 8338357.51 # Average gap between requests -system.physmem.pageHitRate 73.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 356771520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 194667000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 805888200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 464395680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83219414895 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634632736250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905564250425 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.546132 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719229075521 # Time in different power states -system.physmem_0.memoryStateTime::REF 95035980000 # Time in different power states +system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing +system.physmem.readRowHits 164305 # Number of row buffer hits during reads +system.physmem.writeRowHits 82521 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.91 # Row buffer hit rate for writes +system.physmem.avgGap 8321296.66 # Average gap between requests +system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 359440200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 196123125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 806200200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 467888400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185894445360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83210904225 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634677575750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905612577260 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.548459 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719308511052 # Time in different power states +system.physmem_0.memoryStateTime::REF 95038060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31791929979 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31769437698 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 326539080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178171125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 734050200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 441553680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82136174355 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635582947250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905289812570 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.449705 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720812978493 # Time in different power states -system.physmem_1.memoryStateTime::REF 95035980000 # Time in different power states +system.physmem_1.actEnergy 329563080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179821125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 737482200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 439674480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185894445360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82251132525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635519480750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905351599520 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.456762 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720714979061 # Time in different power states +system.physmem_1.memoryStateTime::REF 95038060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30205644507 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30363879439 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -362,15 +362,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 19599196 # Number of BP lookups -system.cpu0.branchPred.condPredicted 12768904 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 991514 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 12558764 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8839837 # Number of BTB hits +system.cpu0.branchPred.lookups 34784409 # Number of BP lookups +system.cpu0.branchPred.condPredicted 16478031 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1480168 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 19725615 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14342133 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.387795 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3295346 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 199810 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.708167 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 11162624 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 702720 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -401,58 +401,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 67395 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67395 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44710 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22685 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 67395 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 67395 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 67395 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6692 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10409.593545 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9352.624092 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5969.180600 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6501 97.15% 97.15% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 173 2.59% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 11 0.16% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6692 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 65972 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65972 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 43486 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22486 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 65972 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 65972 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 65972 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6612 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10372.504537 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9312.931281 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6218.139441 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6425 97.17% 97.17% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 170 2.57% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 7 0.11% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6612 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 327753000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 327753000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 327753000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5137 76.76% 76.76% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1555 23.24% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6692 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67395 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5105 77.21% 77.21% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1507 22.79% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6612 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65972 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67395 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6692 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6612 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6692 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 74087 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6612 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 72584 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 16492967 # DTB read hits -system.cpu0.dtb.read_misses 61485 # DTB read misses -system.cpu0.dtb.write_hits 13879033 # DTB write hits -system.cpu0.dtb.write_misses 5910 # DTB write misses +system.cpu0.dtb.read_hits 23562231 # DTB read hits +system.cpu0.dtb.read_misses 59962 # DTB read misses +system.cpu0.dtb.write_hits 17431474 # DTB write hits +system.cpu0.dtb.write_misses 6010 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3512 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1104 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1584 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3494 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1076 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1600 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16554452 # DTB read accesses -system.cpu0.dtb.write_accesses 13884943 # DTB write accesses +system.cpu0.dtb.perms_faults 577 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23622193 # DTB read accesses +system.cpu0.dtb.write_accesses 17437484 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 30372000 # DTB hits -system.cpu0.dtb.misses 67395 # DTB misses -system.cpu0.dtb.accesses 30439395 # DTB accesses +system.cpu0.dtb.hits 40993705 # DTB hits +system.cpu0.dtb.misses 65972 # DTB misses +system.cpu0.dtb.accesses 41059677 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -482,36 +482,36 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3867 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3867 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3867 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3867 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3867 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10756.092524 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9615.276250 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7885.681727 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 2419 99.92% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3855 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3855 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3550 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3855 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3855 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3855 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2424 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10979.785479 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9797.993767 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 8035.967164 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 2422 99.92% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::32768-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2424 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 327059500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 327059500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 327059500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2121 87.61% 87.61% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.39% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2124 87.62% 87.62% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.38% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2424 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3867 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3867 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3855 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3855 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6288 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 36759532 # ITB inst hits -system.cpu0.itb.inst_misses 3867 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2424 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2424 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6279 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 68397916 # ITB inst hits +system.cpu0.itb.inst_misses 3855 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -520,131 +520,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2226 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7295 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7522 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 36763399 # ITB inst accesses -system.cpu0.itb.hits 36759532 # DTB hits -system.cpu0.itb.misses 3867 # DTB misses -system.cpu0.itb.accesses 36763399 # DTB accesses -system.cpu0.numCycles 154883476 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 68401771 # ITB inst accesses +system.cpu0.itb.hits 68397916 # DTB hits +system.cpu0.itb.misses 3855 # DTB misses +system.cpu0.itb.accesses 68401771 # DTB accesses +system.cpu0.numCycles 225406925 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 75627253 # Number of instructions committed -system.cpu0.committedOps 91033342 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 4957970 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 2062 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5537267530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.047985 # CPI: cycles per instruction -system.cpu0.ipc 0.488285 # IPC: instructions per cycle +system.cpu0.committedInsts 107236402 # Number of instructions committed +system.cpu0.committedOps 129680129 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8567834 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 2087 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5466862375 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.101963 # CPI: cycles per instruction +system.cpu0.ipc 0.475746 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2064 # number of quiesce instructions executed -system.cpu0.tickCycles 121009607 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 33873869 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 680149 # number of replacements -system.cpu0.dcache.tags.tagsinuse 489.017964 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28930962 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 680661 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.504216 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 2088 # number of quiesce instructions executed +system.cpu0.tickCycles 187552407 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 37854518 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 678280 # number of replacements +system.cpu0.dcache.tags.tagsinuse 485.010035 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 39540240 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 678792 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 58.250893 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 345600000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.017964 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.955113 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.955113 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.010035 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947285 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.947285 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 60723709 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 60723709 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15008806 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15008806 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12795540 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12795540 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306691 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 306691 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356713 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 356713 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352309 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 352309 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27804346 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27804346 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 28111037 # number of overall hits -system.cpu0.dcache.overall_hits::total 28111037 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 442745 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 442745 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 557072 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 557072 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131875 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 131875 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21262 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21262 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21236 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21236 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 999817 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 999817 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1131692 # number of overall misses -system.cpu0.dcache.overall_misses::total 1131692 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5845429500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5845429500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8925410000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8925410000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 323710500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 323710500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 479970000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 479970000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 445000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 445000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 14770839500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14770839500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 14770839500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14770839500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15451551 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 15451551 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13352612 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13352612 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438566 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 438566 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377975 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 377975 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373545 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 373545 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 28804163 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 28804163 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 29242729 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 29242729 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028654 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028654 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041720 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041720 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300696 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300696 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056252 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056252 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056850 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056850 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034711 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.034711 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038700 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.038700 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13202.700200 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13202.700200 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16022.004337 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16022.004337 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15224.837739 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15224.837739 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22601.714070 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22601.714070 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81933612 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81933612 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 22071197 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22071197 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16340314 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16340314 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307086 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 307086 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357744 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 357744 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352756 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 352756 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 38411511 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 38411511 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 38718597 # number of overall hits +system.cpu0.dcache.overall_hits::total 38718597 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 442022 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 442022 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 555005 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 555005 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131972 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 131972 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20768 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20768 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21303 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21303 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 997027 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 997027 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1128999 # number of overall misses +system.cpu0.dcache.overall_misses::total 1128999 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5846536500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5846536500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8888918500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8888918500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 319234500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 319234500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481221000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 481221000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 684000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 684000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 14735455000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 14735455000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 14735455000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 14735455000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22513219 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22513219 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16895319 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16895319 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 439058 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 439058 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378512 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 378512 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 374059 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 374059 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 39408538 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 39408538 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39847596 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39847596 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019634 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019634 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032850 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.032850 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300580 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300580 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054867 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054867 # miss rate for LoadLockedReq accesses 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13051.996038 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14779.394139 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14779.394139 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.787468 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13051.787468 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,149 +653,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 493052 # number of writebacks -system.cpu0.dcache.writebacks::total 493052 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69962 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 69962 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244118 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 244118 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15072 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15072 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 314080 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 314080 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 314080 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 314080 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372783 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 372783 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312954 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312954 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99314 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 99314 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6190 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6190 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21236 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21236 # number of StoreCondReq MSHR misses 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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458745000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 434000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 434000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9361889500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9361889500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10974796000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10974796000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3751362500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3751362500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2725552500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725552500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6476915000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6476915000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024126 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024126 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023438 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023438 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226452 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226452 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016377 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016377 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056850 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056850 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023807 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023807 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026846 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026846 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11779.371645 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11779.371645 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15883.292752 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15883.292752 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16240.474656 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16240.474656 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15307.915994 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15307.915994 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21602.232059 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21602.232059 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 490245 # number of writebacks +system.cpu0.dcache.writebacks::total 490245 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69954 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 69954 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243081 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 243081 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14749 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14749 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 313035 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 313035 # number of demand (read+write) MSHR hits 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uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5696567000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4315116500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4315116500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10011683500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10011683500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016527 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016527 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018462 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018462 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226417 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226417 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015902 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015902 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056951 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056951 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017356 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.017356 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019660 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019660 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11823.481192 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11823.481192 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15898.619536 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15898.619536 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16181.043155 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16181.043155 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15369.579664 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15369.579664 # average LoadLockedReq mshr miss latency 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mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208397.450142 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162661.285510 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162661.285510 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186348.505337 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186348.505337 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13681.885168 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13681.885168 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13999.016469 # average overall mshr miss latency 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for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.051161 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9304.519888 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9304.519888 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9304.519888 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9304.519888 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 138666991 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 138666991 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 66503170 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 66503170 # number of ReadReq hits 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miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 17552107500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17552107500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 17552107500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17552107500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 68390054 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 68390054 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 68390054 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 68390054 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 68390054 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 68390054 # number of overall (read+write) accesses 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overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9302.165634 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,463 +804,463 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1880268 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1880268 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1880268 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1880268 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1880268 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1880268 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1886884 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1886884 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1886884 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1886884 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1886884 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1886884 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3426 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3426 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16554857500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16554857500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16554857500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16554857500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16554857500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16554857500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16608666000 # number of ReadReq MSHR miss cycles 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-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051161 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.051161 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.051161 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8804.520154 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8804.520154 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8804.520154 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027590 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027590 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027590 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8802.165899 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8802.165899 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8802.165899 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1762988 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1763146 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 137 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1753692 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1753724 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 223158 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 285163 # number of replacements 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+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40453.560105 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40453.560105 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38921.345401 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22761.226578 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22761.226578 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27852.629303 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31267.095420 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27852.629303 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46321.554224 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200392.006000 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.254212 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155145.738840 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155145.738840 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185586.624074 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174964.766224 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157428.197386 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157428.197386 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178579.235837 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170069.114527 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172334.109880 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167190.480225 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 136175 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2526619 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16756 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 865136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2178805 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 280675 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 92865 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43660 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114593 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 285252 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 271172 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1880268 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604912 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 134550 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2542059 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26162 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 862676 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2186135 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 279695 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 92964 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43745 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114531 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 284097 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 270085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1886884 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603437 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5613549 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2467613 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11765 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 169746 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8262673 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120556352 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82765674 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17352 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 318664 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 203658042 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1202366 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 6476462 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.183069 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.386723 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5633887 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2503276 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11828 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167039 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8316030 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120979776 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82538715 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17692 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314324 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 203850507 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1178802 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 6482684 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.179159 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.383485 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 5290820 81.69% 81.69% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1185642 18.31% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 5321256 82.08% 82.08% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1161428 17.92% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 6476462 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3195593995 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 6482684 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3211889987 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113765999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113481999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2825774529 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2835744437 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1168364927 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1181675942 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7430992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7408493 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 90084491 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 88460994 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 20439224 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7037667 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 906738 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 10483361 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 7695105 # Number of BTB hits +system.cpu1.branchPred.lookups 5445699 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3358034 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 328537 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3334781 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2260975 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.403034 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8822837 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 629691 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 67.799805 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 969415 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 68088 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1290,58 +1290,59 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 30282 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 30282 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22625 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7657 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 30282 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 30282 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 30282 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2657 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10518.253670 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9441.717442 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7245.373074 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 2512 94.54% 94.54% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 4.89% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.26% 99.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-98303 5 0.19% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-114687 2 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2657 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1594102264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1594102264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1594102264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1972 74.22% 74.22% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 685 25.78% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2657 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30282 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 29420 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 29420 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 21788 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7632 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 29420 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 29420 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 29420 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10739.844904 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9761.358244 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6619.660152 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 2565 94.72% 94.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 128 4.73% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 8 0.30% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.04% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-98303 4 0.15% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-114687 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1720699264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1720699264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1720699264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2021 74.63% 74.63% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 687 25.37% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 29420 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30282 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2657 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 29420 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2657 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 32939 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 32128 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12124185 # DTB read hits -system.cpu1.dtb.read_misses 27903 # DTB read misses -system.cpu1.dtb.write_hits 7716793 # DTB write hits -system.cpu1.dtb.write_misses 2379 # DTB write misses +system.cpu1.dtb.read_hits 5163963 # DTB read hits +system.cpu1.dtb.read_misses 27269 # DTB read misses +system.cpu1.dtb.write_hits 4235498 # DTB write hits +system.cpu1.dtb.write_misses 2151 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2053 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 374 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 549 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2054 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 296 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 518 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 291 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12152088 # DTB read accesses -system.cpu1.dtb.write_accesses 7719172 # DTB write accesses +system.cpu1.dtb.perms_faults 294 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5191232 # DTB read accesses +system.cpu1.dtb.write_accesses 4237649 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19840978 # DTB hits -system.cpu1.dtb.misses 30282 # DTB misses -system.cpu1.dtb.accesses 19871260 # DTB accesses +system.cpu1.dtb.hits 9399461 # DTB hits +system.cpu1.dtb.misses 29420 # DTB misses +system.cpu1.dtb.accesses 9428881 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1371,41 +1372,39 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2290 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2290 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2108 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2290 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2290 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2290 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 2244 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2244 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2063 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2244 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2244 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2244 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10627.337489 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9754.511529 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5025.096618 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 329 29.30% 29.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 526 46.84% 76.14% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 229 20.39% 96.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 14 1.25% 97.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.87% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10959.928762 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10069.580655 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5627.290327 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 289 25.73% 25.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 792 70.53% 96.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 4 0.36% 96.62% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 34 3.03% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1593536764 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1593536764 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1593536764 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::samples 1720133764 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1720133764 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1720133764 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 954 84.95% 84.95% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 169 15.05% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2290 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2290 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2244 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2244 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3413 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 41919801 # ITB inst hits -system.cpu1.itb.inst_misses 2290 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin::total 3367 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 10150571 # ITB inst hits +system.cpu1.itb.inst_misses 2244 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1418,126 +1417,126 @@ system.cpu1.itb.flush_entries 1161 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1868 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1947 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 41922091 # ITB inst accesses -system.cpu1.itb.hits 41919801 # DTB hits -system.cpu1.itb.misses 2290 # DTB misses -system.cpu1.itb.accesses 41922091 # DTB accesses -system.cpu1.numCycles 125017818 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10152815 # ITB inst accesses +system.cpu1.itb.hits 10150571 # DTB hits +system.cpu1.itb.misses 2244 # DTB misses +system.cpu1.itb.accesses 10152815 # DTB accesses +system.cpu1.numCycles 54273174 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51886096 # Number of instructions committed -system.cpu1.committedOps 63386159 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5353179 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2738 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5566469050 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.409467 # CPI: cycles per instruction -system.cpu1.ipc 0.415030 # IPC: instructions per cycle +system.cpu1.committedInsts 20894475 # Number of instructions committed +system.cpu1.committedOps 25513831 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1850967 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2736 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5637336830 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.597489 # CPI: cycles per instruction +system.cpu1.ipc 0.384987 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed -system.cpu1.tickCycles 105304281 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 19713537 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 231375 # number of replacements -system.cpu1.dcache.tags.tagsinuse 483.037999 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19321104 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 231701 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 83.388091 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90467560500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.037999 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943434 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.943434 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 253 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39693132 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39693132 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11664966 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11664966 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7379255 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7379255 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66113 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 66113 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88582 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88582 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80498 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80498 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19044221 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19044221 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19110334 # number of overall hits -system.cpu1.dcache.overall_hits::total 19110334 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 184342 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 184342 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 167268 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 167268 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34982 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 34982 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17676 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17676 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23450 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23450 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 351610 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 351610 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 386592 # number of overall misses -system.cpu1.dcache.overall_misses::total 386592 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2719374500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2719374500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4153510500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4153510500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325753000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 325753000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548137000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 548137000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 684500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 684500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6872885000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6872885000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6872885000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6872885000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11849308 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11849308 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7546523 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7546523 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101095 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 101095 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106258 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 106258 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103948 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 103948 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19395831 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19395831 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19496926 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19496926 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015557 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.015557 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022165 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.022165 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.346031 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.346031 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166350 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166350 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225594 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225594 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018128 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.018128 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019828 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.019828 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14751.790151 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14751.790151 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24831.471052 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24831.471052 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18429.112921 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18429.112921 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23374.712154 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23374.712154 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed +system.cpu1.tickCycles 38589177 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 15683997 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 232297 # number of replacements +system.cpu1.dcache.tags.tagsinuse 482.192292 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8906174 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 232671 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.277972 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90623150500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.192292 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941782 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.941782 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18859700 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18859700 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4719301 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4719301 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3908024 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3908024 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65371 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 65371 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88156 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88156 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80067 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 80067 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8627325 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8627325 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8692696 # number of overall hits +system.cpu1.dcache.overall_hits::total 8692696 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 183894 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 183894 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 168264 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 168264 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35705 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 35705 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17716 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17716 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23526 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23526 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 352158 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 352158 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 387863 # number of overall misses +system.cpu1.dcache.overall_misses::total 387863 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2718275000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2718275000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4151672000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4151672000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326404500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 326404500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549519500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 549519500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 392000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 392000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6869947000 # number of demand (read+write) miss cycles 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rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14781.749269 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14781.749269 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24673.560595 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24673.560595 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18424.277489 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18424.277489 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23357.965655 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23357.965655 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 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system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1546,148 +1545,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 138377 # number of writebacks -system.cpu1.dcache.writebacks::total 138377 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18221 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 18221 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62038 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 62038 # number of WriteReq MSHR hits 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# number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 544638000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 92810500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 92810500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524700000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524700000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 671500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 671500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4812143000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 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0.225594 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013990 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013990 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015634 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015634 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13815.887215 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13815.887215 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23919.357598 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23919.357598 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16275.827033 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16275.827033 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17026.325445 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17026.325445 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22375.266525 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22375.266525 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 139329 # number of writebacks +system.cpu1.dcache.writebacks::total 139329 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18066 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 18066 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62670 # number of WriteReq MSHR hits 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WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 559951000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 559951000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93173500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93173500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 526001500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 526001500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 384000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 384000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4805955500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4805955500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5365906500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5365906500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 990469500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 990469500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 857774500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 857774500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1848244000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1848244000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033820 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033820 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025904 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025904 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.338933 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.338933 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051515 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051515 # mshr miss rate for LoadLockedReq accesses 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23782.587079 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16345.116469 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16345.116469 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17083.516685 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17083.516685 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22358.305704 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22358.305704 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17734.016090 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17734.016090 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17573.933612 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17573.933612 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171349.427837 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171349.427837 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169843.977785 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169843.977785 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170661.703612 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170661.703612 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17706.580528 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17706.580528 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17553.999280 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17553.999280 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173098.479553 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173098.479553 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171246.656019 # average WriteReq mshr uncacheable latency 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(read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9237616500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9237616500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9237616500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 41917763 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 41917763 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 41917763 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 41917763 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 41917763 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 41917763 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024873 # miss rate for ReadReq accesses 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overall miss latency +system.cpu1.icache.tags.tag_accesses 21333497 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21333497 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 9111880 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9111880 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9111880 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9111880 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9111880 # number of overall hits +system.cpu1.icache.overall_hits::total 9111880 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 1036579 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 1036579 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 1036579 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 1036579 # number of demand (read+write) misses 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demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10148459 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10148459 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10148459 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.102142 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.102142 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.102142 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.102142 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.102142 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.102142 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8856.249741 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8856.249741 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8856.249741 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8856.249741 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8856.249741 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8856.249741 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1696,453 +1695,453 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed 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number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 1036579 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 113 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 113 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8716298000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8716298000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8716298000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8716298000 # number of demand (read+write) MSHR miss cycles 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89610.619469 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89610.619469 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89610.619469 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8661913000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8661913000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8661913000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8661913000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8661913000 # number of overall MSHR miss cycles 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queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 70190 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 69559 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15624.003278 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 2421583 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 84278 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 28.733276 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 68922 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 69326 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15661.573061 # Cycle average of tags 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32631.727491 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32807.374375 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17821.205078 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17821.205078 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22655.468961 # average overall mshr miss latency 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mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17768.987342 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33592.193891 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17084.195320 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17084.195320 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15524.650396 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15524.650396 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 324000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 324000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32602.420961 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32602.420961 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32857.947044 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17951.096211 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17951.096211 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22717.342843 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24690.019115 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22717.342843 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26510.479321 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165091.488990 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163463.410454 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163722.200040 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163722.200040 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164452.334358 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163582.949096 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 81005 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1348099 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 14405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 510462 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1265020 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 43516 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 77320 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42972 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89288 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 97251 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 79776 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1042637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 559861 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 80046 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1329975 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5009 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 511761 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1258534 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 43565 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76909 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43045 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89356 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 97332 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 80052 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1036579 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 560078 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3108261 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1040223 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7202 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71706 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 4227392 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66736000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29812791 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11216 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135068 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 96695075 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 1172897 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 3809713 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.296141 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.456554 # Request fanout histogram +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3090316 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1000986 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7189 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70268 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 4168759 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66348288 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29828599 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 132864 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 96321279 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 1191896 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 3797471 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.302048 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.459146 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2681500 70.39% 70.39% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1128213 29.61% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2650451 69.80% 69.80% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1147020 30.20% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 3809713 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1507501992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 3797471 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1487742991 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 87443999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87115499 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1564193862 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1555110854 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 470956198 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 456039835 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4398499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4307000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 37948980 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 37064974 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31013 # Transaction distribution -system.iobus.trans_dist::ReadResp 31013 # Transaction distribution +system.iobus.trans_dist::ReadReq 30994 # Transaction distribution +system.iobus.trans_dist::ReadResp 30994 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) @@ -2150,7 +2149,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2166,16 +2165,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72920 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72920 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180832 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2191,10 +2190,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484073 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483914 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2205,7 +2204,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2235,52 +2234,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187545199 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187482956 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36744000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36462 # number of replacements -system.iocache.tags.tagsinuse 14.479963 # Cycle average of tags in use +system.iocache.tags.replacements 36426 # number of replacements +system.iocache.tags.tagsinuse 1.010803 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36442 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270370198000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.479963 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904998 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904998 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270452648000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.010803 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.063175 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.063175 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328320 # Number of tag accesses -system.iocache.tags.data_accesses 328320 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses -system.iocache.ReadReq_misses::total 256 # number of ReadReq misses +system.iocache.tags.tag_accesses 328140 # Number of tag accesses +system.iocache.tags.data_accesses 328140 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 236 # number of ReadReq misses +system.iocache.ReadReq_misses::total 236 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 256 # number of demand (read+write) misses -system.iocache.demand_misses::total 256 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 256 # number of overall misses -system.iocache.overall_misses::total 256 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32688877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32688877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4277206322 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4277206322 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32688877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32688877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32688877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32688877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 236 # number of demand (read+write) misses +system.iocache.demand_misses::total 236 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 236 # number of overall misses +system.iocache.overall_misses::total 236 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 30330877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30330877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4273955079 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4273955079 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30330877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30330877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30330877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30330877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 236 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 236 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 256 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 256 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 256 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 256 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 236 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 236 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 236 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 236 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2289,40 +2288,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 127690.925781 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 127690.925781 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118076.587953 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118076.587953 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 127690.925781 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 127690.925781 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128520.665254 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128520.665254 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117986.834116 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117986.834116 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128520.665254 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128520.665254 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128520.665254 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128520.665254 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 236 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 236 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 256 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19888877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19888877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466006322 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2466006322 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19888877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19888877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19888877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19888877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 236 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 236 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 236 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 236 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18530877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18530877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2462755079 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2462755079 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18530877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18530877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18530877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18530877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2331,576 +2330,603 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77690.925781 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 77690.925781 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68076.587953 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68076.587953 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78520.665254 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78520.665254 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67986.834116 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67986.834116 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78520.665254 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78520.665254 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78520.665254 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78520.665254 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 134724 # number of replacements -system.l2c.tags.tagsinuse 64068.233504 # Cycle average of tags in use -system.l2c.tags.total_refs 443602 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 199053 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.228562 # Average number of references to valid blocks. +system.l2c.tags.replacements 135428 # number of replacements +system.l2c.tags.tagsinuse 64138.208301 # Cycle average of tags in use +system.l2c.tags.total_refs 442739 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 199807 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.215833 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12835.902941 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.531822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.025215 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7257.127456 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2101.817094 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32009.024605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 30.126345 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4045.876721 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1535.093827 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4184.707478 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.195860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001046 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12941.285088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.276334 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.031468 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7274.373268 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2166.846690 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 31945.045858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 24.318023 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4022.114049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1496.265741 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4197.799819 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.197468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001057 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.110735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.032071 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.488419 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000460 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023424 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.063854 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977604 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29296 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34966 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 113 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23800 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.110998 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.033063 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.487443 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000371 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061373 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.022831 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064053 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.978671 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 29250 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 35037 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 144 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5264 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 23842 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 313 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2923 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31711 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.447021 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.533539 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5827626 # Number of tag accesses -system.l2c.tags.data_accesses 5827626 # Number of data accesses -system.l2c.Writeback_hits::writebacks 232709 # number of Writeback hits -system.l2c.Writeback_hits::total 232709 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3025 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 939 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3964 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 83 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 340 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4055 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2183 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6238 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 387 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 52 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 44381 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47292 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46189 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 171 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 33 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 21681 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11241 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8230 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 179657 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 387 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 52 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 44381 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51347 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46189 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 171 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21681 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13424 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 8230 # number of demand (read+write) hits -system.l2c.demand_hits::total 185895 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 387 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 52 # number of overall hits -system.l2c.overall_hits::cpu0.inst 44381 # number of overall hits -system.l2c.overall_hits::cpu0.data 51347 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46189 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 171 # number of overall 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+system.l2c.overall_avg_mshr_miss_latency::total 87597.565398 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.728237 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145381.657323 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 155041.433892 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138140.158749 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145335.820896 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141466.544719 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167586.233263 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147195.872683 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154971.563736 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140424.604388 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146721.601118 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141436.495461 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161058.491815 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145360.715532 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 148983.329753 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154802.853134 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146974.410366 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 148931.800613 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 38664 # Transaction distribution -system.membus.trans_dist::ReadResp 213442 # Transaction distribution -system.membus.trans_dist::WriteReq 31161 # Transaction distribution -system.membus.trans_dist::WriteResp 31161 # Transaction distribution -system.membus.trans_dist::Writeback 139337 # Transaction distribution -system.membus.trans_dist::CleanEvict 18210 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78893 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41609 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14967 # Transaction distribution -system.membus.trans_dist::ReadExReq 39746 # Transaction distribution -system.membus.trans_dist::ReadExResp 19293 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174778 # Transaction distribution +system.membus.trans_dist::ReadReq 38683 # Transaction distribution +system.membus.trans_dist::ReadResp 213983 # Transaction distribution +system.membus.trans_dist::WriteReq 31171 # Transaction distribution +system.membus.trans_dist::WriteResp 31171 # Transaction distribution +system.membus.trans_dist::Writeback 139589 # Transaction distribution +system.membus.trans_dist::CleanEvict 18226 # Transaction distribution +system.membus.trans_dist::UpgradeReq 78324 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41642 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15039 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 39751 # Transaction distribution +system.membus.trans_dist::ReadExResp 19228 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 175300 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 681524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 804190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108938 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108938 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 913128 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 682330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 805060 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 913962 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29428 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19228072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19421637 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21739781 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 126569 # Total snoops (count) -system.membus.snoop_fanout::samples 598906 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19274524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19468214 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21785334 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 126049 # Total snoops (count) +system.membus.snoop_fanout::samples 599148 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 598906 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 599148 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 598906 # Request fanout histogram -system.membus.reqLayer0.occupancy 91147500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 599148 # Request fanout histogram +system.membus.reqLayer0.occupancy 91414000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 24328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12904500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12977999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1003618732 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1005422091 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1163956699 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1166590180 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64493538 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64371509 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2933,56 +2959,56 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 38668 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 519865 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31161 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 372085 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 99404 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 82727 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 124676 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51768 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51768 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 481212 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 38687 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 518927 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31171 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 372432 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 99547 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 82215 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41967 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 124182 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51561 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51561 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 480255 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1091980 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 404567 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1496547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32727326 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6930535 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39657861 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 466410 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1287380 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.161360 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.367862 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1133004 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 361504 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1494508 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32818575 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6820071 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39638646 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 465665 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1285667 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.162057 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.368503 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1079649 83.86% 83.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 207731 16.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1077316 83.79% 83.79% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 208351 16.21% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1287380 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 861414818 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1285667 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 860205550 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 361500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 331500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 631551677 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 646726661 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 286263459 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 269148617 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini index 46b536a54..37b26c84c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -179,7 +179,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -638,7 +638,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -748,7 +748,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -836,7 +836,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1251,9 +1251,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout index 174785dd4..f4a19412e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 10:47:25 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:06:44 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2852648357500 because m5_exit instruction encountered +Exiting @ tick 2852654988500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index b263a31ec..954a8904e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852648 # Number of seconds simulated -sim_ticks 2852648357500 # Number of ticks simulated -final_tick 2852648357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852655 # Number of seconds simulated +sim_ticks 2852654988500 # Number of ticks simulated +final_tick 2852654988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154527 # Simulator instruction rate (inst/s) -host_op_rate 186842 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3929586318 # Simulator tick rate (ticks/s) -host_mem_usage 575824 # Number of bytes of host memory used -host_seconds 725.94 # Real time elapsed on the host -sim_insts 112177181 # Number of instructions simulated -sim_ops 135636113 # Number of ops (including micro ops) simulated +host_inst_rate 116178 # Simulator instruction rate (inst/s) +host_op_rate 140471 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2957977243 # Simulator tick rate (ticks/s) +host_mem_usage 618900 # Number of bytes of host memory used +host_seconds 964.39 # Real time elapsed on the host +sim_insts 112040950 # Number of instructions simulated +sim_ops 135468925 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1670464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9187820 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 8064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1669952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9187372 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10867564 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1670464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1670464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7983168 # Number of bytes written to this memory +system.physmem.bytes_read::total 10866412 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1669952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1669952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7981376 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8000692 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26101 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144081 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7998900 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 126 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144074 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170327 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124737 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170309 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124709 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129118 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 585584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3220804 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129090 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 585403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3220639 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3809640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 585584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 585584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2798511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3809228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 585403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 585403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2797876 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2804654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2798511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 585584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3226947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2804019 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2797876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 585403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3226782 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6614294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170327 # Number of read requests accepted -system.physmem.writeReqs 129118 # Number of write requests accepted -system.physmem.readBursts 170327 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129118 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10891072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue -system.physmem.bytesWritten 8012864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10867564 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8000692 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6613247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170309 # Number of read requests accepted +system.physmem.writeReqs 129090 # Number of write requests accepted +system.physmem.readBursts 170309 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129090 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10890880 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue +system.physmem.bytesWritten 8010944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10866412 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7998900 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40818 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10912 # Per bank write bursts -system.physmem.perBankRdBursts::1 10835 # Per bank write bursts -system.physmem.perBankRdBursts::2 10722 # Per bank write bursts -system.physmem.perBankRdBursts::3 10734 # Per bank write bursts -system.physmem.perBankRdBursts::4 13360 # Per bank write bursts -system.physmem.perBankRdBursts::5 10814 # Per bank write bursts -system.physmem.perBankRdBursts::6 11148 # Per bank write bursts -system.physmem.perBankRdBursts::7 10988 # Per bank write bursts -system.physmem.perBankRdBursts::8 10136 # Per bank write bursts -system.physmem.perBankRdBursts::9 10280 # Per bank write bursts -system.physmem.perBankRdBursts::10 10233 # Per bank write bursts -system.physmem.perBankRdBursts::11 9195 # Per bank write bursts -system.physmem.perBankRdBursts::12 10314 # Per bank write bursts -system.physmem.perBankRdBursts::13 10738 # Per bank write bursts -system.physmem.perBankRdBursts::14 10036 # Per bank write bursts -system.physmem.perBankRdBursts::15 9728 # Per bank write bursts -system.physmem.perBankWrBursts::0 8115 # Per bank write bursts -system.physmem.perBankWrBursts::1 8199 # Per bank write bursts -system.physmem.perBankWrBursts::2 8378 # Per bank write bursts -system.physmem.perBankWrBursts::3 8308 # Per bank write bursts -system.physmem.perBankWrBursts::4 7548 # Per bank write bursts -system.physmem.perBankWrBursts::5 7862 # Per bank write bursts -system.physmem.perBankWrBursts::6 8189 # Per bank write bursts -system.physmem.perBankWrBursts::7 8102 # Per bank write bursts -system.physmem.perBankWrBursts::8 7754 # Per bank write bursts -system.physmem.perBankWrBursts::9 7814 # Per bank write bursts -system.physmem.perBankWrBursts::10 7662 # Per bank write bursts -system.physmem.perBankWrBursts::11 7060 # Per bank write bursts -system.physmem.perBankWrBursts::12 7768 # Per bank write bursts -system.physmem.perBankWrBursts::13 7969 # Per bank write bursts -system.physmem.perBankWrBursts::14 7379 # Per bank write bursts -system.physmem.perBankWrBursts::15 7094 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40828 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10905 # Per bank write bursts +system.physmem.perBankRdBursts::1 10842 # Per bank write bursts +system.physmem.perBankRdBursts::2 10713 # Per bank write bursts +system.physmem.perBankRdBursts::3 10735 # Per bank write bursts +system.physmem.perBankRdBursts::4 13349 # Per bank write bursts +system.physmem.perBankRdBursts::5 10818 # Per bank write bursts +system.physmem.perBankRdBursts::6 11158 # Per bank write bursts +system.physmem.perBankRdBursts::7 10982 # Per bank write bursts +system.physmem.perBankRdBursts::8 10119 # Per bank write bursts +system.physmem.perBankRdBursts::9 10274 # Per bank write bursts +system.physmem.perBankRdBursts::10 10247 # Per bank write bursts +system.physmem.perBankRdBursts::11 9187 # Per bank write bursts +system.physmem.perBankRdBursts::12 10322 # Per bank write bursts +system.physmem.perBankRdBursts::13 10753 # Per bank write bursts +system.physmem.perBankRdBursts::14 10041 # Per bank write bursts +system.physmem.perBankRdBursts::15 9725 # Per bank write bursts +system.physmem.perBankWrBursts::0 8109 # Per bank write bursts +system.physmem.perBankWrBursts::1 8208 # Per bank write bursts +system.physmem.perBankWrBursts::2 8370 # Per bank write bursts +system.physmem.perBankWrBursts::3 8304 # Per bank write bursts +system.physmem.perBankWrBursts::4 7540 # Per bank write bursts +system.physmem.perBankWrBursts::5 7865 # Per bank write bursts +system.physmem.perBankWrBursts::6 8185 # Per bank write bursts +system.physmem.perBankWrBursts::7 8104 # Per bank write bursts +system.physmem.perBankWrBursts::8 7740 # Per bank write bursts +system.physmem.perBankWrBursts::9 7807 # Per bank write bursts +system.physmem.perBankWrBursts::10 7671 # Per bank write bursts +system.physmem.perBankWrBursts::11 7052 # Per bank write bursts +system.physmem.perBankWrBursts::12 7765 # Per bank write bursts +system.physmem.perBankWrBursts::13 7977 # Per bank write bursts +system.physmem.perBankWrBursts::14 7383 # Per bank write bursts +system.physmem.perBankWrBursts::15 7091 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 2852647955000 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 2852654585000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169770 # Read request sizes (log2) +system.physmem.readPktSize::6 169752 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124737 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 282 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124709 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,116 +159,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60792 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.959863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.660922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.542835 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22288 36.66% 36.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14645 24.09% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6538 10.75% 71.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3485 5.73% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2623 4.31% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1593 2.62% 84.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1118 1.84% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1065 1.75% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7437 12.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60792 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6289 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.056766 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 539.634570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6287 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6545 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::34 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.442553 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.035683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.553660 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22186 36.56% 36.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14675 24.18% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6464 10.65% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3592 5.92% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2485 4.09% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1671 2.75% 84.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1111 1.83% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1120 1.85% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7387 12.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60691 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6290 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.051669 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 539.627643 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6288 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6289 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.907934 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.344478 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.522535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5503 87.50% 87.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 53 0.84% 88.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 178 2.83% 91.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.73% 91.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 61 0.97% 92.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 176 2.80% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.30% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.10% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.19% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.16% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.13% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 165 2.62% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.08% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.06% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.27% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6289 # Writes before turning the bus around for reads -system.physmem.totQLat 1698489250 # Total ticks spent queuing -system.physmem.totMemAccLat 4889233000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 850865000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9980.96 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6290 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6290 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.900000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.361154 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.375647 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5497 87.39% 87.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 61 0.97% 88.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 183 2.91% 91.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.73% 92.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 63 1.00% 93.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 171 2.72% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.30% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.13% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.16% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.16% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.03% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 171 2.72% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.03% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.08% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.05% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.24% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6290 # Writes before turning the bus around for reads +system.physmem.totQLat 1692148250 # Total ticks spent queuing +system.physmem.totMemAccLat 4882835750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850850000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9943.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28730.96 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28693.87 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s @@ -277,41 +277,41 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.43 # Average write queue length when enqueuing -system.physmem.readRowHits 140383 # Number of row buffer hits during reads -system.physmem.writeRowHits 94198 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing +system.physmem.readRowHits 140376 # Number of row buffer hits during reads +system.physmem.writeRowHits 94273 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.22 # Row buffer hit rate for writes -system.physmem.avgGap 9526450.45 # Average gap between requests -system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240748200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131360625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 698201400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 419262480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186320618640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83613121875 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638239679750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909662992970 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.436876 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725220726500 # Time in different power states -system.physmem_0.memoryStateTime::REF 95255940000 # Time in different power states +system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes +system.physmem.avgGap 9527936.25 # Average gap between requests +system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 240143400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131030625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 698115600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 419158800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186321127200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83459244105 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638379332000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909648151730 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.429846 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725453951250 # Time in different power states +system.physmem_0.memoryStateTime::REF 95256200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32164219750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31938521250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 218839320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119406375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 629140200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 392040000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186320618640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82051531065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639609496250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909341071850 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.324025 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727521283250 # Time in different power states -system.physmem_1.memoryStateTime::REF 95255940000 # Time in different power states +system.physmem_1.actEnergy 218680560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119319750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 629202600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 391949280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186321127200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82079606700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639589540250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909349426340 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.325127 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727485699500 # Time in different power states +system.physmem_1.memoryStateTime::REF 95256200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29871038250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29912992000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory @@ -331,15 +331,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31035995 # Number of BP lookups -system.cpu.branchPred.condPredicted 16848460 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2529330 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18616538 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13364370 # Number of BTB hits +system.cpu.branchPred.lookups 31017301 # Number of BP lookups +system.cpu.branchPred.condPredicted 16826801 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2510748 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18518050 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13329905 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.787622 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7827743 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1524480 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.983308 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7858653 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1517345 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -370,56 +370,57 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66851 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66851 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44044 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22807 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66851 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66851 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66851 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7848 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11969.673802 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9947.704899 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7432.490287 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6134 78.16% 78.16% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1708 21.76% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 65935 # Table walker walks requested +system.cpu.dtb.walker.walksShort 65935 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43131 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22804 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 65935 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 65935 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 65935 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7817 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11967.954458 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9949.329384 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7404.205030 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6115 78.23% 78.23% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.70% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7848 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7817 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 260813000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 260813000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 260813000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6448 82.16% 82.16% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1400 17.84% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7848 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66851 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6422 82.15% 82.15% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1395 17.85% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7817 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65935 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66851 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7848 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65935 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7817 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7848 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74699 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7817 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 73752 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24795366 # DTB read hits -system.cpu.dtb.read_misses 59924 # DTB read misses -system.cpu.dtb.write_hits 19459513 # DTB write hits -system.cpu.dtb.write_misses 6927 # DTB write misses +system.cpu.dtb.read_hits 24760096 # DTB read hits +system.cpu.dtb.read_misses 58949 # DTB read misses +system.cpu.dtb.write_hits 19444061 # DTB write hits +system.cpu.dtb.write_misses 6986 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4353 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1315 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1793 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 1337 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1780 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 738 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24855290 # DTB read accesses -system.cpu.dtb.write_accesses 19466440 # DTB write accesses +system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24819045 # DTB read accesses +system.cpu.dtb.write_accesses 19451047 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44254879 # DTB hits -system.cpu.dtb.misses 66851 # DTB misses -system.cpu.dtb.accesses 44321730 # DTB accesses +system.cpu.dtb.hits 44204157 # DTB hits +system.cpu.dtb.misses 65935 # DTB misses +system.cpu.dtb.accesses 44270092 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -449,37 +450,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5476 # Table walker walks requested -system.cpu.itb.walker.walksShort 5476 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5156 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5476 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5476 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5476 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3185 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12111.930926 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10073.036735 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7077.069157 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1309 41.10% 41.10% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1163 36.51% 77.61% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 712 22.35% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5452 # Table walker walks requested +system.cpu.itb.walker.walksShort 5452 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 318 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5134 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5452 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5452 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5452 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12119.032663 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10076.122020 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7085.501487 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1309 41.11% 41.11% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1160 36.43% 77.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 714 22.42% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3185 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 260408500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 260408500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 260408500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2875 90.27% 90.27% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.73% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3185 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2874 90.26% 90.26% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5476 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5476 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5452 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5452 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3185 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3185 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8661 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57644793 # ITB inst hits -system.cpu.itb.inst_misses 5476 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8636 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57598025 # ITB inst hits +system.cpu.itb.inst_misses 5452 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -488,274 +489,274 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2975 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8375 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57650269 # ITB inst accesses -system.cpu.itb.hits 57644793 # DTB hits -system.cpu.itb.misses 5476 # DTB misses -system.cpu.itb.accesses 57650269 # DTB accesses -system.cpu.numCycles 315472495 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57603477 # ITB inst accesses +system.cpu.itb.hits 57598025 # DTB hits +system.cpu.itb.misses 5452 # DTB misses +system.cpu.itb.accesses 57603477 # DTB accesses +system.cpu.numCycles 315393196 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112177181 # Number of instructions committed -system.cpu.committedOps 135636113 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7815514 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112040950 # Number of instructions committed +system.cpu.committedOps 135468925 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7774524 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5389884731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.812270 # CPI: cycles per instruction -system.cpu.ipc 0.355585 # IPC: instructions per cycle +system.cpu.quiesceCycles 5389977386 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.814981 # CPI: cycles per instruction +system.cpu.ipc 0.355242 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.tickCycles 227521960 # Number of cycles that the object actually ticked -system.cpu.idleCycles 87950535 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 843739 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.948229 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42652951 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 844251 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.521647 # Average number of references to valid blocks. +system.cpu.tickCycles 227419103 # Number of cycles that the object actually ticked +system.cpu.idleCycles 87974093 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 843754 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.948230 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42602633 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 844266 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.461150 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 310642500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.948229 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.948230 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999899 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999899 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176384491 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176384491 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23097762 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23097762 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18292469 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18292469 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356103 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356103 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460142 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460142 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41390231 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41390231 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41746334 # number of overall hits -system.cpu.dcache.overall_hits::total 41746334 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 493938 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 493938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 548534 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 548534 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 170153 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 170153 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22409 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22409 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176183318 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176183318 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23061882 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23061882 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18277764 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18277764 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356325 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356325 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443565 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443565 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460145 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460145 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41339646 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41339646 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41695971 # number of overall hits +system.cpu.dcache.overall_hits::total 41695971 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 494235 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 494235 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 548281 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 548281 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 170165 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 170165 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22392 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22392 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1042472 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1042472 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1212625 # number of overall misses -system.cpu.dcache.overall_misses::total 1212625 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7285426000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7285426000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23290524980 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23290524980 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 282897500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 282897500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30575950980 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30575950980 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30575950980 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30575950980 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23591700 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23591700 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18841003 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18841003 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526256 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526256 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460144 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460144 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42432703 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42432703 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42958959 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42958959 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020937 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020937 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029114 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029114 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323327 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.323327 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048093 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048093 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 1042516 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1042516 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1212681 # number of overall misses +system.cpu.dcache.overall_misses::total 1212681 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7291153500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7291153500 # number of ReadReq miss cycles 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+system.cpu.dcache.ReadReq_accesses::cpu.data 23556117 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23556117 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18826045 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18826045 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526490 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526490 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465957 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465957 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460147 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460147 # number of StoreCondReq accesses(hits+misses) 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-system.cpu.dcache.WriteReq_avg_miss_latency::total 42459.583143 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12624.280423 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12624.280423 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29330.237148 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29330.237148 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25214.679707 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25214.679707 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 276 # number of cycles access was blocked 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31128 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5919321500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5919321500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12456778000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12456778000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1615525000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1615525000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109204500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109204500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18376099500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18376099500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19991624500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19991624500 # number of overall MSHR miss cycles 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# number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1618736500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109455500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109455500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18372678000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18372678000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19991414500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19991414500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5909069000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5909069000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4568816000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4568816000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10477885000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10477885000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017763 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017763 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015867 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015867 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231313 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231313 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017665 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017665 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016901 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019527 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019527 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14149.107333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14149.107333 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41686.281465 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41686.281465 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13274.323558 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13274.323558 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13262.630556 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13262.630556 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25622.894691 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25622.894691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23831.384897 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23831.384897 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189832.594449 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189832.594449 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165637.983541 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165637.983541 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178465.730442 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178465.730442 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016921 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016921 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019551 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14154.610570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14154.610570 # average ReadReq mshr miss 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latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25619.802880 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23830.168719 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23830.168719 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189831.309432 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189831.309432 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165638.835515 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165638.835515 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178465.449405 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 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2894929 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2894929 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2894929 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2894929 # number of overall misses -system.cpu.icache.overall_misses::total 2894929 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39235778500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39235778500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39235778500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39235778500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39235778500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39235778500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57635949 # 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# miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13553.278336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13553.278336 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13553.278336 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13553.278336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13553.278336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13553.278336 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60485733 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60485733 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54692690 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54692690 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54692690 # number of demand (read+write) hits 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miss cycles +system.cpu.icache.demand_miss_latency::total 39250501500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39250501500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39250501500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57589212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57589212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57589212 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57589212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57589212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57589212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050296 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050296 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050296 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050296 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050296 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050296 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13550.907433 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13550.907433 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13550.907433 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13550.907433 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13550.907433 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13550.907433 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -764,212 +765,212 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2894929 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2894929 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2894929 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2894929 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2894929 # number of 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miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12553.278681 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050296 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050296 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050296 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050296 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050296 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050296 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12550.907778 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12550.907778 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12550.907778 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12550.907778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12550.907778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12550.907778 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77943.748041 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77943.748041 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77943.748041 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77943.748041 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 97027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65057.378732 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7025854 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162288 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 43.292505 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 97004 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65057.313836 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7028000 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162262 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 43.312667 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47465.165488 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 71.060465 # Average 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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20761.322789 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67447.280774 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67447.280774 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69850.857292 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69850.857292 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73229.997874 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73229.997874 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 175500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69850.857292 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68007.646667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68265.930515 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 175500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69850.857292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68007.646667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68265.930515 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.444140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007911 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007911 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025892 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025892 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001796 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000227 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007911 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172458 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044202 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001796 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000227 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007911 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172458 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044202 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79488.188976 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20759.649750 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20759.649750 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67456.611240 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67456.611240 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69598.153886 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69598.153886 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73111.690141 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73111.690141 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69598.153886 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68008.117853 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68232.793738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69598.153886 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68008.117853 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68232.793738 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62416.170479 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177331.341557 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166646.464058 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154135.862669 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154135.862669 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177330.088666 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166645.327661 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154136.841533 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154136.841533 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62416.170479 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.879512 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.847436 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.675121 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.653581 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 134609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3577964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 133644 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3578737 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 824000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2989342 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2833 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 823959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2990642 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2849 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894929 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 548519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2896522 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 548664 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8639925 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2647968 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15065 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160688 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11463646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185478080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98978525 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17732 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284758457 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 194907 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 7812293 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.034587 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.182731 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8644384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2648037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14998 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158879 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11466298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185580160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98978397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 280560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284856765 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 194832 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7814541 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.034451 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.182385 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7542089 96.54% 96.54% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 270204 3.46% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7545321 96.55% 96.55% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 269220 3.45% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7812293 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4534239000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 7814541 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4535355500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4347433988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4349852430 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1312866777 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312899273 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10632499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10586000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89658000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88739000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1249,7 +1250,7 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187463964 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187477706 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) @@ -1258,14 +1259,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.030996 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.030922 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270425383000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.030996 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064437 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064437 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270445541000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.030922 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064433 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064433 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1281,8 +1282,8 @@ system.iocache.overall_misses::realview.ide 234 # system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 29161877 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 29161877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4271869087 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4271869087 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4273547829 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4273547829 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ide 29161877 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 29161877 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 29161877 # number of overall miss cycles @@ -1305,17 +1306,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 124623.405983 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 124623.405983 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117929.248206 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117929.248206 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117975.591569 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117975.591569 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 124623.405983 # average overall miss latency system.iocache.demand_avg_miss_latency::total 124623.405983 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 124623.405983 # average overall miss latency system.iocache.overall_avg_miss_latency::total 124623.405983 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1331,8 +1332,8 @@ system.iocache.overall_mshr_misses::realview.ide 234 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 17461877 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 17461877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460669087 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2460669087 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2462347829 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2462347829 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 17461877 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 17461877 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 17461877 # number of overall MSHR miss cycles @@ -1347,66 +1348,66 @@ system.iocache.overall_mshr_miss_rate::realview.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74623.405983 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 74623.405983 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67929.248206 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67929.248206 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67975.591569 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67975.591569 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 74623.405983 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 74623.405983 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 74623.405983 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 74623.405983 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 34319 # Transaction distribution -system.membus.trans_dist::ReadResp 71715 # Transaction distribution +system.membus.trans_dist::ReadResp 71793 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124737 # Transaction distribution -system.membus.trans_dist::CleanEvict 8493 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution +system.membus.trans_dist::Writeback 124709 # Transaction distribution +system.membus.trans_dist::CleanEvict 8498 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4596 # Transaction distribution -system.membus.trans_dist::ReadExReq 129696 # Transaction distribution -system.membus.trans_dist::ReadExResp 129696 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37396 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution +system.membus.trans_dist::ReadExReq 129599 # Transaction distribution +system.membus.trans_dist::ReadExResp 129599 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37474 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455889 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 563451 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 563411 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 672351 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 672311 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16551136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16714909 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16548192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16711965 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19032029 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 507 # Total snoops (count) -system.membus.snoop_fanout::samples 403270 # Request fanout histogram +system.membus.pkt_size::total 19029085 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 506 # Total snoops (count) +system.membus.snoop_fanout::samples 403242 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 403270 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 403242 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 403270 # Request fanout histogram -system.membus.reqLayer0.occupancy 87538000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 403242 # Request fanout histogram +system.membus.reqLayer0.occupancy 87534500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1706000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1700500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 881842801 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 881620222 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 999291900 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 999181641 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64464474 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64440498 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1439,13 +1440,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 4a6c72a8e..04e2b0998 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -352,7 +352,7 @@ type=ExeTracer eventq_index=0 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -693,7 +693,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -803,7 +803,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -891,7 +891,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1306,9 +1306,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index ec3f91aac..7ab7491a1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -201,7 +201,7 @@ instShiftAmt=2 numThreads=1 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -542,7 +542,7 @@ opLat=4 pipelined=true [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -652,7 +652,7 @@ sys=system port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -835,7 +835,7 @@ instShiftAmt=2 numThreads=1 [system.cpu1.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -1176,7 +1176,7 @@ opLat=4 pipelined=true [system.cpu1.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -1286,7 +1286,7 @@ sys=system port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -1399,7 +1399,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1434,7 +1434,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1849,9 +1849,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index e8a4671f3..01c286841 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 10:47:25 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 14 2015 23:52:21 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 6e37ea292..923e006af 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.825406 # Nu sim_ticks 2825405893500 # Number of ticks simulated final_tick 2825405893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99518 # Simulator instruction rate (inst/s) -host_op_rate 120734 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2339943688 # Simulator tick rate (ticks/s) -host_mem_usage 607076 # Number of bytes of host memory used -host_seconds 1207.47 # Real time elapsed on the host +host_inst_rate 67919 # Simulator instruction rate (inst/s) +host_op_rate 82398 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1596954995 # Simulator tick rate (ticks/s) +host_mem_usage 650656 # Number of bytes of host memory used +host_seconds 1769.25 # Real time elapsed on the host sim_insts 120165205 # Number of instructions simulated sim_ops 145782922 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -768,9 +768,9 @@ system.cpu0.iew.iewDispNonSpecInsts 876681 # Nu system.cpu0.iew.iewIQFullEvents 26796 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 125236 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 19035 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 291770 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 291768 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 399939 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 691709 # Number of branch mispredicts detected at execute +system.cpu0.iew.branchMispredicts 691707 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 99697701 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 18022679 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1031168 # Number of squashed instructions skipped in execute @@ -3629,13 +3629,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index d2adfc64d..ff84ed2f5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -201,7 +201,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -542,7 +542,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -652,7 +652,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -740,7 +740,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1155,9 +1155,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 124b0c524..718de535d 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 10:47:25 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:43:21 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index fa71746e2..5e44bb6ce 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -212,7 +212,7 @@ sys=system port=system.toL2Bus.slave[3] [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -1610,7 +1610,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1645,7 +1645,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -2060,9 +2060,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index 392d7b9c9..9e05ec404 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -40,21 +40,19 @@ warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9104, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 11912, Bank: 1 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] +WARNING: Bank is already active! +Command: 0, Timestamp: 9339, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is not active! -Command: 1, Timestamp: 3178, Bank: 4 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7386, Bank: 2 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +Command: 0, Timestamp: 8168, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: Returning zero for read from miscreg pmcr @@ -66,28 +64,27 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[2] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2] -warn: instruction 'mcr bpiall' unimplemented WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: instruction 'mcr bpiall' unimplemented WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -106,6 +103,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 5454319fd..8581849c1 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 10:47:25 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:34:12 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 19db0f3e8..b0310bea3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823474 # Number of seconds simulated -sim_ticks 2823473696000 # Number of ticks simulated -final_tick 2823473696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823417 # Number of seconds simulated +sim_ticks 2823417216000 # Number of ticks simulated +final_tick 2823417216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253388 # Simulator instruction rate (inst/s) -host_op_rate 307362 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5820051646 # Simulator tick rate (ticks/s) -host_mem_usage 579664 # Number of bytes of host memory used -host_seconds 485.13 # Real time elapsed on the host -sim_insts 122925898 # Number of instructions simulated -sim_ops 149109939 # Number of ops (including micro ops) simulated +host_inst_rate 190092 # Simulator instruction rate (inst/s) +host_op_rate 230584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4366555088 # Simulator tick rate (ticks/s) +host_mem_usage 623124 # Number of bytes of host memory used +host_seconds 646.60 # Real time elapsed on the host +sim_insts 122913537 # Number of instructions simulated +sim_ops 149095594 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 537380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3052900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 891264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 373952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2012736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 356480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3623360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 532260 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3026788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 122112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 894784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 379328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2028160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 356352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3635968 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10976712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 537380 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 373952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 356480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1388836 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8247936 # Number of bytes written to this memory +system.physmem.bytes_read::total 10983560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 532260 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 122112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 379328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 356352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1390052 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8264064 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8265460 # Number of bytes written to this memory +system.physmem.bytes_written::total 8281588 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 48221 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5843 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 31449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 66 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5570 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 56615 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 47813 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5927 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 31690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 75 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5568 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 56812 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180484 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 128874 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180591 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133255 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133507 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1081257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 315662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 132444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 712858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 126256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1283299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 188516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1072030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 316915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 134351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 718335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 126213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1287790 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3887662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 132444 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 126256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2921202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3890165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 188516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43250 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 134351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 126213 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 492330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2926972 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6207 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2927408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2921202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2933179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2926972 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1087463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 315662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 132444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 712858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 126256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1283299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 188516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1078237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 316915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 134351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 718335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 126213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1287790 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6815070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 115392 # Number of read requests accepted -system.physmem.writeReqs 70006 # Number of write requests accepted -system.physmem.readBursts 115392 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 70006 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 7377600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 4479552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 7385088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4480384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6823344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 115987 # Number of read requests accepted +system.physmem.writeReqs 70622 # Number of write requests accepted +system.physmem.readBursts 115987 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 70622 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 7416384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 4519488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 7423168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4519808 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16729 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7736 # Per bank write bursts -system.physmem.perBankRdBursts::1 7063 # Per bank write bursts -system.physmem.perBankRdBursts::2 7688 # Per bank write bursts -system.physmem.perBankRdBursts::3 7632 # Per bank write bursts -system.physmem.perBankRdBursts::4 7697 # Per bank write bursts -system.physmem.perBankRdBursts::5 7461 # Per bank write bursts -system.physmem.perBankRdBursts::6 7652 # Per bank write bursts -system.physmem.perBankRdBursts::7 7853 # Per bank write bursts -system.physmem.perBankRdBursts::8 7016 # Per bank write bursts -system.physmem.perBankRdBursts::9 7651 # Per bank write bursts -system.physmem.perBankRdBursts::10 6943 # Per bank write bursts -system.physmem.perBankRdBursts::11 6411 # Per bank write bursts -system.physmem.perBankRdBursts::12 6488 # Per bank write bursts -system.physmem.perBankRdBursts::13 7344 # Per bank write bursts -system.physmem.perBankRdBursts::14 6713 # Per bank write bursts -system.physmem.perBankRdBursts::15 5927 # Per bank write bursts -system.physmem.perBankWrBursts::0 4604 # Per bank write bursts -system.physmem.perBankWrBursts::1 4172 # Per bank write bursts -system.physmem.perBankWrBursts::2 4724 # Per bank write bursts -system.physmem.perBankWrBursts::3 4597 # Per bank write bursts -system.physmem.perBankWrBursts::4 4526 # Per bank write bursts -system.physmem.perBankWrBursts::5 4564 # Per bank write bursts -system.physmem.perBankWrBursts::6 4573 # Per bank write bursts -system.physmem.perBankWrBursts::7 4592 # Per bank write bursts -system.physmem.perBankWrBursts::8 4263 # Per bank write bursts -system.physmem.perBankWrBursts::9 4993 # Per bank write bursts -system.physmem.perBankWrBursts::10 4344 # Per bank write bursts -system.physmem.perBankWrBursts::11 3939 # Per bank write bursts -system.physmem.perBankWrBursts::12 3901 # Per bank write bursts -system.physmem.perBankWrBursts::13 4724 # Per bank write bursts -system.physmem.perBankWrBursts::14 4019 # Per bank write bursts -system.physmem.perBankWrBursts::15 3458 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 16716 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 7738 # Per bank write bursts +system.physmem.perBankRdBursts::1 7157 # Per bank write bursts +system.physmem.perBankRdBursts::2 7568 # Per bank write bursts +system.physmem.perBankRdBursts::3 7635 # Per bank write bursts +system.physmem.perBankRdBursts::4 7727 # Per bank write bursts +system.physmem.perBankRdBursts::5 7298 # Per bank write bursts +system.physmem.perBankRdBursts::6 7875 # Per bank write bursts +system.physmem.perBankRdBursts::7 7810 # Per bank write bursts +system.physmem.perBankRdBursts::8 7237 # Per bank write bursts +system.physmem.perBankRdBursts::9 7597 # Per bank write bursts +system.physmem.perBankRdBursts::10 7159 # Per bank write bursts +system.physmem.perBankRdBursts::11 6221 # Per bank write bursts +system.physmem.perBankRdBursts::12 6467 # Per bank write bursts +system.physmem.perBankRdBursts::13 7007 # Per bank write bursts +system.physmem.perBankRdBursts::14 6960 # Per bank write bursts +system.physmem.perBankRdBursts::15 6425 # Per bank write bursts +system.physmem.perBankWrBursts::0 4628 # Per bank write bursts +system.physmem.perBankWrBursts::1 4274 # Per bank write bursts +system.physmem.perBankWrBursts::2 4625 # Per bank write bursts +system.physmem.perBankWrBursts::3 4563 # Per bank write bursts +system.physmem.perBankWrBursts::4 4564 # Per bank write bursts +system.physmem.perBankWrBursts::5 4431 # Per bank write bursts +system.physmem.perBankWrBursts::6 4784 # Per bank write bursts +system.physmem.perBankWrBursts::7 4577 # Per bank write bursts +system.physmem.perBankWrBursts::8 4485 # Per bank write bursts +system.physmem.perBankWrBursts::9 4954 # Per bank write bursts +system.physmem.perBankWrBursts::10 4488 # Per bank write bursts +system.physmem.perBankWrBursts::11 3709 # Per bank write bursts +system.physmem.perBankWrBursts::12 3882 # Per bank write bursts +system.physmem.perBankWrBursts::13 4478 # Per bank write bursts +system.physmem.perBankWrBursts::14 4241 # Per bank write bursts +system.physmem.perBankWrBursts::15 3934 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2821902889500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2821846409500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 115392 # Read request sizes (log2) +system.physmem.readPktSize::6 115987 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 70006 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 25035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 70622 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 25234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,173 +182,173 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.819355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.296873 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.728623 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15567 39.23% 39.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9452 23.82% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3895 9.82% 72.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2106 5.31% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1684 4.24% 82.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 926 2.33% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 731 1.84% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 606 1.53% 88.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4713 11.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39680 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3702 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 31.134792 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 625.115005 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 3701 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.076368 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.108717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.784807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15715 39.25% 39.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9618 24.02% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3841 9.59% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2194 5.48% 78.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1638 4.09% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 995 2.48% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 706 1.76% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 639 1.60% 88.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4697 11.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40043 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3750 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.898667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 620.943727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 3749 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3702 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3702 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.906807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.729572 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.893119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 6 0.16% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.05% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.05% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 7 0.19% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3319 89.65% 90.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 56 1.51% 91.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 61 1.65% 93.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 52 1.40% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 33 0.89% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 1.46% 97.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.38% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 4 0.11% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.27% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.05% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.03% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.03% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 54 1.46% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.08% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.08% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.14% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.11% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3702 # Writes before turning the bus around for reads -system.physmem.totQLat 1386684000 # Total ticks spent queuing -system.physmem.totMemAccLat 3548090250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 576375000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12029.36 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3750 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3750 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.831200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.732451 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.879160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 7 0.19% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 3 0.08% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.05% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 3 0.08% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3363 89.68% 90.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 40 1.07% 91.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 85 2.27% 93.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 1.17% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 28 0.75% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 63 1.68% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.51% 97.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.03% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.24% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.03% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.13% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.05% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 56 1.49% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.08% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.03% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.13% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3750 # Writes before turning the bus around for reads +system.physmem.totQLat 1369225250 # Total ticks spent queuing +system.physmem.totMemAccLat 3541994000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 579405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11815.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30779.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30565.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.44 # Average write queue length when enqueuing -system.physmem.readRowHits 95329 # Number of row buffer hits during reads -system.physmem.writeRowHits 50259 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes -system.physmem.avgGap 15220783.88 # Average gap between requests -system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 160733160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 87536625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 474099600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 235560960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179692556160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72207385965 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1621122462750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1873980335220 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.505718 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640566607500 # Time in different power states -system.physmem_0.memoryStateTime::REF 91867360000 # Time in different power states +system.physmem.avgWrQLen 16.05 # Average write queue length when enqueuing +system.physmem.readRowHits 95975 # Number of row buffer hits during reads +system.physmem.writeRowHits 50480 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.48 # Row buffer hit rate for writes +system.physmem.avgGap 15121705.86 # Average gap between requests +system.physmem.pageHitRate 78.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 160793640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 87577875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 474302400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 236170080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179688996240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72061472520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1621212124500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1873921437255 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.499929 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640719336250 # Time in different power states +system.physmem_0.memoryStateTime::REF 91865540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18778047250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18574630750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139247640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 75805125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 425045400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 217993680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179692556160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71111774430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616695526250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1868357948685 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.638582 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2642185763250 # Time in different power states -system.physmem_1.memoryStateTime::REF 91867360000 # Time in different power states +system.physmem_1.actEnergy 141931440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 77281875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 429569400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 221428080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179688996240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 71292253815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1621879121250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1873730582100 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.435019 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2641834859500 # Time in different power states +system.physmem_1.memoryStateTime::REF 91865540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17159721000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17456789000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -402,47 +398,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5013 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5013 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5013 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5013 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5013 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 56727642376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.269102 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -15265500874 -26.91% -26.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993143250 126.91% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 56727642376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2853 68.40% 68.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1318 31.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4171 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5013 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 5058 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5058 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5058 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5058 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5058 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 56709099876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.269517 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -15284046374 -26.95% -26.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993146250 126.95% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 56709099876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2875 68.18% 68.18% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1342 31.82% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4217 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5058 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5013 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4171 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5058 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4217 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4171 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9184 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4217 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9275 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12054005 # DTB read hits -system.cpu0.dtb.read_misses 4307 # DTB read misses -system.cpu0.dtb.write_hits 9056572 # DTB write hits -system.cpu0.dtb.write_misses 706 # DTB write misses +system.cpu0.dtb.read_hits 12051362 # DTB read hits +system.cpu0.dtb.read_misses 4340 # DTB read misses +system.cpu0.dtb.write_hits 9035813 # DTB write hits +system.cpu0.dtb.write_misses 718 # DTB write misses system.cpu0.dtb.flush_tlb 172 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 358 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 378 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2897 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2913 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 829 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 825 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 179 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12058312 # DTB read accesses -system.cpu0.dtb.write_accesses 9057278 # DTB write accesses +system.cpu0.dtb.perms_faults 186 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12055702 # DTB read accesses +system.cpu0.dtb.write_accesses 9036531 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21110577 # DTB hits -system.cpu0.dtb.misses 5013 # DTB misses -system.cpu0.dtb.accesses 21115590 # DTB accesses +system.cpu0.dtb.hits 21087175 # DTB hits +system.cpu0.dtb.misses 5058 # DTB misses +system.cpu0.dtb.accesses 21092233 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -472,648 +468,648 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2456 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2456 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2456 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2456 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2456 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 56727642376 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.269104 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -15265627374 -26.91% -26.91% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993269750 126.91% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 56727642376 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1347 75.13% 75.13% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 446 24.87% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1793 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2491 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2491 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2491 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2491 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2491 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 56709099876 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.269519 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -15284164374 -26.95% -26.95% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993264250 126.95% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 56709099876 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1355 75.15% 75.15% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 448 24.85% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1803 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2456 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2456 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2491 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2491 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1793 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1793 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4249 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56651895 # ITB inst hits -system.cpu0.itb.inst_misses 2456 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1803 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1803 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4294 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56612424 # ITB inst hits +system.cpu0.itb.inst_misses 2491 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 172 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 358 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 378 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1793 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1798 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56654351 # ITB inst accesses -system.cpu0.itb.hits 56651895 # DTB hits -system.cpu0.itb.misses 2456 # DTB misses -system.cpu0.itb.accesses 56654351 # DTB accesses -system.cpu0.numCycles 68396174 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56614915 # ITB inst accesses +system.cpu0.itb.hits 56612424 # DTB hits +system.cpu0.itb.misses 2491 # DTB misses +system.cpu0.itb.accesses 56614915 # DTB accesses +system.cpu0.numCycles 68338048 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 55195315 # Number of instructions committed -system.cpu0.committedOps 66856964 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58675450 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4621 # Number of float alu accesses -system.cpu0.num_func_calls 5764530 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7314757 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58675450 # number of integer instructions -system.cpu0.num_fp_insts 4621 # number of float instructions -system.cpu0.num_int_register_reads 108161484 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40950551 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3516 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1106 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 203464939 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 24566154 # number of times the CC registers were written -system.cpu0.num_mem_refs 21694661 # number of memory refs -system.cpu0.num_load_insts 12202966 # Number of load instructions -system.cpu0.num_store_insts 9491695 # Number of store instructions -system.cpu0.num_idle_cycles 64604771.704346 # Number of idle cycles -system.cpu0.num_busy_cycles 3791402.295654 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055433 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944567 # Percentage of idle cycles -system.cpu0.Branches 13394190 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2179 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46192822 67.99% 67.99% # Class of executed instruction -system.cpu0.op_class::IntMult 50582 0.07% 68.06% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3903 0.01% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::MemRead 12202966 17.96% 86.03% # Class of executed instruction -system.cpu0.op_class::MemWrite 9491695 13.97% 100.00% # Class of executed instruction +system.cpu0.committedInsts 55154455 # Number of instructions committed +system.cpu0.committedOps 66797328 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58626360 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4657 # Number of float alu accesses +system.cpu0.num_func_calls 5768343 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7305007 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58626360 # number of integer instructions +system.cpu0.num_fp_insts 4657 # number of float instructions +system.cpu0.num_int_register_reads 108074182 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40930233 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3548 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1110 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 203289315 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 24533313 # number of times the CC registers were written +system.cpu0.num_mem_refs 21670788 # number of memory refs +system.cpu0.num_load_insts 12200183 # Number of load instructions +system.cpu0.num_store_insts 9470605 # Number of store instructions +system.cpu0.num_idle_cycles 64551377.953400 # Number of idle cycles +system.cpu0.num_busy_cycles 3786670.046600 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055411 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944589 # Percentage of idle cycles +system.cpu0.Branches 13387911 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46158472 67.99% 68.00% # Class of executed instruction +system.cpu0.op_class::IntMult 50521 0.07% 68.07% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3911 0.01% 68.08% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.08% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.08% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.08% # Class of executed instruction +system.cpu0.op_class::MemRead 12200183 17.97% 86.05% # Class of executed instruction +system.cpu0.op_class::MemWrite 9470605 13.95% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 67944147 # Class of executed instruction +system.cpu0.op_class::total 67885870 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3087 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 833490 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996671 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 45958483 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 834002 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.105963 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 832545 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996677 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 45907523 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833057 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.107301 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.294893 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.112781 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.133577 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 11.455419 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943935 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.021705 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.022374 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.190626 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.229209 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.101691 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 15.475151 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937872 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.021932 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009964 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.030225 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193340724 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193340724 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11422910 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3593204 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4066922 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6785601 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25868637 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8719261 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2659250 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3172966 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 4237084 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18788561 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177218 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 53891 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 68030 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87717 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 386856 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 215939 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74279 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70102 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 90632 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450952 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216972 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 75904 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 72697 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 95027 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460600 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20142171 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6252454 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7239888 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 11022685 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44657198 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20319389 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6306345 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7307918 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 11110402 # number of overall hits -system.cpu0.dcache.overall_hits::total 45044054 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 171223 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 51523 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 83889 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 223011 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 529646 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 111924 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 33653 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 105580 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1235287 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1486444 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54469 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 16872 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 18830 # number of SoftPFReq misses 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SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86860 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 134533 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 523843 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 219641 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 76598 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 73615 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 99067 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468921 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216972 # number of StoreCondReq accesses(hits+misses) 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rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.032203 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.225732 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.073314 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235097 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.238430 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.216786 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.347989 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.261504 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016855 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.030275 # miss rate for LoadLockedReq accesses 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miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3884752500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 7036068902 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13117689902 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 706453000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1317087500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1529047000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3552587500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 543393000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 982352000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1199505482 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725250482 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1249846000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2299439500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2728552482 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6277837982 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014111 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018160 # mshr miss rate for ReadReq accesses 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for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009139 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.014888 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031110 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010403 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000221 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013425 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017803 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016772 # mshr miss rate for demand accesses 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35922.176329 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46929.420244 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50865.031911 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46987.629724 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12986.466892 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13599.298912 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15455.931307 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14373.790203 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12677.857143 # average LoadLockedReq mshr miss latency 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mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21615.275250 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26332.484901 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29138.601237 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26736.365827 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172389.702294 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194864.255067 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202388.749173 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192949.570932 # average ReadReq mshr uncacheable latency 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LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1112 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 3167 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4956 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 27 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 84504 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 132328 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 210003 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 426835 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 100767 # number of overall MSHR misses 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(read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2177738500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3904773500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 7053289438 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13135801438 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 729067500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1290773000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1548554500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3568395000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 558890500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 964426500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1217476000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2740793000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1287958000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2255199500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2766030500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6309188000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014099 # mshr miss rate for ReadReq accesses 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for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121965 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008934 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.015027 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031836 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010571 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000283 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013410 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017781 # mshr miss rate for demand accesses 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demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054386 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012976 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011887 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045177 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054386 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012976 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.025821 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.025821 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.025821 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 41700 # number of ReadReq MSHR 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+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2642350000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6179717500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 6915980993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 15738048493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2642350000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6179717500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 6915980993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15738048493 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011795 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045434 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054581 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012984 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011795 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045434 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054581 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012984 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011795 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045434 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054581 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012984 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12649.238370 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12875.108860 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12753.171232 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12783.074616 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12649.238370 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12875.108860 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12753.171232 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12783.074616 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12649.238370 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12875.108860 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12753.171232 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12783.074616 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1144,58 +1140,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1944 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1944 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 547 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1397 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1944 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1944 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1944 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1569 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12632.887189 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11014.350507 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6231.121643 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.96% 0.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 406 25.88% 26.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 522 33.27% 60.10% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 230 14.66% 74.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 77 4.91% 79.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 319 20.33% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1569 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 1838 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1838 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 545 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1293 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1838 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1838 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1838 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1481 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10921.336935 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9355.199997 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6102.562917 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 1.01% 1.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 577 38.96% 39.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 520 35.11% 75.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 129 8.71% 83.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 18 1.22% 85.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 222 14.99% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1481 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1032 65.77% 65.77% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 537 34.23% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1569 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1944 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 946 63.88% 63.88% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 535 36.12% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1481 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1838 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1944 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1569 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1838 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1481 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1569 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3513 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1481 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3319 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3796186 # DTB read hits -system.cpu1.dtb.read_misses 1676 # DTB read misses -system.cpu1.dtb.write_hits 2772085 # DTB write hits -system.cpu1.dtb.write_misses 268 # DTB write misses +system.cpu1.dtb.read_hits 3781599 # DTB read hits +system.cpu1.dtb.read_misses 1598 # DTB read misses +system.cpu1.dtb.write_hits 2748070 # DTB write hits +system.cpu1.dtb.write_misses 240 # DTB write misses system.cpu1.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 168 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1249 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1169 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 75 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3797862 # DTB read accesses -system.cpu1.dtb.write_accesses 2772353 # DTB write accesses +system.cpu1.dtb.perms_faults 67 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3783197 # DTB read accesses +system.cpu1.dtb.write_accesses 2748310 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6568271 # DTB hits -system.cpu1.dtb.misses 1944 # DTB misses -system.cpu1.dtb.accesses 6570215 # DTB accesses +system.cpu1.dtb.hits 6529669 # DTB hits +system.cpu1.dtb.misses 1838 # DTB misses +system.cpu1.dtb.accesses 6531507 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1225,128 +1221,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1001 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1001 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walks 906 # Table walker walks requested +system.cpu1.itb.walker.walksShort 906 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 197 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 804 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1001 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1001 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1001 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 723 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12766.251729 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11015.623409 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6540.201330 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 211 29.18% 29.18% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 26.97% 56.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 151 20.89% 77.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 4 0.55% 77.59% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 162 22.41% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 723 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 709 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 906 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 906 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 906 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 660 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11564.393939 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9819.657022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6526.531967 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 251 38.03% 38.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 29.55% 67.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 88 13.33% 80.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 3 0.45% 81.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 123 18.64% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 660 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 526 72.75% 72.75% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 197 27.25% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 723 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 463 70.15% 70.15% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 197 29.85% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 660 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1001 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1001 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 906 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 906 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 723 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 723 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1724 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 17742437 # ITB inst hits -system.cpu1.itb.inst_misses 1001 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 660 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 660 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1566 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 17710907 # ITB inst hits +system.cpu1.itb.inst_misses 906 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 168 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 750 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 687 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 17743438 # ITB inst accesses -system.cpu1.itb.hits 17742437 # DTB hits -system.cpu1.itb.misses 1001 # DTB misses -system.cpu1.itb.accesses 17743438 # DTB accesses -system.cpu1.numCycles 143583360 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 17711813 # ITB inst accesses +system.cpu1.itb.hits 17710907 # DTB hits +system.cpu1.itb.misses 906 # DTB misses +system.cpu1.itb.accesses 17711813 # DTB accesses +system.cpu1.numCycles 143508927 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 17142475 # Number of instructions committed -system.cpu1.committedOps 20690900 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18446976 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1261 # Number of float alu accesses -system.cpu1.num_func_calls 2007420 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2180791 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18446976 # number of integer instructions -system.cpu1.num_fp_insts 1261 # number of float instructions -system.cpu1.num_int_register_reads 34256544 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12938178 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 872 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 390 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 75360742 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7365753 # number of times the CC registers were written -system.cpu1.num_mem_refs 6767228 # number of memory refs -system.cpu1.num_load_insts 3839902 # Number of load instructions -system.cpu1.num_store_insts 2927326 # Number of store instructions -system.cpu1.num_idle_cycles 136602426.841061 # Number of idle cycles -system.cpu1.num_busy_cycles 6980933.158939 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048619 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951381 # Percentage of idle cycles -system.cpu1.Branches 4294582 # Number of branches fetched +system.cpu1.committedInsts 17104818 # Number of instructions committed +system.cpu1.committedOps 20623291 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18381943 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1289 # Number of float alu accesses +system.cpu1.num_func_calls 1997851 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2177891 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18381943 # number of integer instructions +system.cpu1.num_fp_insts 1289 # number of float instructions +system.cpu1.num_int_register_reads 34111926 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12889581 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 904 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 386 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 75094286 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7377149 # number of times the CC registers were written +system.cpu1.num_mem_refs 6727087 # number of memory refs +system.cpu1.num_load_insts 3824966 # Number of load instructions +system.cpu1.num_store_insts 2902121 # Number of store instructions +system.cpu1.num_idle_cycles 136535289.121910 # Number of idle cycles +system.cpu1.num_busy_cycles 6973637.878090 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048594 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951406 # Percentage of idle cycles +system.cpu1.Branches 4285863 # Number of branches fetched system.cpu1.op_class::No_OpClass 47 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14519635 68.15% 68.15% # Class of executed instruction -system.cpu1.op_class::IntMult 16307 0.08% 68.23% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 962 0.00% 68.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.24% # Class of executed instruction -system.cpu1.op_class::MemRead 3839902 18.02% 86.26% # Class of executed instruction -system.cpu1.op_class::MemWrite 2927326 13.74% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14489486 68.24% 68.24% # Class of executed instruction +system.cpu1.op_class::IntMult 16051 0.08% 68.31% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 956 0.00% 68.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.32% # Class of executed instruction +system.cpu1.op_class::MemRead 3824966 18.01% 86.33% # Class of executed instruction +system.cpu1.op_class::MemWrite 2902121 13.67% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21304179 # Class of executed instruction +system.cpu1.op_class::total 21233627 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 5611894 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2863788 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 506095 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3300567 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2344817 # Number of BTB hits +system.cpu2.branchPred.lookups 5616381 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2865516 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 500930 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3264186 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2338379 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.042854 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1575596 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 331093 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.637431 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1579826 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 329229 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1376,56 +1372,56 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 12465 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 12465 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7792 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4673 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 12465 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 12465 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 12465 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2089 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 13064.145524 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 11307.663622 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6855.441685 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 538 25.75% 25.75% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1043 49.93% 75.68% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 506 24.22% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2089 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 12496 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 12496 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7848 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4648 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 12496 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 12496 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 12496 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2107 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12567.631704 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10798.757465 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6853.701577 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 615 29.19% 29.19% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1022 48.50% 77.69% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 468 22.21% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2107 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000070000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000070000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000070000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1323 63.33% 63.33% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 766 36.67% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2089 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12465 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 1329 63.08% 63.08% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 778 36.92% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2107 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12496 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12465 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2089 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12496 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2107 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2089 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 14554 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2107 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 14603 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4354485 # DTB read hits -system.cpu2.dtb.read_misses 11147 # DTB read misses -system.cpu2.dtb.write_hits 3379229 # DTB write hits -system.cpu2.dtb.write_misses 1318 # DTB write misses +system.cpu2.dtb.read_hits 4358544 # DTB read hits +system.cpu2.dtb.read_misses 11242 # DTB read misses +system.cpu2.dtb.write_hits 3388369 # DTB write hits +system.cpu2.dtb.write_misses 1254 # DTB write misses system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1531 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 193 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 294 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1540 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 194 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 307 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 117 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4365632 # DTB read accesses -system.cpu2.dtb.write_accesses 3380547 # DTB write accesses +system.cpu2.dtb.perms_faults 126 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4369786 # DTB read accesses +system.cpu2.dtb.write_accesses 3389623 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 7733714 # DTB hits -system.cpu2.dtb.misses 12465 # DTB misses -system.cpu2.dtb.accesses 7746179 # DTB accesses +system.cpu2.dtb.hits 7746913 # DTB hits +system.cpu2.dtb.misses 12496 # DTB misses +system.cpu2.dtb.accesses 7759409 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1455,80 +1451,80 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 1328 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1328 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walks 1368 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1368 # Table walker walks initiated with short descriptors system.cpu2.itb.walker.walksShortTerminationLevel::Level1 246 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1082 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1328 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1328 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1328 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 881 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12986.379115 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 11270.183591 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6464.618437 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 240 27.24% 27.24% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 238 27.01% 54.26% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 191 21.68% 75.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 6 0.68% 76.62% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 206 23.38% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 881 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1122 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1368 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1368 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1368 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 900 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12559.444444 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 10783.610995 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6567.445052 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 280 31.11% 31.11% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 242 26.89% 58.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 171 19.00% 77.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 5 0.56% 77.56% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 202 22.44% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 900 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000055500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000055500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000055500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 640 72.64% 72.64% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 241 27.36% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 881 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 655 72.78% 72.78% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 245 27.22% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 900 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1328 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1328 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1368 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1368 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 881 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 881 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2209 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10575904 # ITB inst hits -system.cpu2.itb.inst_misses 1328 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 900 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 900 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2268 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10566039 # ITB inst hits +system.cpu2.itb.inst_misses 1368 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 923 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 943 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1777 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1761 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10577232 # ITB inst accesses -system.cpu2.itb.hits 10575904 # DTB hits -system.cpu2.itb.misses 1328 # DTB misses -system.cpu2.itb.accesses 10577232 # DTB accesses -system.cpu2.numCycles 1381990575 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10567407 # ITB inst accesses +system.cpu2.itb.hits 10566039 # DTB hits +system.cpu2.itb.misses 1368 # DTB misses +system.cpu2.itb.accesses 10567407 # DTB accesses +system.cpu2.numCycles 1381994110 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 19415856 # Number of instructions committed -system.cpu2.committedOps 23538274 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1407481 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 550 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 4259391923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 71.178452 # CPI: cycles per instruction -system.cpu2.ipc 0.014049 # IPC: instructions per cycle +system.cpu2.committedInsts 19454188 # Number of instructions committed +system.cpu2.committedOps 23590012 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1394518 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 553 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 4259350283 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 71.038386 # CPI: cycles per instruction +system.cpu2.ipc 0.014077 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 41337448 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1340653127 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13659827 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7557018 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 321485 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8617850 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 6480530 # Number of BTB hits +system.cpu2.tickCycles 41318295 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1340675815 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13596196 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7509425 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 305533 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8486163 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 6439399 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 75.198919 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3094736 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16291 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 75.881161 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3090908 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 15400 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1558,88 +1554,90 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 35471 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 35471 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11945 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7769 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 15757 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19714 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 617.099523 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 4045.428418 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-16383 19501 98.92% 98.92% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-32767 152 0.77% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-49151 42 0.21% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walks 33126 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 33126 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11032 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7972 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 14122 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19004 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 831.246053 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 4468.197044 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-16383 18648 98.13% 98.13% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-32767 304 1.60% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-49151 32 0.17% 99.89% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::49152-65535 8 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-81919 7 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-81919 8 0.04% 99.98% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19714 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6425 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 12552.451362 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 10392.470797 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 7297.231216 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-8191 1902 29.60% 29.60% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::8192-16383 3093 48.14% 77.74% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-24575 1290 20.08% 97.82% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::24576-32767 56 0.87% 98.69% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-40959 42 0.65% 99.35% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::40960-49151 37 0.58% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-57343 1 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-90111 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6425 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8701578064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 1.155310 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8749138564 100.55% 100.55% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 32608500 -0.37% 100.17% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 7394500 -0.08% 100.09% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2262500 -0.03% 100.06% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1618000 -0.02% 100.04% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 1153500 -0.01% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 459000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 1335500 -0.02% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 300000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 181000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 108000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 25500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 53500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 12000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-29 19000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 30000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8701578064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1781 71.41% 71.41% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 713 28.59% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2494 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 35471 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkWaitTime::total 19004 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6133 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 11867.275395 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 9714.087610 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 7406.609922 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-8191 2110 34.40% 34.40% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2847 46.42% 80.83% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-24575 1040 16.96% 97.78% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::24576-32767 49 0.80% 98.58% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-40959 40 0.65% 99.23% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::40960-49151 39 0.64% 99.87% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-57343 3 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-90111 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::90112-98303 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 6133 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8716832064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.261873 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::stdev 0.297258 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8763394564 100.53% 100.53% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 31995000 -0.37% 100.17% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 7342000 -0.08% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 3254000 -0.04% 100.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1291000 -0.01% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 970500 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 493000 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 640500 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 281000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 70500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 112500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 18500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 49000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 6500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-29 10500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::30-31 28000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8716832064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1783 70.92% 70.92% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 731 29.08% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2514 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33126 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 35471 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2494 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33126 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2514 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2494 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 37965 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2514 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 35640 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7577935 # DTB read hits -system.cpu3.dtb.read_misses 29413 # DTB read misses -system.cpu3.dtb.write_hits 5839655 # DTB write hits -system.cpu3.dtb.write_misses 6058 # DTB write misses +system.cpu3.dtb.read_hits 7551044 # DTB read hits +system.cpu3.dtb.read_misses 27915 # DTB read misses +system.cpu3.dtb.write_hits 5856516 # DTB write hits +system.cpu3.dtb.write_misses 5211 # DTB write misses system.cpu3.dtb.flush_tlb 158 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 224 # Number of times TLB was flushed by MVA +system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 415 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 739 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 394 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 742 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 327 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7607348 # DTB read accesses -system.cpu3.dtb.write_accesses 5845713 # DTB write accesses +system.cpu3.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7578959 # DTB read accesses +system.cpu3.dtb.write_accesses 5861727 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13417590 # DTB hits -system.cpu3.dtb.misses 35471 # DTB misses -system.cpu3.dtb.accesses 13453061 # DTB accesses +system.cpu3.dtb.hits 13407560 # DTB hits +system.cpu3.dtb.misses 33126 # DTB misses +system.cpu3.dtb.accesses 13440686 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1669,385 +1667,385 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 4217 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4217 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1465 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2667 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 85 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 4132 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1732.090997 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 7203.300582 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-16383 3973 96.15% 96.15% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-32767 122 2.95% 99.10% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-49151 16 0.39% 99.49% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-65535 12 0.29% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-81919 4 0.10% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-98303 2 0.05% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-114687 1 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::114688-131071 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-147455 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 4132 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walks 4167 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4167 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1453 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2641 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 73 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 4094 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1495.114802 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 5985.882126 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 3827 93.48% 93.48% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 124 3.03% 96.51% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 85 2.08% 98.58% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 26 0.64% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 12 0.29% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.15% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 5 0.12% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.10% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 3 0.07% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.05% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 4094 # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkCompletionTime::samples 1265 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 13666.007905 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 11737.085754 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7328.478477 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-4095 21 1.66% 1.66% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::4096-8191 283 22.37% 24.03% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-12287 342 27.04% 51.07% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::12288-16383 308 24.35% 75.42% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-20479 17 1.34% 76.76% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::20480-24575 261 20.63% 97.39% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-28671 6 0.47% 97.87% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::28672-32767 7 0.55% 98.42% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-36863 1 0.08% 98.50% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::36864-40959 7 0.55% 99.05% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-45055 9 0.71% 99.76% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::45056-49151 2 0.16% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::57344-61439 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 13262.450593 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 11104.068636 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7912.964367 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-4095 17 1.34% 1.34% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::4096-8191 362 28.62% 29.96% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-12287 345 27.27% 57.23% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::12288-16383 231 18.26% 75.49% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-20479 10 0.79% 76.28% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::20480-24575 261 20.63% 96.92% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-28671 10 0.79% 97.71% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::28672-32767 6 0.47% 98.18% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-36863 2 0.16% 98.34% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::36864-40959 5 0.40% 98.74% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-45055 9 0.71% 99.45% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::45056-49151 4 0.32% 99.76% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.08% 99.84% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.16% 100.00% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::total 1265 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8974548064 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.863052 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.342327 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -1226005296 13.66% 13.66% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -7750612268 86.36% 100.02% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1421000 -0.02% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 452500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 116500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 31500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::6 48000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8974548064 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 850 72.03% 72.03% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 330 27.97% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1180 # Table walker page sizes translated +system.cpu3.itb.walker.walksPending::samples -4725503768 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.775529 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.415678 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -1058328796 22.40% 22.40% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -3669011472 77.64% 100.04% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1338500 -0.03% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 422000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 76000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -4725503768 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 861 72.23% 72.23% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 331 27.77% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1192 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4217 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4217 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4167 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4167 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1180 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1180 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5397 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9998093 # ITB inst hits -system.cpu3.itb.inst_misses 4217 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1192 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1192 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5359 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9936571 # ITB inst hits +system.cpu3.itb.inst_misses 4167 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.itb.flush_tlb 158 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 224 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1209 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1221 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 709 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 718 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 10002310 # ITB inst accesses -system.cpu3.itb.hits 9998093 # DTB hits -system.cpu3.itb.misses 4217 # DTB misses -system.cpu3.itb.accesses 10002310 # DTB accesses -system.cpu3.numCycles 55588609 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9940738 # ITB inst accesses +system.cpu3.itb.hits 9936571 # DTB hits +system.cpu3.itb.misses 4167 # DTB misses +system.cpu3.itb.accesses 9940738 # DTB accesses +system.cpu3.numCycles 55573485 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20911805 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 54608834 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13659827 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9575266 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32188027 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1609304 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 73500 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 188 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 174621 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 79934 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 246 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9997086 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 214812 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2061 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54233591 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.215961 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.348203 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20863261 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 54294907 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13596196 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9530307 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 32292568 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1579965 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 69120 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 1162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 268 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 137847 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 66642 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 261 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9935560 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 207453 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2022 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54221093 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.209618 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.343030 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39592641 73.00% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1866738 3.44% 76.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1209172 2.23% 78.68% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3694476 6.81% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 961111 1.77% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 647261 1.19% 88.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2977203 5.49% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 646450 1.19% 95.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2638539 4.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39652063 73.13% 73.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1860834 3.43% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1199577 2.21% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3689809 6.81% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 944481 1.74% 87.32% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 637799 1.18% 88.50% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2980778 5.50% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 640190 1.18% 95.18% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2615562 4.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54233591 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.245731 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.982375 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14602129 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 29778773 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 8106369 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 1026636 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 719503 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 1079419 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 86358 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 47749839 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 276699 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 719503 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15137242 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3025598 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21153466 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8589840 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 5607720 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 45799280 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 610 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1145187 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 113658 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 3954911 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 47609045 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 210470711 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 51575848 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3589 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 39452126 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 8156919 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 730493 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 676284 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5731608 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 8102362 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6460033 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1172202 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1643889 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 44018542 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 534103 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41806723 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 56092 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6528844 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14989618 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 58298 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54233591 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.770864 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.468112 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 54221093 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.244653 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.976993 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14541124 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 29923428 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 8020267 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 1031030 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 705051 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 1065595 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 86058 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 47410230 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 276975 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 705051 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15074857 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 2997482 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21287118 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8510425 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 5645953 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 45500627 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 766 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1126128 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 117998 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 4001017 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 47247848 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 209204758 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 51266498 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3571 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 39476281 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7771567 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 731786 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 677453 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5778610 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 8053628 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6456539 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1175060 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1664059 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 43783527 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 535809 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 41699371 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 53091 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6234373 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14300280 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 56558 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 54221093 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.769062 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.467188 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 37808852 69.71% 69.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5406123 9.97% 79.68% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4124283 7.60% 87.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3378417 6.23% 93.52% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1383474 2.55% 96.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 844457 1.56% 97.63% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 890959 1.64% 99.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 261360 0.48% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 135666 0.25% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 37844395 69.80% 69.80% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5386682 9.93% 79.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4110296 7.58% 87.31% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3372256 6.22% 93.53% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1382084 2.55% 96.08% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 838917 1.55% 97.63% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 889664 1.64% 99.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 259968 0.48% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 136831 0.25% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54233591 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54221093 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 64650 10.11% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 286710 44.85% 54.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 287936 45.04% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 63437 9.96% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 290906 45.69% 55.65% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 282359 44.35% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 64 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27827699 66.56% 66.56% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 30281 0.07% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2306 0.01% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7806443 18.67% 85.31% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 6139930 14.69% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 65 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27741162 66.53% 66.53% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 30355 0.07% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2311 0.01% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7771642 18.64% 85.24% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 6153835 14.76% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41806723 # Type of FU issued -system.cpu3.iq.rate 0.752074 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 639296 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015292 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 138534759 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 51105205 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40599791 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 7666 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4221 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3348 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 42441848 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4107 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 178912 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 41699371 # Type of FU issued +system.cpu3.iq.rate 0.750347 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 636702 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015269 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 138301991 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 50577353 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40524265 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 7637 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4163 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3346 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 42331916 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4092 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 178799 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1280236 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1538 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28536 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 657537 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1221804 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1431 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28394 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 619889 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 107166 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 47571 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 105799 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 48648 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 719503 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2584673 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 329572 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 44617850 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 80448 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 8102362 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6460033 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 277261 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 23890 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 299738 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28536 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 153085 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 129623 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 282708 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 41453550 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7664420 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 317790 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 705051 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 2546149 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 337754 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 44384176 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 73225 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 8053628 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6456539 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 278302 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 24620 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 307122 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28394 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 141723 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 123945 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 265668 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 41365560 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7637563 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 300776 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 65205 # number of nop insts executed -system.cpu3.iew.exec_refs 13740951 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7582733 # Number of branches executed -system.cpu3.iew.exec_stores 6076531 # Number of stores executed -system.cpu3.iew.exec_rate 0.745720 # Inst execution rate -system.cpu3.iew.wb_sent 41141473 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40603139 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21356385 # num instructions producing a value -system.cpu3.iew.wb_consumers 37848912 # num instructions consuming a value +system.cpu3.iew.exec_nop 64840 # number of nop insts executed +system.cpu3.iew.exec_refs 13731746 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7566030 # Number of branches executed +system.cpu3.iew.exec_stores 6094183 # Number of stores executed +system.cpu3.iew.exec_rate 0.744340 # Inst execution rate +system.cpu3.iew.wb_sent 41063512 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40527611 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21306307 # num instructions producing a value +system.cpu3.iew.wb_consumers 37726918 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.730422 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.564254 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.729262 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.564751 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 6551591 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 475805 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 236318 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 52873966 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.719843 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.617254 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 6255806 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 479251 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 220583 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 52905057 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.720581 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.620547 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38351228 72.53% 72.53% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6390419 12.09% 84.62% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3217103 6.08% 90.70% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1425073 2.70% 93.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 785450 1.49% 94.88% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 547204 1.03% 95.92% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 964459 1.82% 97.74% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 247730 0.47% 98.21% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 945300 1.79% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38385903 72.56% 72.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6395220 12.09% 84.64% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3197776 6.04% 90.69% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1426680 2.70% 93.39% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 782047 1.48% 94.86% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 543081 1.03% 95.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 967847 1.83% 97.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 251119 0.47% 98.19% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 955384 1.81% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 52873966 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 31209379 # Number of instructions committed -system.cpu3.commit.committedOps 38060928 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 52905057 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 31237505 # Number of instructions committed +system.cpu3.commit.committedOps 38122392 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 12624622 # Number of memory references committed -system.cpu3.commit.loads 6822126 # Number of loads committed -system.cpu3.commit.membars 184951 # Number of memory barriers committed -system.cpu3.commit.branches 7133186 # Number of branches committed +system.cpu3.commit.refs 12668474 # Number of memory references committed +system.cpu3.commit.loads 6831824 # Number of loads committed +system.cpu3.commit.membars 186001 # Number of memory barriers committed +system.cpu3.commit.branches 7139918 # Number of branches committed system.cpu3.commit.fp_insts 3315 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 33210326 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1242319 # Number of function calls committed. +system.cpu3.commit.int_insts 33267854 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1244626 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 25404774 66.75% 66.75% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 29228 0.08% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2304 0.01% 66.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6822126 17.92% 84.75% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5802496 15.25% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 25422255 66.69% 66.69% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 29353 0.08% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2310 0.01% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6831824 17.92% 84.69% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5836650 15.31% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 38060928 # Class of committed instruction -system.cpu3.commit.bw_lim_events 945300 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90970787 # The number of ROB reads -system.cpu3.rob.rob_writes 90587481 # The number of ROB writes -system.cpu3.timesIdled 219785 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1355018 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161755203 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 31172252 # Number of Instructions Simulated -system.cpu3.committedOps 38023801 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.783272 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.783272 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.560767 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.560767 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 45496208 # number of integer regfile reads -system.cpu3.int_regfile_writes 25431004 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14216 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12004 # number of floating regfile writes -system.cpu3.cc_regfile_reads 146184815 # number of cc regfile reads -system.cpu3.cc_regfile_writes 16067235 # number of cc regfile writes -system.cpu3.misc_regfile_reads 75058867 # number of misc regfile reads -system.cpu3.misc_regfile_writes 353976 # number of misc regfile writes +system.cpu3.commit.op_class_0::total 38122392 # Class of committed instruction +system.cpu3.commit.bw_lim_events 955384 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90746167 # The number of ROB reads +system.cpu3.rob.rob_writes 90074886 # The number of ROB writes +system.cpu3.timesIdled 219461 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1352392 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161729815 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 31200076 # Number of Instructions Simulated +system.cpu3.committedOps 38084963 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.781197 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.781197 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.561420 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.561420 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 45423777 # number of integer regfile reads +system.cpu3.int_regfile_writes 25365434 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14212 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12005 # number of floating regfile writes +system.cpu3.cc_regfile_reads 145868338 # number of cc regfile reads +system.cpu3.cc_regfile_writes 16008509 # number of cc regfile writes +system.cpu3.misc_regfile_reads 75068874 # number of misc regfile reads +system.cpu3.misc_regfile_writes 356547 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30152 # Transaction distribution system.iobus.trans_dist::ReadResp 30152 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2102,7 +2100,7 @@ system.iobus.pkt_size_system.bridge.master::total 159093 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 23971000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 24223000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2118,31 +2116,31 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3350000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3354000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 18885000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 18813000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 75000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 72461073 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 72446830 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 50561000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 50749000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.001949 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.001763 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 248566131009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.001949 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062622 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062622 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 248545825009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.001763 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062610 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062610 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2158,8 +2156,8 @@ system.iocache.overall_misses::realview.ide 220 # system.iocache.overall_misses::total 220 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 16046914 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 16046914 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1649931159 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1649931159 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1650232916 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1650232916 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ide 16046914 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 16046914 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 16046914 # number of overall miss cycles @@ -2182,8 +2180,8 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 72940.518182 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 72940.518182 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45548.011236 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 45548.011236 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45556.341542 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 45556.341542 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency system.iocache.demand_avg_miss_latency::total 72940.518182 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency @@ -2208,8 +2206,8 @@ system.iocache.overall_mshr_misses::realview.ide 135 system.iocache.overall_mshr_misses::total 135 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 9296914 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 9296914 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 950731159 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 950731159 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 951032916 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 951032916 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 9296914 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 9296914 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 9296914 # number of overall MSHR miss cycles @@ -2224,390 +2222,376 @@ system.iocache.overall_mshr_miss_rate::realview.ide 0.613636 system.iocache.overall_mshr_miss_rate::total 0.613636 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68866.029630 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68866.029630 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67987.068006 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67987.068006 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68008.646739 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68008.646739 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 101236 # number of replacements -system.l2c.tags.tagsinuse 65107.326464 # Cycle average of tags in use -system.l2c.tags.total_refs 5169585 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166405 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 31.066284 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 79214835000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49083.542399 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902823 # Average occupied blocks per requestor +system.l2c.tags.replacements 101351 # number of replacements +system.l2c.tags.tagsinuse 65107.437503 # Cycle average of tags in use +system.l2c.tags.total_refs 5159062 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166512 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.983124 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 79184308500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48838.010407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902867 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4686.027695 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1888.757570 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 762.533127 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 823.027459 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 21.612176 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006778 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2605.585835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 671.628280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 48.673794 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2617.148912 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1895.879520 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.748955 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4685.718264 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1889.035593 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 795.990767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 850.885557 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 18.207428 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2675.377352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 739.764762 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 57.652959 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2556.556001 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1997.335453 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.745209 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071503 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.028820 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011635 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000330 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.039758 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.010248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.039935 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.028929 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993459 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65117 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 52 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2279 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8100 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54698 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.993607 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45651328 # Number of tag accesses -system.l2c.tags.data_accesses 45651328 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4883 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1737 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 894 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 13247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 21839 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 4721 # number of ReadReq hits -system.l2c.ReadReq_hits::total 50915 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 692577 # number of Writeback hits -system.l2c.Writeback_hits::total 692577 # number of Writeback hits +system.l2c.tags.occ_percent::cpu0.inst 0.071498 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.028824 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.012146 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012983 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000278 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.040823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.011288 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000880 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.039010 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.030477 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993461 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65101 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2291 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8090 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54680 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.993362 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45578118 # Number of tag accesses +system.l2c.tags.data_accesses 45578118 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4244 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1248 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 674 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 13130 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 1192 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 20158 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 4312 # number of ReadReq hits +system.l2c.ReadReq_hits::total 47143 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 690898 # number of Writeback hits +system.l2c.Writeback_hits::total 690898 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits 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cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 421029000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2135480500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 6095500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 401833000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 4141106000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8210309500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 135809000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 966871000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2085500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 421029000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2135480500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 6095500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 401833000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 4141106000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8210309500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 676680000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1207720500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1453053500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3337454000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 521354500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 905601000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1147910000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2574865500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1198034500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2113321500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2600963500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5912319500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.001976 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003707 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.002138 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987069 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985477 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.964844 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.597004 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.259259 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.259259 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.361120 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.534755 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.541443 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.318964 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009134 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012355 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010269 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006786 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035468 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.019554 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.033537 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.017097 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009134 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.141355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.001976 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.216581 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003707 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010269 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.234219 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.041054 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009134 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.141355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.001976 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.216581 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003707 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010269 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.234219 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.041054 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 80211.538462 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 81273.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 81000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.008734 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20768.421053 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20749.662618 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20758.363202 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 35142.857143 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 35142.857143 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67178.417812 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66199.184711 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 71748.945671 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 69397.658530 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71178.721174 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 70999.831366 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72168.283046 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71510.592272 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70474.348366 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72615.986585 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 76724.894345 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74277.111717 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.721174 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67736.513941 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 80211.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70999.831366 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66556.973664 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 81273.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72168.283046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72179.913547 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 70031.128985 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.721174 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67736.513941 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 80211.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70999.831366 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66556.973664 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 81273.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72168.283046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72179.913547 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70031.128985 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161460.272011 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 181776.113787 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 190190.248691 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180647.036536 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159728.707108 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 177048.093842 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 189768.556786 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178463.092598 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160702.146211 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 179719.491453 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 190003.908247 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 179689.374829 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 75602 # Transaction distribution +system.membus.trans_dist::ReadResp 75713 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::Writeback 128874 # Transaction distribution -system.membus.trans_dist::CleanEvict 8637 # Transaction distribution +system.membus.trans_dist::Writeback 129126 # Transaction distribution +system.membus.trans_dist::CleanEvict 8500 # Transaction distribution system.membus.trans_dist::UpgradeReq 4529 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4540 # Transaction distribution -system.membus.trans_dist::ReadExReq 135912 # Transaction distribution -system.membus.trans_dist::ReadExResp 135912 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35488 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4536 # Transaction distribution +system.membus.trans_dist::ReadExReq 135907 # Transaction distribution +system.membus.trans_dist::ReadExResp 135907 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35599 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 587833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480701 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 588153 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109028 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 696861 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697181 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16930428 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17093553 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16953404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17116529 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19415153 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 336 # Total snoops (count) -system.membus.snoop_fanout::samples 417491 # Request fanout histogram +system.membus.pkt_size::total 19438129 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 335 # Total snoops (count) +system.membus.snoop_fanout::samples 417709 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 417491 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 417709 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 417491 # Request fanout histogram -system.membus.reqLayer0.occupancy 56695500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 417709 # Request fanout histogram +system.membus.reqLayer0.occupancy 57005500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 701000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 697500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 501323202 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 504943941 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 664397755 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 667734518 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 25144064 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 25122086 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2922,63 +2894,63 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 112246 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2626935 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 111495 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2623751 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 762585 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2095941 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2795 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296569 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296569 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1977107 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537598 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 761523 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2094648 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2804 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2831 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296447 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296447 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1975500 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 536772 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 13984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5926014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2620361 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26770 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102262 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8675407 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126565496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97893497 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 45160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 182440 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224686593 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 127382 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5875721 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.031320 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.174182 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5920920 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2617534 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26086 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99400 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8663940 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126461880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97725369 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 173572 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224403669 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 129912 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5870347 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.031302 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.174132 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5691691 96.87% 96.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 184030 3.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5686595 96.87% 96.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 183752 3.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5875721 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2190361997 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5870347 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2188688500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 178500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1848817301 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1847107273 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 767245312 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 767774788 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11020987 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10846487 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 48078267 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 47373752 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 07cc062ab..c1c48178d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -204,7 +204,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -587,7 +587,7 @@ opLat=3 pipelined=false [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -1261,7 +1261,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1296,7 +1296,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1711,9 +1711,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index b551fcaf9..ced0bcc1f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -26,7 +26,6 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5] warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] @@ -34,18 +33,18 @@ warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1] -warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[0] -warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3] -warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3] +warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1] +warn: CP14 unimplemented crn[4], opc1[0], crm[12], opc2[1] warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmcr warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] +warn: CP14 unimplemented crn[3], opc1[5], crm[12], opc2[1] warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3] warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3] -warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[2] +warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0] warn: instruction 'mcr bpiall' unimplemented warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -59,7 +58,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index b9bed144d..8b2102f6a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804297 # Number of seconds simulated -sim_ticks 2804296829000 # Number of ticks simulated -final_tick 2804296829000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804117 # Number of seconds simulated +sim_ticks 2804116777000 # Number of ticks simulated +final_tick 2804116777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111219 # Simulator instruction rate (inst/s) -host_op_rate 134991 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2666745991 # Simulator tick rate (ticks/s) -host_mem_usage 581460 # Number of bytes of host memory used -host_seconds 1051.58 # Real time elapsed on the host -sim_insts 116955586 # Number of instructions simulated -sim_ops 141953418 # Number of ops (including micro ops) simulated +host_inst_rate 79056 # Simulator instruction rate (inst/s) +host_op_rate 95953 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1895501031 # Simulator tick rate (ticks/s) +host_mem_usage 624156 # Number of bytes of host memory used +host_seconds 1479.35 # Real time elapsed on the host +sim_insts 116952036 # Number of instructions simulated +sim_ops 141948815 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 4480 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 694336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4949664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 683520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4874120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 698944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4896096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 676224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4916296 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11211752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 694336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 683520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1377856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8431616 # Number of bytes written to this memory +system.physmem.bytes_read::total 11197544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 698944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 676224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1375168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8445824 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8449140 # Number of bytes written to this memory +system.physmem.bytes_written::total 8463348 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 70 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 77857 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 72 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10680 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 76160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 77020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 70 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10566 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 76819 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175704 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131744 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175482 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131966 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136125 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136347 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 1598 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 247597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1765029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 243740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1738090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 249256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1746039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 241154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1753242 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3998062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 247597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 243740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491337 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3006677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3993252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 249256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 241154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490410 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3011937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6247 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3012926 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3006677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3018187 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3011937 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 1598 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 247597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1771275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 243740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1738093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 249256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1752285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 241154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1753245 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7010988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175705 # Number of read requests accepted -system.physmem.writeReqs 136125 # Number of write requests accepted -system.physmem.readBursts 175705 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136125 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11235200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue -system.physmem.bytesWritten 8462208 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11211816 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8449140 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40824 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11564 # Per bank write bursts -system.physmem.perBankRdBursts::1 11591 # Per bank write bursts -system.physmem.perBankRdBursts::2 11445 # Per bank write bursts -system.physmem.perBankRdBursts::3 11009 # Per bank write bursts -system.physmem.perBankRdBursts::4 11560 # Per bank write bursts -system.physmem.perBankRdBursts::5 11263 # Per bank write bursts -system.physmem.perBankRdBursts::6 12057 # Per bank write bursts -system.physmem.perBankRdBursts::7 11817 # Per bank write bursts -system.physmem.perBankRdBursts::8 10124 # Per bank write bursts -system.physmem.perBankRdBursts::9 10528 # Per bank write bursts -system.physmem.perBankRdBursts::10 10442 # Per bank write bursts -system.physmem.perBankRdBursts::11 9442 # Per bank write bursts -system.physmem.perBankRdBursts::12 10178 # Per bank write bursts -system.physmem.perBankRdBursts::13 11257 # Per bank write bursts -system.physmem.perBankRdBursts::14 10875 # Per bank write bursts -system.physmem.perBankRdBursts::15 10398 # Per bank write bursts -system.physmem.perBankWrBursts::0 8593 # Per bank write bursts -system.physmem.perBankWrBursts::1 8838 # Per bank write bursts -system.physmem.perBankWrBursts::2 8913 # Per bank write bursts -system.physmem.perBankWrBursts::3 8377 # Per bank write bursts -system.physmem.perBankWrBursts::4 8541 # Per bank write bursts -system.physmem.perBankWrBursts::5 8325 # Per bank write bursts -system.physmem.perBankWrBursts::6 9064 # Per bank write bursts -system.physmem.perBankWrBursts::7 8810 # Per bank write bursts -system.physmem.perBankWrBursts::8 7663 # Per bank write bursts -system.physmem.perBankWrBursts::9 7908 # Per bank write bursts -system.physmem.perBankWrBursts::10 7816 # Per bank write bursts -system.physmem.perBankWrBursts::11 7099 # Per bank write bursts -system.physmem.perBankWrBursts::12 7741 # Per bank write bursts -system.physmem.perBankWrBursts::13 8641 # Per bank write bursts -system.physmem.perBankWrBursts::14 8211 # Per bank write bursts -system.physmem.perBankWrBursts::15 7682 # Per bank write bursts +system.physmem.bw_total::total 7011438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175483 # Number of read requests accepted +system.physmem.writeReqs 136347 # Number of write requests accepted +system.physmem.readBursts 175483 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136347 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11221120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue +system.physmem.bytesWritten 8475904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11197608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8463348 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3889 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40841 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11242 # Per bank write bursts +system.physmem.perBankRdBursts::1 11247 # Per bank write bursts +system.physmem.perBankRdBursts::2 11589 # Per bank write bursts +system.physmem.perBankRdBursts::3 11122 # Per bank write bursts +system.physmem.perBankRdBursts::4 11335 # Per bank write bursts +system.physmem.perBankRdBursts::5 11409 # Per bank write bursts +system.physmem.perBankRdBursts::6 11590 # Per bank write bursts +system.physmem.perBankRdBursts::7 11844 # Per bank write bursts +system.physmem.perBankRdBursts::8 10538 # Per bank write bursts +system.physmem.perBankRdBursts::9 10661 # Per bank write bursts +system.physmem.perBankRdBursts::10 10504 # Per bank write bursts +system.physmem.perBankRdBursts::11 9563 # Per bank write bursts +system.physmem.perBankRdBursts::12 10483 # Per bank write bursts +system.physmem.perBankRdBursts::13 10932 # Per bank write bursts +system.physmem.perBankRdBursts::14 10755 # Per bank write bursts +system.physmem.perBankRdBursts::15 10516 # Per bank write bursts +system.physmem.perBankWrBursts::0 8424 # Per bank write bursts +system.physmem.perBankWrBursts::1 8579 # Per bank write bursts +system.physmem.perBankWrBursts::2 8987 # Per bank write bursts +system.physmem.perBankWrBursts::3 8481 # Per bank write bursts +system.physmem.perBankWrBursts::4 8341 # Per bank write bursts +system.physmem.perBankWrBursts::5 8592 # Per bank write bursts +system.physmem.perBankWrBursts::6 8708 # Per bank write bursts +system.physmem.perBankWrBursts::7 8869 # Per bank write bursts +system.physmem.perBankWrBursts::8 8028 # Per bank write bursts +system.physmem.perBankWrBursts::9 8030 # Per bank write bursts +system.physmem.perBankWrBursts::10 7878 # Per bank write bursts +system.physmem.perBankWrBursts::11 7235 # Per bank write bursts +system.physmem.perBankWrBursts::12 7993 # Per bank write bursts +system.physmem.perBankWrBursts::13 8331 # Per bank write bursts +system.physmem.perBankWrBursts::14 8147 # Per bank write bursts +system.physmem.perBankWrBursts::15 7813 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 2804296665000 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 2804116613000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175149 # Read request sizes (log2) +system.physmem.readPktSize::6 174927 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131744 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 103856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1726 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131966 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 103653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1700 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -161,182 +161,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 109 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 101 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 85 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 84 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7882 # What write queue length does an incoming req see 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does an incoming req see -system.physmem.wrQLenPdf::40 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 83 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::27 7947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 59 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65040 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.849692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.291679 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.303136 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24533 37.72% 37.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15784 24.27% 61.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6682 10.27% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3695 5.68% 77.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2905 4.47% 82.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1458 2.24% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1174 1.81% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1054 1.62% 88.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7755 11.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65040 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.267993 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 478.078944 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6681 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.152399 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.671137 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.237503 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24321 37.43% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15991 24.61% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6608 10.17% 72.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3730 5.74% 77.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2732 4.20% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1666 2.56% 84.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1104 1.70% 86.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1133 1.74% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7689 11.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64974 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6726 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.057835 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 476.710834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6724 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6683 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.784827 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.157430 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.794900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 18 0.27% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.09% 0.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 6 0.09% 0.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 12 0.18% 0.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5769 86.32% 86.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 120 1.80% 88.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 172 2.57% 91.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 80 1.20% 92.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 71 1.06% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 155 2.32% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 21 0.31% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.21% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.16% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.09% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.03% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 156 2.33% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.04% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.06% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.21% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6683 # Writes before turning the bus around for reads -system.physmem.totQLat 2675585250 # Total ticks spent queuing -system.physmem.totMemAccLat 5967147750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 877750000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15241.16 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33991.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.rdPerTurnAround::total 6726 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6726 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.690158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.212427 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.515810 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 16 0.24% 0.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 4 0.06% 0.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 7 0.10% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 10 0.15% 0.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5748 85.46% 86.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 152 2.26% 88.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 195 2.90% 91.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 73 1.09% 92.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 81 1.20% 93.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 162 2.41% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 28 0.42% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.16% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.25% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.15% 96.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.12% 97.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 154 2.29% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6726 # Writes before turning the bus around for reads +system.physmem.totQLat 2656155250 # Total ticks spent queuing +system.physmem.totMemAccLat 5943592750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 876650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15149.38 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 33899.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.95 # Average write queue length when enqueuing -system.physmem.readRowHits 145103 # Number of row buffer hits during reads -system.physmem.writeRowHits 97628 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.83 # Row buffer hit rate for writes -system.physmem.avgGap 8993030.39 # Average gap between requests -system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 260993880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 142407375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 719979000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 450107280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 183162969600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 78025608810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1614134111250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1876896177195 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.293165 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2685155496500 # Time in different power states -system.physmem_0.memoryStateTime::REF 93641600000 # Time in different power states +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.62 # Average write queue length when enqueuing +system.physmem.readRowHits 144959 # Number of row buffer hits during reads +system.physmem.writeRowHits 97833 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.86 # Row buffer hit rate for writes +system.physmem.avgGap 8992452.98 # Average gap between requests +system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 259035840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 141339000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 712748400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 446996880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 183151272720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 77780216115 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1614241917750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1876733526705 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.277905 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2685339699500 # Time in different power states +system.physmem_0.memoryStateTime::REF 93635360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25499722000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25141656750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 230708520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 125882625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 649303200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 406691280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 183162969600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 76764954915 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1615239948000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1876580458140 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.180581 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2687003305500 # Time in different power states -system.physmem_1.memoryStateTime::REF 93641600000 # Time in different power states +system.physmem_1.actEnergy 232167600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 126678750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654825600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 411188400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 183151272720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 76668937560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1615216723500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1876461794130 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.181000 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2686967028000 # Time in different power states +system.physmem_1.memoryStateTime::REF 93635360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23651154500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23514328250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory @@ -356,15 +349,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26812041 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13971263 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 545954 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 16789639 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12578074 # Number of BTB hits +system.cpu0.branchPred.lookups 26869227 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13991642 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 524467 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16420293 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12603750 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 74.915691 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6641912 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29629 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.757157 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6640393 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 27621 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -395,93 +388,87 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 60251 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 60251 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 19166 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14911 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 26174 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 34077 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 605.672448 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3875.346595 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-16383 33739 99.01% 99.01% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-32767 267 0.78% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-49151 41 0.12% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-65535 11 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-81919 12 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-114687 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::114688-131071 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-147455 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 34077 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12355.685957 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10118.887695 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7958.316755 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-8191 4001 32.38% 32.38% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::8192-16383 5682 45.99% 78.37% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2378 19.25% 97.62% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::24576-32767 80 0.65% 98.27% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-40959 88 0.71% 98.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::40960-49151 103 0.83% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-57343 4 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::73728-81919 1 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-90111 7 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::90112-98303 8 0.06% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 80764749336 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.624014 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.503698 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 80684502836 99.90% 99.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 56898500 0.07% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 12104000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4341500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2388000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1576500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 755000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1408500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 265500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 266500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 51500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 38500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 30000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 29500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 26000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 67000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 80764749336 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3631 69.79% 69.79% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1572 30.21% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5203 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 60251 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 57399 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 57399 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17473 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14797 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 25129 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 32270 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 687.186241 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 4502.840845 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-16383 31894 98.83% 98.83% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-32767 274 0.85% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-49151 54 0.17% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-65535 17 0.05% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-81919 17 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-98303 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-114687 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::114688-131071 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-147455 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 32270 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 12902 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12660.750271 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10400.452854 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8033.389954 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 9915 76.85% 76.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 2761 21.40% 98.25% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 203 1.57% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 6 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-81919 2 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 14 0.11% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 12902 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 76391677040 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.743538 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.460978 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 76311291040 99.89% 99.89% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 56342500 0.07% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 12108500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4568500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2307500 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1375000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 973000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1821000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 435000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 132000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 55000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 49500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 144000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 14500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 8500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 51500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 76391677040 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3747 70.16% 70.16% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1594 29.84% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5341 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 57399 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 60251 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5203 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 57399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5341 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5203 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 65454 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5341 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 62740 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14022096 # DTB read hits -system.cpu0.dtb.read_misses 51656 # DTB read misses -system.cpu0.dtb.write_hits 10360983 # DTB write hits -system.cpu0.dtb.write_misses 8595 # DTB write misses -system.cpu0.dtb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 463 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 14047287 # DTB read hits +system.cpu0.dtb.read_misses 49327 # DTB read misses +system.cpu0.dtb.write_hits 10317828 # DTB write hits +system.cpu0.dtb.write_misses 8072 # DTB write misses +system.cpu0.dtb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 482 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3475 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 881 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1392 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 817 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1439 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 599 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14073752 # DTB read accesses -system.cpu0.dtb.write_accesses 10369578 # DTB write accesses +system.cpu0.dtb.perms_faults 656 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14096614 # DTB read accesses +system.cpu0.dtb.write_accesses 10325900 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24383079 # DTB hits -system.cpu0.dtb.misses 60251 # DTB misses -system.cpu0.dtb.accesses 24443330 # DTB accesses +system.cpu0.dtb.hits 24365115 # DTB hits +system.cpu0.dtb.misses 57399 # DTB misses +system.cpu0.dtb.accesses 24422514 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,806 +498,804 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 8217 # Table walker walks requested -system.cpu0.itb.walker.walksShort 8217 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2960 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5117 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 140 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 8077 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1443.543395 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 6102.235478 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 7600 94.09% 94.09% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 232 2.87% 96.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 133 1.65% 98.61% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 50 0.62% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 22 0.27% 99.50% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 13 0.16% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 11 0.14% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 2 0.02% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-73727 8 0.10% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::81920-90111 4 0.05% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-106495 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 8077 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2488 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13472.467846 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11168.518762 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7984.929111 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 793 31.87% 31.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 981 39.43% 71.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 648 26.05% 97.35% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 24 0.96% 98.31% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 15 0.60% 98.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 24 0.96% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 7905 # Table walker walks requested +system.cpu0.itb.walker.walksShort 7905 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2649 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5113 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 143 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 7762 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1462.316413 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 6006.318105 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 7298 94.02% 94.02% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 191 2.46% 96.48% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 163 2.10% 98.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 55 0.71% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 14 0.18% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 16 0.21% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 11 0.14% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 7 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-73727 3 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::81920-90111 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 7762 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2523 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13374.950456 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11026.619167 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 8136.408829 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 825 32.70% 32.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 999 39.60% 72.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 627 24.85% 97.15% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 25 0.99% 98.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 16 0.63% 98.77% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 27 1.07% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 2 0.08% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2488 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 37746197376 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.883119 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.321811 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 4416616428 11.70% 11.70% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 33326087448 88.29% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2489000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 727000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 244500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 33000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 37746197376 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1794 76.41% 76.41% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 554 23.59% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2348 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 2523 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 33438392080 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.922681 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.267784 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 2590170000 7.75% 7.75% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 30844665580 92.24% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2600500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 732500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 223500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 33438392080 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1818 76.39% 76.39% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 562 23.61% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2380 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8217 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8217 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7905 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7905 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2348 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2348 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 10565 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 20173848 # ITB inst hits -system.cpu0.itb.inst_misses 8217 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2380 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2380 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 10285 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 20120654 # ITB inst hits +system.cpu0.itb.inst_misses 7905 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 463 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 482 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2291 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2326 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 1412 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20182065 # ITB inst accesses -system.cpu0.itb.hits 20173848 # DTB hits -system.cpu0.itb.misses 8217 # DTB misses -system.cpu0.itb.accesses 20182065 # DTB accesses -system.cpu0.numCycles 106431987 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20128559 # ITB inst accesses +system.cpu0.itb.hits 20120654 # DTB hits +system.cpu0.itb.misses 7905 # DTB misses +system.cpu0.itb.accesses 20128559 # DTB accesses +system.cpu0.numCycles 106084335 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39926124 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 104046311 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26812041 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19219986 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61721491 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3201846 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 134355 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 4118 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 472 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 336728 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 143479 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 355 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20172603 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 372165 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3674 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103868008 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.205189 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.307808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39806494 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 103893687 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26869227 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19244143 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61681241 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3154924 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 126092 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 416 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 201724 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 122006 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 398 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20119405 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 359114 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3525 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103520405 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.205881 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.305845 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75224337 72.42% 72.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3826153 3.68% 76.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2403715 2.31% 78.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 7967440 7.67% 86.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1659017 1.60% 87.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1036461 1.00% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6057785 5.83% 94.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1065173 1.03% 95.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4627927 4.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 74908218 72.36% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3833241 3.70% 76.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2379626 2.30% 78.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8018936 7.75% 86.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1633248 1.58% 87.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1022119 0.99% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6115753 5.91% 94.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1028201 0.99% 95.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4581063 4.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103868008 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.251917 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.977585 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27603064 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 57749227 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15599106 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1464170 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1452197 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1874763 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 150759 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 86325331 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 486551 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1452197 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28440398 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6572412 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 43697521 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16217184 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7488032 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 82550644 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 3098 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1081958 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 289974 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5413982 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 85027824 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 380373358 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 92135642 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 6326 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 71200016 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13827808 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1531327 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1437175 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8438984 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14879838 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11477452 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1996170 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2776563 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 79349721 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1058033 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 75951748 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96660 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11354988 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24738171 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 114625 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103868008 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.731233 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.423636 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103520405 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.253282 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.979350 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27459073 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 57640843 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15538578 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1452555 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1429102 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1871474 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 150372 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 86076544 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 485871 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1429102 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28294007 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6612104 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 43619414 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16146294 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7419215 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 82346799 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3179 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1065744 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 299526 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 5341738 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 84890721 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 379205899 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 91831678 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 6335 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 71376559 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13514162 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1526597 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1432651 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8443957 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14885891 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11404400 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1982860 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2750757 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 79215613 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1056336 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 75904646 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 90770 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11089379 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24203913 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 112312 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103520405 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.733234 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.426738 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 73542868 70.80% 70.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10072511 9.70% 80.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7759579 7.47% 87.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6464332 6.22% 94.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2333365 2.25% 96.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1472075 1.42% 97.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1515581 1.46% 99.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 481814 0.46% 99.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 225883 0.22% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73282727 70.79% 70.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10008412 9.67% 80.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7714570 7.45% 87.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6465771 6.25% 94.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2339617 2.26% 96.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1485866 1.44% 97.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1511901 1.46% 99.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 481751 0.47% 99.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 229790 0.22% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103868008 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103520405 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 101947 9.17% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 527360 47.45% 56.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 481989 43.37% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 105175 9.45% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 531702 47.76% 57.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 476475 42.80% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2185 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 50526992 66.53% 66.53% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57691 0.08% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4308 0.01% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14430381 19.00% 85.61% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10930190 14.39% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 50511411 66.55% 66.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57825 0.08% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 5 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4290 0.01% 66.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.63% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14447360 19.03% 85.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10881568 14.34% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 75951748 # Type of FU issued -system.cpu0.iq.rate 0.713618 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1111298 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014632 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 256965506 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 91807957 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 73625831 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 13956 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7486 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6230 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 77053395 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7466 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 363562 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 75904646 # Type of FU issued +system.cpu0.iq.rate 0.715512 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1113353 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014668 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 256519810 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 91406915 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 73615254 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 14010 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7412 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 6126 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 77008290 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7524 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 368125 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2216786 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2550 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 53728 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1148638 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2165393 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54160 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1099887 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 206531 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 94919 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 208534 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 95734 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1452197 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5712747 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 651844 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 80559572 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 134213 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14879838 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11477452 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 551306 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44233 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 595893 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 53728 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 250776 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 220293 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 471069 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 75340518 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14186156 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 551092 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1429102 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5759594 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 639314 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 80435080 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 122511 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14885891 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11404400 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 549713 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 48457 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 578413 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 54160 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 234602 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 214611 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 449213 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 75318249 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14211760 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 529106 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 151818 # number of nop insts executed -system.cpu0.iew.exec_refs 25009470 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14210768 # Number of branches executed -system.cpu0.iew.exec_stores 10823314 # Number of stores executed -system.cpu0.iew.exec_rate 0.707875 # Inst execution rate -system.cpu0.iew.wb_sent 74794094 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 73632061 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 38328256 # num instructions producing a value -system.cpu0.iew.wb_consumers 66642343 # num instructions consuming a value +system.cpu0.iew.exec_nop 163131 # number of nop insts executed +system.cpu0.iew.exec_refs 24990941 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14215836 # Number of branches executed +system.cpu0.iew.exec_stores 10779181 # Number of stores executed +system.cpu0.iew.exec_rate 0.709985 # Inst execution rate +system.cpu0.iew.wb_sent 74778323 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 73621380 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 38389560 # num instructions producing a value +system.cpu0.iew.wb_consumers 66627447 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.691823 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575134 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.693989 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.576182 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11328784 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 943408 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 397191 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 101330688 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.682350 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.572509 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11066735 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 944024 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 376070 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 101026787 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.685770 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.579563 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 74383354 73.41% 73.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12129402 11.97% 85.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6135914 6.06% 91.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2613445 2.58% 94.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1268685 1.25% 95.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 826588 0.82% 96.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1844857 1.82% 97.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 402953 0.40% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1725490 1.70% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 74129277 73.38% 73.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12088684 11.97% 85.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6100635 6.04% 91.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2597407 2.57% 93.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1266923 1.25% 95.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 835295 0.83% 96.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1855576 1.84% 97.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 402562 0.40% 98.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1750428 1.73% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 101330688 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 56867581 # Number of instructions committed -system.cpu0.commit.committedOps 69142978 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 101026787 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 57027520 # Number of instructions committed +system.cpu0.commit.committedOps 69281156 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 22991866 # Number of memory references committed -system.cpu0.commit.loads 12663052 # Number of loads committed -system.cpu0.commit.membars 379145 # Number of memory barriers committed -system.cpu0.commit.branches 13422378 # Number of branches committed -system.cpu0.commit.fp_insts 6158 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 60521589 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2622248 # Number of function calls committed. +system.cpu0.commit.refs 23025011 # Number of memory references committed +system.cpu0.commit.loads 12720498 # Number of loads committed +system.cpu0.commit.membars 379883 # Number of memory barriers committed +system.cpu0.commit.branches 13454174 # Number of branches committed +system.cpu0.commit.fp_insts 6046 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 60620890 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2622879 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 46090829 66.66% 66.66% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55975 0.08% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4308 0.01% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12663052 18.31% 85.06% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10328814 14.94% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 46195742 66.68% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 56117 0.08% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4286 0.01% 66.77% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12720498 18.36% 85.13% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10304513 14.87% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 69142978 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1725490 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 167648310 # The number of ROB reads -system.cpu0.rob.rob_writes 163485257 # The number of ROB writes -system.cpu0.timesIdled 393439 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2563979 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2956083785 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 56777369 # Number of Instructions Simulated -system.cpu0.committedOps 69052766 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.874549 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.874549 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.533462 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.533462 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 82027611 # number of integer regfile reads -system.cpu0.int_regfile_writes 46869593 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16807 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13164 # number of floating regfile writes -system.cpu0.cc_regfile_reads 266520742 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27747679 # number of cc regfile writes -system.cpu0.misc_regfile_reads 144321385 # number of misc regfile reads -system.cpu0.misc_regfile_writes 724502 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 852950 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.982213 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42504025 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 853462 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.801895 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 69281156 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1750428 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 167227208 # The number of ROB reads +system.cpu0.rob.rob_writes 163193530 # The number of ROB writes +system.cpu0.timesIdled 392212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2563930 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2956294180 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 56928934 # Number of Instructions Simulated +system.cpu0.committedOps 69182570 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.863452 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.863452 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.536638 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.536638 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 81967291 # number of integer regfile reads +system.cpu0.int_regfile_writes 46848639 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16893 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13046 # number of floating regfile writes +system.cpu0.cc_regfile_reads 266506484 # number of cc regfile reads +system.cpu0.cc_regfile_writes 27807772 # number of cc regfile writes +system.cpu0.misc_regfile_reads 144531551 # number of misc regfile reads +system.cpu0.misc_regfile_writes 724861 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 854304 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.982090 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42365382 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 854816 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.560820 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 105251500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 187.204537 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 324.777676 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.365634 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.634331 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 186.651423 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 325.330668 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.364554 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.635411 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189817658 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189817658 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12454816 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12866965 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25321781 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7691483 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8218685 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15910168 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178893 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 183845 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 362738 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209855 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236893 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446748 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216102 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243311 # number of StoreCondReq hits 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number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4528693 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2456716 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2255572 # number of overall misses -system.cpu0.dcache.overall_misses::total 4712288 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6076761000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6454165500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 12530926500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84857330299 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 79343865125 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 164201195424 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 181836500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 208543500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 390380000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 611500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 544500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 1156000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 90934091299 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 85798030625 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 176732121924 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 90934091299 # number of overall miss cycles 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demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 22781908 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23525067 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46306975 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032068 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031713 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031888 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.202951 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.174405 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188456 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323679 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.347660 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.336050 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061589 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056079 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058675 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000125 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000140 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000133 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105301 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.092827 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.098965 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107836 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.095880 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.101762 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14726.615096 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15315.425850 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.118942 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43328.555928 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45700.331893 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44443.095908 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13202.388732 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14817.642461 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14018.745287 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22648.148148 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16014.705882 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18950.819672 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38351.014845 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39765.623371 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39024.972972 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37014.490604 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 38038.258422 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37504.524750 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1148125 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 185430 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 52981 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2987 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.670505 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 62.079009 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 189302421 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189302421 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12461175 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12728962 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25190137 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7687590 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8214972 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15902562 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 179184 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 184541 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 363725 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210025 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236354 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 446379 # number of LoadLockedReq hits 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0.016634 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015868 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016267 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014320 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015279 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.221724 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.227419 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224662 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018884 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019580 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019252 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000125 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000140 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000133 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016477 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015205 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015831 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018860 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017747 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018295 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14105.078609 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14436.621154 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14269.610774 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45516.737049 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47349.481818 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46388.988412 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13750.980426 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14332.771641 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14054.778393 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12990.172863 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16814.204314 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15046.787786 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21648.148148 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15014.705882 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17950.819672 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27395.652149 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27712.698962 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27550.324683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25533.186199 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25658.740121 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25595.062527 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190036.603796 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190081.179294 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190057.490282 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148874.133197 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189644.993441 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165775.771353 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169702.789055 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189889.488855 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178649.288498 # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3060881000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3004845500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6065726500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7052803399 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6808261422 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13861064821 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 813215500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 923997500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737213000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 53086000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81449000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 134535000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 541500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 591000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1132500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10113684399 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9813106922 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 19926791321 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10926899899 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10737104422 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21664004321 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3144537000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2771379000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5915916000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2402448877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2170311500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4572760377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5546985877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4941690500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10488676377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016851 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015828 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016335 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016179 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014456 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015302 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222138 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.228143 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225242 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018306 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019584 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018981 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000116 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000160 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000139 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016564 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015236 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015891 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018956 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017816 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018378 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14096.997191 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14447.136627 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14268.302522 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45284.300613 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47202.888514 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46206.783878 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13814.923979 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14282.584165 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14059.785204 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12963.614164 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16601.916021 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14946.672592 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21660 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15153.846154 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17695.312500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27123.525039 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27860.494408 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27481.514666 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25308.982024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25753.577863 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25527.397195 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190289.682300 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189794.480208 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190057.377839 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148970.600670 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189431.046522 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165775.825732 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169881.963647 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189634.694347 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178649.254433 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1944870 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.570452 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39033281 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1945382 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.064584 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9679828500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 227.356025 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 284.214426 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.444055 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.555106 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999161 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1933259 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.562237 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 38860881 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1933771 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.095906 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9655718500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 227.659514 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 283.902722 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.444647 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.554498 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999145 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 145 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43073652 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43073652 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19127800 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19905481 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39033281 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19127800 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19905481 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39033281 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19127800 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19905481 # number of overall hits -system.cpu0.icache.overall_hits::total 39033281 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1044128 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1050765 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2094893 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1044128 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1050765 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2094893 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1044128 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1050765 # number of overall misses -system.cpu0.icache.overall_misses::total 2094893 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14016783986 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14160518990 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28177302976 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14016783986 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14160518990 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28177302976 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14016783986 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14160518990 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28177302976 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 20171928 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20956246 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 41128174 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 20171928 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20956246 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41128174 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 20171928 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20956246 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41128174 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051761 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050141 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050936 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051761 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050141 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050936 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051761 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050141 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050936 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13424.392398 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.390049 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13450.473593 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13424.392398 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.390049 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13450.473593 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13424.392398 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.390049 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13450.473593 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10866 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42875303 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42875303 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19083138 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19777743 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 38860881 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19083138 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19777743 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 38860881 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19083138 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19777743 # number of overall hits +system.cpu0.icache.overall_hits::total 38860881 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1035596 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1044946 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2080542 # number of ReadReq misses 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miss cycles +system.cpu0.icache.demand_miss_latency::total 28016557469 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13933067983 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14083489486 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28016557469 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20118734 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20822689 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 40941423 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20118734 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20822689 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 40941423 # number of demand (read+write) accesses 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accesses +system.cpu0.icache.overall_miss_rate::total 0.050818 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13454.153920 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.719888 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13465.989857 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13454.153920 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13477.719888 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13465.989857 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13454.153920 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13477.719888 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13465.989857 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 11261 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 629 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 589 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.275040 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.118846 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 74230 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 75184 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 149414 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 74230 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 75184 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 149414 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 74230 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 75184 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 149414 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969898 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 975581 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1945479 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 969898 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 975581 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1945479 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 969898 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 975581 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1945479 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 72785 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 73876 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 146661 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 72785 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 73876 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 146661 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 72785 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 73876 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 146661 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 962811 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 971070 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1933881 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 962811 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 971070 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1933881 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 962811 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 971070 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1933881 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 670 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 670 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 670 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 670 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12381694490 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12496898492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 24878592982 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12381694490 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12496898492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 24878592982 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12381694490 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12496898492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 24878592982 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12308964487 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12437182489 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 24746146976 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12308964487 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12437182489 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 24746146976 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12308964487 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12437182489 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 24746146976 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52946500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52946500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52946500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 52946500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048082 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046553 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047303 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048082 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046553 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047303 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048082 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046553 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047303 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12765.975896 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12809.698520 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12787.901068 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12765.975896 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12809.698520 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12787.901068 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12765.975896 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12809.698520 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12787.901068 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047856 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046635 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047235 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047856 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046635 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047235 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047856 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046635 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047235 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12784.403675 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.709526 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12796.106366 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12784.403675 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.709526 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12796.106366 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12784.403675 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.709526 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12796.106366 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79024.626866 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79024.626866 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27779338 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14456404 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 556707 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17586832 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 13077233 # Number of BTB hits +system.cpu1.branchPred.lookups 27575669 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14289271 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 524894 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17274855 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 12959236 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.358094 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6867114 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29983 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 75.017915 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6858393 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 28646 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1340,90 +1325,83 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 59343 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 59343 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20532 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13405 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25406 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33937 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 563.264284 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3642.212390 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-16383 33612 99.04% 99.04% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-32767 250 0.74% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-49151 49 0.14% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-65535 14 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-81919 8 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 57029 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 57029 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18821 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 12862 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 25346 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 31683 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 591.216110 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3688.783466 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 31359 98.98% 98.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 255 0.80% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 48 0.15% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 10 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 7 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33937 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 12361 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12657.592428 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10412.763280 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7705.801044 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 3725 30.14% 30.14% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5842 47.26% 77.40% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2426 19.63% 97.02% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 136 1.10% 98.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 110 0.89% 99.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 110 0.89% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::73728-81919 2 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 12361 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 85582012132 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.698276 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.478879 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 85506656132 99.91% 99.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 54226500 0.06% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 10815500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 3396500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 2104000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1227000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 804500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 1696500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 468000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 271500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 107000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 23500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 101500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 14500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 14000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 85500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 85582012132 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3538 68.22% 68.22% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1648 31.78% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5186 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 59343 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 31683 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 12352 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12478.424547 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10246.973289 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7685.568959 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 3962 32.08% 32.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5577 45.15% 77.23% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2494 20.19% 97.42% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 102 0.83% 98.24% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 90 0.73% 98.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 118 0.96% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 12352 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 89696770428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.667017 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.494297 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 89674974428 99.98% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 14056500 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 3500500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 2366000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 661500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 722500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 410000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 58000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 21000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 89696770428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3380 68.04% 68.04% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1588 31.96% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 4968 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 57029 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 59343 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5186 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 57029 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 4968 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5186 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 64529 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 4968 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 61997 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14473413 # DTB read hits -system.cpu1.dtb.read_misses 50516 # DTB read misses -system.cpu1.dtb.write_hits 10662986 # DTB write hits -system.cpu1.dtb.write_misses 8827 # DTB write misses -system.cpu1.dtb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 454 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14318727 # DTB read hits +system.cpu1.dtb.read_misses 47357 # DTB read misses +system.cpu1.dtb.write_hits 10661439 # DTB write hits +system.cpu1.dtb.write_misses 9672 # DTB write misses +system.cpu1.dtb.flush_tlb 177 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 435 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3428 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 911 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1182 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3458 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 745 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1189 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 534 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14523929 # DTB read accesses -system.cpu1.dtb.write_accesses 10671813 # DTB write accesses +system.cpu1.dtb.perms_faults 539 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14366084 # DTB read accesses +system.cpu1.dtb.write_accesses 10671111 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25136399 # DTB hits -system.cpu1.dtb.misses 59343 # DTB misses -system.cpu1.dtb.accesses 25195742 # DTB accesses +system.cpu1.dtb.hits 24980166 # DTB hits +system.cpu1.dtb.misses 57029 # DTB misses +system.cpu1.dtb.accesses 25037195 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1453,385 +1431,385 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 8383 # Table walker walks requested -system.cpu1.itb.walker.walksShort 8383 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 3253 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4959 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 171 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 8212 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1247.503653 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 5444.991786 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 7787 94.82% 94.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 188 2.29% 97.11% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 140 1.70% 98.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 47 0.57% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 15 0.18% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 15 0.18% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 8 0.10% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 6 0.07% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 4 0.05% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-90111 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 8212 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2522 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13607.454401 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11346.951670 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7824.124854 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 43 1.70% 1.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 713 28.27% 29.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 591 23.43% 53.41% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 450 17.84% 71.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 33 1.31% 72.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 613 24.31% 96.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 0.83% 97.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 20 0.79% 98.49% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 10 0.40% 98.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.12% 99.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 20 0.79% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 3 0.12% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2522 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 25452156488 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.888283 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.315639 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2847537836 11.19% 11.19% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 22601300152 88.80% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2634500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 584500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 99500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 25452156488 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1775 75.50% 75.50% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 576 24.50% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2351 # Table walker page sizes translated +system.cpu1.itb.walker.walks 7307 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7307 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2390 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4761 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 156 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 7151 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1572.647182 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6795.072359 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-8191 6710 93.83% 93.83% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-16383 190 2.66% 96.49% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-24575 127 1.78% 98.27% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-32767 50 0.70% 98.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-40959 21 0.29% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::40960-49151 20 0.28% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-57343 12 0.17% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::57344-65535 7 0.10% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-73727 4 0.06% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::73728-81919 4 0.06% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-90111 1 0.01% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::90112-98303 3 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-106495 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::106496-114687 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 7151 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2506 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 14007.980846 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11793.815638 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 8015.636923 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 694 27.69% 27.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1049 41.86% 69.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 688 27.45% 97.01% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 39 1.56% 98.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 20 0.80% 99.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 13 0.52% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2506 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 33862083580 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.923542 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.266537 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2594238448 7.66% 7.66% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 31264179132 92.33% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2561000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 759000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 256500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 89500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 33862083580 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1782 75.83% 75.83% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 568 24.17% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2350 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 8383 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 8383 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7307 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7307 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2351 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2351 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 10734 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20958158 # ITB inst hits -system.cpu1.itb.inst_misses 8383 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2350 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2350 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 9657 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20824521 # ITB inst hits +system.cpu1.itb.inst_misses 7307 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 454 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 177 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 435 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2298 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2324 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1383 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1310 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20966541 # ITB inst accesses -system.cpu1.itb.hits 20958158 # DTB hits -system.cpu1.itb.misses 8383 # DTB misses -system.cpu1.itb.accesses 20966541 # DTB accesses -system.cpu1.numCycles 108767456 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20831828 # ITB inst accesses +system.cpu1.itb.hits 20824521 # DTB hits +system.cpu1.itb.misses 7307 # DTB misses +system.cpu1.itb.accesses 20831828 # DTB accesses +system.cpu1.numCycles 108440670 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40797494 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108309619 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27779338 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19944347 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 62902331 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3273623 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 135203 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 7501 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 353 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 608716 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 138611 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 328 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20956250 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 381072 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3851 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 106227312 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.226074 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.322776 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40658841 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 107348372 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27575669 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19817629 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 63179196 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3214627 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 116865 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 7302 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 337 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 214773 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 119592 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20822690 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 365691 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3329 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 105904439 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.219564 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.316618 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 76467157 71.98% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3961882 3.73% 75.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2508117 2.36% 78.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8239256 7.76% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1628076 1.53% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1204845 1.13% 88.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6274984 5.91% 94.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1183680 1.11% 95.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4759315 4.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 76345521 72.09% 72.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3953421 3.73% 75.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2478828 2.34% 78.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8244207 7.78% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1577040 1.49% 87.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1177168 1.11% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6267610 5.92% 94.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1171227 1.11% 95.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4689417 4.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 106227312 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.255401 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.995791 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27883552 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 59140248 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15967546 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1750379 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1485269 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 2004727 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 153597 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90349816 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 499958 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1485269 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28837036 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 5092551 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 46434989 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16757814 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7619325 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 86416848 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2460 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1673796 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 189232 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 4958723 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 89422811 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 398213792 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 96413461 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5558 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 75531757 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13891038 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1607608 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1506576 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10031791 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15342800 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11846385 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2170677 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2932432 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 83143036 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157387 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 79677045 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 92227 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 11399767 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25586754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 106787 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 106227312 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.750062 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.431163 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 105904439 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.254293 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.989927 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27742693 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 59209108 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15734012 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1761502 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1456830 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1964004 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 152599 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 89283066 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 495711 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1456830 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28693287 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 4990149 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 46482214 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16541431 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7740224 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 85441153 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 1754 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1703174 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 185824 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 5043602 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 88283625 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 394169118 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 95445176 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5573 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 75350045 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12933564 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1608887 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1508528 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10148655 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15129586 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11812866 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2166416 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2845057 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 82323765 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1155194 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 79175749 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 89458 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10712710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23890163 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 105302 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 105904439 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.747615 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.428343 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74225476 69.87% 69.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10735161 10.11% 79.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8165707 7.69% 87.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6810651 6.41% 94.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2489155 2.34% 96.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1551071 1.46% 97.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1525154 1.44% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 483878 0.46% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 241059 0.23% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74038259 69.91% 69.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10747404 10.15% 80.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8120323 7.67% 87.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6768186 6.39% 94.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2459889 2.32% 96.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1534209 1.45% 97.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1518475 1.43% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 479862 0.45% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 237832 0.22% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 106227312 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 105904439 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 112109 9.87% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 6 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 520489 45.82% 55.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 503315 44.31% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 107820 9.57% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 6 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 518879 46.05% 55.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 500179 44.39% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 152 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 53438266 67.07% 67.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 58943 0.07% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4274 0.01% 67.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 67.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14882536 18.68% 85.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11292868 14.17% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 53114016 67.08% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 58553 0.07% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 2 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4284 0.01% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14709821 18.58% 85.74% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11288919 14.26% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 79677045 # Type of FU issued -system.cpu1.iq.rate 0.732545 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1135919 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014257 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 266797245 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 95743822 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 77316154 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12303 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6570 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5329 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 80806190 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6622 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 349291 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 79175749 # Type of FU issued +system.cpu1.iq.rate 0.730130 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1126884 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014233 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 265459723 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 94235106 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 76889252 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12556 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6622 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5424 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 80295719 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6762 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 344779 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2194104 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2343 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 51353 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1130901 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2039504 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2297 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 51237 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1073925 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 191600 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 108001 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 189496 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 106526 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1485269 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4109384 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 740435 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 84415132 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 132598 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15342800 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11846385 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 585452 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 40704 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 687401 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 51353 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 260478 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 222263 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 482741 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 79065408 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14638962 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 552436 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1456830 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 3996467 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 749020 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 83580457 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 125116 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15129586 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11812866 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 584610 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 40298 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 696432 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 51237 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 238658 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 209145 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 447803 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 78601263 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14483577 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 517602 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 114709 # number of nop insts executed -system.cpu1.iew.exec_refs 25822462 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14738058 # Number of branches executed -system.cpu1.iew.exec_stores 11183500 # Number of stores executed -system.cpu1.iew.exec_rate 0.726922 # Inst execution rate -system.cpu1.iew.wb_sent 78493230 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 77321483 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 40676282 # num instructions producing a value -system.cpu1.iew.wb_consumers 71272745 # num instructions consuming a value +system.cpu1.iew.exec_nop 101498 # number of nop insts executed +system.cpu1.iew.exec_refs 25666157 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14648718 # Number of branches executed +system.cpu1.iew.exec_stores 11182580 # Number of stores executed +system.cpu1.iew.exec_rate 0.724832 # Inst execution rate +system.cpu1.iew.wb_sent 78056908 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 76894676 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 40431219 # num instructions producing a value +system.cpu1.iew.wb_consumers 70987120 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.710888 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.570713 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.709094 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.569557 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11437303 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1050600 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 405128 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103651619 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.703948 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.590010 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10746753 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1049892 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 374374 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103429928 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.704076 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.589371 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 75257268 72.61% 72.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12658548 12.21% 84.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6546278 6.32% 91.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2731593 2.64% 93.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1415647 1.37% 95.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 932934 0.90% 96.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1873819 1.81% 97.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 434966 0.42% 98.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1800566 1.74% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 75071598 72.58% 72.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12660376 12.24% 84.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6524786 6.31% 91.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2717712 2.63% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1422802 1.38% 95.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 934618 0.90% 96.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1880111 1.82% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 428884 0.41% 98.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1789041 1.73% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103651619 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 60242910 # Number of instructions committed -system.cpu1.commit.committedOps 72965345 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103429928 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 60079421 # Number of instructions committed +system.cpu1.commit.committedOps 72822564 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23864180 # Number of memory references committed -system.cpu1.commit.loads 13148696 # Number of loads committed -system.cpu1.commit.membars 435175 # Number of memory barriers committed -system.cpu1.commit.branches 13969261 # Number of branches committed -system.cpu1.commit.fp_insts 5270 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 63961435 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2719031 # Number of function calls committed. +system.cpu1.commit.refs 23829023 # Number of memory references committed +system.cpu1.commit.loads 13090082 # Number of loads committed +system.cpu1.commit.membars 434438 # Number of memory barriers committed +system.cpu1.commit.branches 13936997 # Number of branches committed +system.cpu1.commit.fp_insts 5382 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 63857795 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2718317 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 49039858 67.21% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57036 0.08% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4271 0.01% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13148696 18.02% 85.31% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10715484 14.69% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 48932373 67.19% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 56887 0.08% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4281 0.01% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13090082 17.98% 85.25% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10738941 14.75% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 72965345 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1800566 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 173538824 # The number of ROB reads -system.cpu1.rob.rob_writes 171385524 # The number of ROB writes -system.cpu1.timesIdled 389774 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2540144 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2437281840 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 60178217 # Number of Instructions Simulated -system.cpu1.committedOps 72900652 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.807422 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.807422 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.553274 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.553274 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 85982923 # number of integer regfile reads -system.cpu1.int_regfile_writes 49280931 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16090 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13091 # number of floating regfile writes -system.cpu1.cc_regfile_reads 279167136 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29456801 # number of cc regfile writes -system.cpu1.misc_regfile_reads 148724045 # number of misc regfile reads -system.cpu1.misc_regfile_writes 795207 # number of misc regfile writes +system.cpu1.commit.op_class_0::total 72822564 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1789041 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 172463469 # The number of ROB reads +system.cpu1.rob.rob_writes 169617134 # The number of ROB writes +system.cpu1.timesIdled 388810 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2536231 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2437380839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 60023102 # Number of Instructions Simulated +system.cpu1.committedOps 72766245 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.806649 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.806649 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.553511 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.553511 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 85555118 # number of integer regfile reads +system.cpu1.int_regfile_writes 48994368 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16096 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13216 # number of floating regfile writes +system.cpu1.cc_regfile_reads 277440920 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29218779 # number of cc regfile writes +system.cpu1.misc_regfile_reads 148245272 # number of misc regfile reads +system.cpu1.misc_regfile_writes 794768 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30198 # Transaction distribution system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1926,7 +1904,7 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187534443 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187527447 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) @@ -1935,14 +1913,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 0.981092 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.980586 # Cycle average of tags in use system.iocache.tags.total_refs 29 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000796 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234155624000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.981092 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061318 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061318 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 234074441000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.980586 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061287 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061287 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1958,14 +1936,14 @@ system.iocache.demand_misses::realview.ide 249 # system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30881877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30881877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4272011566 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4272011566 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30881877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30881877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30881877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30881877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 30886877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30886877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4270029570 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4270029570 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30886877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30886877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30886877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30886877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1982,14 +1960,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124023.602410 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124023.602410 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118024.410598 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118024.410598 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124023.602410 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124023.602410 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124023.602410 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124023.602410 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124043.682731 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124043.682731 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117969.653277 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117969.653277 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124043.682731 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124043.682731 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124043.682731 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124043.682731 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2008,14 +1986,14 @@ system.iocache.demand_mshr_misses::realview.ide 249 system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18431877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18431877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2462211566 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2462211566 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18431877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18431877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18431877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18431877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18436877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18436877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460229570 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2460229570 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18436877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18436877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18436877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18436877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999227 # mshr miss rate for WriteLineReq accesses @@ -2024,270 +2002,270 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74023.602410 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74023.602410 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68024.410598 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68024.410598 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74023.602410 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74023.602410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74023.602410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74023.602410 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74043.682731 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74043.682731 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67969.653277 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67969.653277 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74043.682731 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74043.682731 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74043.682731 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74043.682731 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104591 # number of replacements -system.l2c.tags.tagsinuse 65128.853062 # Cycle average of tags in use -system.l2c.tags.total_refs 5158175 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169835 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.371684 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48560.603393 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 44.868379 # Average occupied blocks per requestor +system.l2c.tags.replacements 104376 # number of replacements +system.l2c.tags.tagsinuse 65128.447881 # Cycle average of tags in use +system.l2c.tags.total_refs 5130866 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169621 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.249002 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 71309274500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48546.195919 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 40.752142 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4741.126354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2359.678514 # Average occupied blocks per requestor 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-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000125 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001972 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.001604 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.963327 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.970769 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.966749 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.296296 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.147059 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.213115 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.460440 # mshr miss rate for ReadExReq accesses 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-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010510 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.181238 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001972 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.183486 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.061169 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001927 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000125 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010510 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.181238 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001972 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.183486 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.061169 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5152786000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4627405000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9822720000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002017 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000129 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.002005 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.001663 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.969717 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.970724 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.970181 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.280000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.153846 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.203125 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.458194 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.487607 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472341 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010662 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.010883 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010773 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.024623 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.029530 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002017 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000129 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010662 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.178605 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.002005 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.185240 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061409 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002017 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000129 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010662 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.178605 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.002005 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.185240 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061409 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78921.428571 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 58500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 74776.223776 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20791.298436 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20745.245642 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.032931 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 33062.500000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77978.723404 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20778.682960 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20764.682540 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20772.228321 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 35000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 21000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28423.076923 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73402.215517 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73016.156154 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73212.760281 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71780.857535 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72896.170771 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72351.578594 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76518.083850 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78415.409678 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77562.047673 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28538.461538 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73240.587195 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72817.542073 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73030.532285 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72454.403741 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73139.727453 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72802.049830 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76274.941995 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78483.530560 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77474.425230 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78921.428571 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 58500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71780.857535 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73671.573507 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72896.170771 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73595.211596 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 73483.090475 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72454.403741 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73510.338915 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73139.727453 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73413.759018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 73387.647996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78921.428571 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 58500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71780.857535 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73671.573507 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72896.170771 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73595.211596 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 73483.090475 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72454.403741 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73510.338915 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73139.727453 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73413.759018 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 73387.647996 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177536.392214 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177581.110730 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 175153.520772 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 137239.209858 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178144.468736 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154196.563225 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177789.591528 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177294.445966 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 175153.489323 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 137335.710299 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177930.653749 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154196.798869 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157630.020495 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177828.689470 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 165418.475607 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157809.200049 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177574.158640 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 165418.568229 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 31797 # Transaction distribution -system.membus.trans_dist::ReadResp 68122 # Transaction distribution +system.membus.trans_dist::ReadResp 68110 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::Writeback 131744 # Transaction distribution -system.membus.trans_dist::CleanEvict 9021 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4618 # Transaction distribution +system.membus.trans_dist::Writeback 131966 # Transaction distribution +system.membus.trans_dist::CleanEvict 8584 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4635 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4631 # Transaction distribution -system.membus.trans_dist::ReadExReq 138685 # Transaction distribution -system.membus.trans_dist::ReadExResp 138685 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36326 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4648 # Transaction distribution +system.membus.trans_dist::ReadExReq 138475 # Transaction distribution +system.membus.trans_dist::ReadExResp 138475 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36314 # Transaction distribution system.membus.trans_dist::InvalidateReq 36195 # Transaction distribution system.membus.trans_dist::InvalidateResp 36195 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 474277 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 581847 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 473652 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 581222 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108830 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 690677 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 690052 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) @@ -2519,28 +2497,28 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315264 system.membus.pkt_size_system.iocache.mem_side::total 2315264 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 19824861 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 523 # Total snoops (count) -system.membus.snoop_fanout::samples 416234 # Request fanout histogram +system.membus.snoop_fanout::samples 415806 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 416234 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 415806 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 416234 # Request fanout histogram -system.membus.reqLayer0.occupancy 95824000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 415806 # Request fanout histogram +system.membus.reqLayer0.occupancy 95819000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1684000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1699000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 923050293 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 923516805 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1019598366 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1018756091 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64439557 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64465031 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2573,66 +2551,66 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 154492 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2656868 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 148196 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2639888 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835335 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2054815 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2828 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 61 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2888 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296748 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296748 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1945479 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 556983 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 836438 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2043009 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 64 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2881 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297192 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297192 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1933881 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 557898 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36195 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5795514 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2675972 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42691 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169160 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8683337 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124535936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99845469 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 291320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224738029 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 211435 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5959204 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.050368 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.218703 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5760848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2679672 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 39941 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 161233 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8641694 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123794112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99989277 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 60616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 278484 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224122489 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 209289 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5932182 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.049498 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.216906 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5659051 94.96% 94.96% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 300153 5.04% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5638548 95.05% 95.05% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 293634 4.95% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5959204 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3608244499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5932182 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3595734997 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 246000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 244500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2920237464 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2902818005 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1326853963 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1328890460 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26388950 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24804964 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 96751648 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 92041633 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini index 04d020f53..12d23ceab 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -179,7 +179,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -638,7 +638,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -748,7 +748,7 @@ sys=system port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -909,7 +909,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu1.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -1368,7 +1368,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu1.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -1478,7 +1478,7 @@ sys=system port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -1591,7 +1591,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1626,7 +1626,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -2041,9 +2041,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout index 501ee633b..e5014ea5e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 10:55:42 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 14 2015 23:38:12 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47411962285000 because m5_exit instruction encountered +Exiting @ tick 47482239150000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index d121e108e..683a782fa 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.411962 # Number of seconds simulated -sim_ticks 47411962285000 # Number of ticks simulated -final_tick 47411962285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.482239 # Number of seconds simulated +sim_ticks 47482239150000 # Number of ticks simulated +final_tick 47482239150000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167928 # Simulator instruction rate (inst/s) -host_op_rate 197524 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9366197696 # Simulator tick rate (ticks/s) -host_mem_usage 719564 # Number of bytes of host memory used -host_seconds 5062.03 # Real time elapsed on the host -sim_insts 850056300 # Number of instructions simulated -sim_ops 999871495 # Number of ops (including micro ops) simulated +host_inst_rate 126606 # Simulator instruction rate (inst/s) +host_op_rate 148916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6789587746 # Simulator tick rate (ticks/s) +host_mem_usage 767628 # Number of bytes of host memory used +host_seconds 6993.39 # Real time elapsed on the host +sim_insts 885402765 # Number of instructions simulated +sim_ops 1041431052 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 75328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 71168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7498816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 38111304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10728384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 51264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 47808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2878784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 12174608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 7747264 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 431104 # Number of bytes read from this memory -system.physmem.bytes_read::total 79815832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7498816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2878784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10377600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 62807296 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 88704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 71680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8153920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 42330888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 14734656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 154368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 137408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2906176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 14216400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12693312 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441664 # Number of bytes read from this memory +system.physmem.bytes_read::total 95929176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8153920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2906176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11060096 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 76090688 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 62827880 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 117169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 595502 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 167631 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 801 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 190241 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 121051 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6736 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1247148 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 981364 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 76111272 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 127405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 661433 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 230229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2147 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 45409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 222144 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 198333 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6901 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1498919 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1188917 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 983938 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 158163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 803833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 226280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 60719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 256783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 163403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1683453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 158163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 60719 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 218881 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1324714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1191491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 171726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 891510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 310319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 61206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 299405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 267328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2020317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 171726 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 61206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 232931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1602508 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1325148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1324714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 158163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 804267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 226280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 60719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 256784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 163403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3008602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1247148 # Number of read requests accepted -system.physmem.writeReqs 983938 # Number of write requests accepted -system.physmem.readBursts 1247148 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 983938 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 79775360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 42112 # Total number of bytes read from write queue -system.physmem.bytesWritten 62826240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 79815832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 62827880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 658 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 218244 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 71187 # Per bank write bursts -system.physmem.perBankRdBursts::1 77028 # Per bank write bursts -system.physmem.perBankRdBursts::2 72273 # Per bank write bursts -system.physmem.perBankRdBursts::3 78219 # Per bank write bursts -system.physmem.perBankRdBursts::4 70385 # Per bank write bursts -system.physmem.perBankRdBursts::5 81119 # Per bank write bursts -system.physmem.perBankRdBursts::6 72267 # Per bank write bursts -system.physmem.perBankRdBursts::7 76746 # Per bank write bursts -system.physmem.perBankRdBursts::8 71370 # Per bank write bursts -system.physmem.perBankRdBursts::9 123762 # Per bank write bursts -system.physmem.perBankRdBursts::10 72044 # Per bank write bursts -system.physmem.perBankRdBursts::11 80747 # Per bank write bursts -system.physmem.perBankRdBursts::12 73100 # Per bank write bursts -system.physmem.perBankRdBursts::13 79351 # Per bank write bursts -system.physmem.perBankRdBursts::14 74612 # Per bank write bursts -system.physmem.perBankRdBursts::15 72280 # Per bank write bursts -system.physmem.perBankWrBursts::0 58860 # Per bank write bursts -system.physmem.perBankWrBursts::1 62909 # Per bank write bursts -system.physmem.perBankWrBursts::2 59749 # Per bank write bursts -system.physmem.perBankWrBursts::3 64358 # Per bank write bursts -system.physmem.perBankWrBursts::4 59245 # Per bank write bursts -system.physmem.perBankWrBursts::5 66477 # Per bank write bursts -system.physmem.perBankWrBursts::6 59553 # Per bank write bursts -system.physmem.perBankWrBursts::7 62082 # Per bank write bursts -system.physmem.perBankWrBursts::8 58790 # Per bank write bursts -system.physmem.perBankWrBursts::9 60994 # Per bank write bursts -system.physmem.perBankWrBursts::10 60508 # Per bank write bursts -system.physmem.perBankWrBursts::11 63849 # Per bank write bursts -system.physmem.perBankWrBursts::12 60193 # Per bank write bursts -system.physmem.perBankWrBursts::13 63756 # Per bank write bursts -system.physmem.perBankWrBursts::14 60310 # Per bank write bursts -system.physmem.perBankWrBursts::15 60027 # Per bank write bursts +system.physmem.bw_write::total 1602942 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1602508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 171726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 891943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 310319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 61206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 299405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 267328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3623259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1498919 # Number of read requests accepted +system.physmem.writeReqs 1191491 # Number of write requests accepted +system.physmem.readBursts 1498919 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1191491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 95891200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 39616 # Total number of bytes read from write queue +system.physmem.bytesWritten 76109696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 95929176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 76111272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 619 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 217911 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 89027 # Per bank write bursts +system.physmem.perBankRdBursts::1 94433 # Per bank write bursts +system.physmem.perBankRdBursts::2 86611 # Per bank write bursts +system.physmem.perBankRdBursts::3 92371 # Per bank write bursts +system.physmem.perBankRdBursts::4 85965 # Per bank write bursts +system.physmem.perBankRdBursts::5 91989 # Per bank write bursts +system.physmem.perBankRdBursts::6 84150 # Per bank write bursts +system.physmem.perBankRdBursts::7 94780 # Per bank write bursts +system.physmem.perBankRdBursts::8 85741 # Per bank write bursts +system.physmem.perBankRdBursts::9 143775 # Per bank write bursts +system.physmem.perBankRdBursts::10 89074 # Per bank write bursts +system.physmem.perBankRdBursts::11 90853 # Per bank write bursts +system.physmem.perBankRdBursts::12 89498 # Per bank write bursts +system.physmem.perBankRdBursts::13 91267 # Per bank write bursts +system.physmem.perBankRdBursts::14 94459 # Per bank write bursts +system.physmem.perBankRdBursts::15 94307 # Per bank write bursts +system.physmem.perBankWrBursts::0 73359 # Per bank write bursts +system.physmem.perBankWrBursts::1 78327 # Per bank write bursts +system.physmem.perBankWrBursts::2 72063 # Per bank write bursts +system.physmem.perBankWrBursts::3 77110 # Per bank write bursts +system.physmem.perBankWrBursts::4 71233 # Per bank write bursts +system.physmem.perBankWrBursts::5 76219 # Per bank write bursts +system.physmem.perBankWrBursts::6 70290 # Per bank write bursts +system.physmem.perBankWrBursts::7 78154 # Per bank write bursts +system.physmem.perBankWrBursts::8 70631 # Per bank write bursts +system.physmem.perBankWrBursts::9 75804 # Per bank write bursts +system.physmem.perBankWrBursts::10 71232 # Per bank write bursts +system.physmem.perBankWrBursts::11 74262 # Per bank write bursts +system.physmem.perBankWrBursts::12 72932 # Per bank write bursts +system.physmem.perBankWrBursts::13 74472 # Per bank write bursts +system.physmem.perBankWrBursts::14 77093 # Per bank write bursts +system.physmem.perBankWrBursts::15 76033 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 47411960356500 # Total gap between requests +system.physmem.numWrRetry 28 # Number of times write queue was full causing retry +system.physmem.totGap 47482237279500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1247118 # Read request sizes (log2) +system.physmem.readPktSize::6 1498889 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 981364 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 795503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 313068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 17861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 16010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 11987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1188917 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 923724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 366189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 26369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 23870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -188,150 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 38389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 48185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 52683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 54849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 56160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 63775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 64447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 57038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 86 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 737647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 193.317834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 117.156586 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 253.851861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 435526 59.04% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 146539 19.87% 78.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49058 6.65% 85.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 25178 3.41% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15871 2.15% 91.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10341 1.40% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7959 1.08% 93.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8404 1.14% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 38771 5.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 737647 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 55115 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.615186 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 363.032286 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 55112 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 16928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 19684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 43592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 66422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 68359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 72568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 74023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 77349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 76686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 79204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 77889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 78555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 85240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 78371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 74036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 70191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 84 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 913839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 188.217382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 115.370572 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 246.881339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 545143 59.65% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 181104 19.82% 79.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 60696 6.64% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 30627 3.35% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20207 2.21% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12827 1.40% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9718 1.06% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9868 1.08% 95.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 43649 4.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 913839 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 67807 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.096303 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 333.350943 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 67804 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 55115 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 55115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.811122 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.212895 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.489514 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 52725 95.66% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 682 1.24% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 764 1.39% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 154 0.28% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 76 0.14% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 61 0.11% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 472 0.86% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 111 0.20% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 10 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 8 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 31 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 55115 # Writes before turning the bus around for reads -system.physmem.totQLat 32865022462 # Total ticks spent queuing -system.physmem.totMemAccLat 56236709962 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6232450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26366.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 67807 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 67807 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.538219 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.057457 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.559402 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 64146 94.60% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1206 1.78% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 504 0.74% 97.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 212 0.31% 97.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 312 0.46% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 493 0.73% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 138 0.20% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.05% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 37 0.05% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 40 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 31 0.05% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 23 0.03% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 428 0.63% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 42 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 41 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 38 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 18 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 20 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 67807 # Writes before turning the bus around for reads +system.physmem.totQLat 45254251156 # Total ticks spent queuing +system.physmem.totMemAccLat 73347376156 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7491500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30203.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45116.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.68 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48953.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.02 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.59 # Average write queue length when enqueuing -system.physmem.readRowHits 1009662 # Number of row buffer hits during reads -system.physmem.writeRowHits 480836 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 48.98 # Row buffer hit rate for writes -system.physmem.avgGap 21250619.81 # Average gap between requests -system.physmem.pageHitRate 66.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2808479520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1532404500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4673861400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3196149840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3096718466400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1173181763970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27418066728000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31700177853630 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.611477 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45611956984095 # Time in different power states -system.physmem_0.memoryStateTime::REF 1583189400000 # Time in different power states +system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing +system.physmem.readRowHits 1205783 # Number of row buffer hits during reads +system.physmem.writeRowHits 567891 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.75 # Row buffer hit rate for writes +system.physmem.avgGap 17648699.37 # Average gap between requests +system.physmem.pageHitRate 66.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3440351880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1877176125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5610742800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3866972400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3101308728960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1186805359620 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27448283421000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31751192752785 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.696261 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45662122488643 # Time in different power states +system.physmem_0.memoryStateTime::REF 1585536160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 216810169905 # Time in different power states +system.physmem_0.memoryStateTime::ACT 234575955107 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2768124240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1510385250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5048596800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3165006960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3096718466400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1175060323800 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27416418868500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31700689771950 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.622274 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45609169557313 # Time in different power states -system.physmem_1.memoryStateTime::REF 1583189400000 # Time in different power states +system.physmem_1.actEnergy 3468270960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1892409750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6075934800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3839134320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3101308728960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1190698585875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27444868310250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31752151374915 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.716450 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45656375341719 # Time in different power states +system.physmem_1.memoryStateTime::REF 1585536160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 219597434187 # Time in different power states +system.physmem_1.memoryStateTime::ACT 240323289781 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -362,18 +376,18 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 130279608 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91518189 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6235368 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97695080 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 70156250 # Number of BTB hits +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 141674450 # Number of BP lookups +system.cpu0.branchPred.condPredicted 99862421 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6468001 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 105068912 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 76755781 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.811446 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15568853 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1041049 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.052799 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16951451 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1146227 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -404,61 +418,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 272738 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 272738 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8357 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 77299 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 272738 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 272738 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 272738 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85656 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20319.907537 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18687.643521 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12933.686898 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 84887 99.10% 99.10% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 657 0.77% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 28 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 42 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85656 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 285287 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 285287 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10160 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74871 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 285287 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 285287 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 285287 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85031 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 19876.756712 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18427.446368 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12146.929549 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 81330 95.65% 95.65% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3040 3.58% 99.22% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 313 0.37% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 238 0.28% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 17 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 17 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 85031 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 77299 90.24% 90.24% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8357 9.76% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85656 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 272738 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 74871 88.05% 88.05% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10160 11.95% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85031 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 285287 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 272738 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85656 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 285287 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85031 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85656 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 358394 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85031 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 370318 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83911764 # DTB read hits -system.cpu0.dtb.read_misses 226051 # DTB read misses -system.cpu0.dtb.write_hits 74892635 # DTB write hits -system.cpu0.dtb.write_misses 46687 # DTB write misses +system.cpu0.dtb.read_hits 92463041 # DTB read hits +system.cpu0.dtb.read_misses 237707 # DTB read misses +system.cpu0.dtb.write_hits 80598198 # DTB write hits +system.cpu0.dtb.write_misses 47580 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35474 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1932 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8858 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37525 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1680 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 10312 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11487 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 84137815 # DTB read accesses -system.cpu0.dtb.write_accesses 74939322 # DTB write accesses +system.cpu0.dtb.perms_faults 10309 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 92700748 # DTB read accesses +system.cpu0.dtb.write_accesses 80645778 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 158804399 # DTB hits -system.cpu0.dtb.misses 272738 # DTB misses -system.cpu0.dtb.accesses 159077137 # DTB accesses +system.cpu0.dtb.hits 173061239 # DTB hits +system.cpu0.dtb.misses 285287 # DTB misses +system.cpu0.dtb.accesses 173346526 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -488,190 +507,192 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 68078 # Table walker walks requested -system.cpu0.itb.walker.walksLong 68078 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 722 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61066 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 68078 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 68078 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 68078 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 61788 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 22737.489480 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21008.732396 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 13692.086470 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 57025 92.29% 92.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3907 6.32% 98.61% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 284 0.46% 99.07% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 503 0.81% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 9 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 25 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 62168 # Table walker walks requested +system.cpu0.itb.walker.walksLong 62168 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 557 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49936 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 62168 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 62168 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 62168 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 50493 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 22007.793159 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 20271.994764 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 13773.268921 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 46934 92.95% 92.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2907 5.76% 98.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 206 0.41% 99.12% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 384 0.76% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 9 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 12 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 4 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 61788 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 50493 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61066 98.83% 98.83% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 722 1.17% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 61788 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 49936 98.90% 98.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 557 1.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 50493 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 68078 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 68078 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 62168 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 62168 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61788 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61788 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 129866 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 232943519 # ITB inst hits -system.cpu0.itb.inst_misses 68078 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50493 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50493 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 112661 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 254201587 # ITB inst hits +system.cpu0.itb.inst_misses 62168 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25164 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26890 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 198596 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 207950 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 233011597 # ITB inst accesses -system.cpu0.itb.hits 232943519 # DTB hits -system.cpu0.itb.misses 68078 # DTB misses -system.cpu0.itb.accesses 233011597 # DTB accesses -system.cpu0.numCycles 944358949 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 254263755 # ITB inst accesses +system.cpu0.itb.hits 254201587 # DTB hits +system.cpu0.itb.misses 62168 # DTB misses +system.cpu0.itb.accesses 254263755 # DTB accesses +system.cpu0.numCycles 1026940097 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 433389926 # Number of instructions committed -system.cpu0.committedOps 509312382 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43329563 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4813 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93880363578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.179005 # CPI: cycles per instruction -system.cpu0.ipc 0.458925 # IPC: instructions per cycle +system.cpu0.committedInsts 473675073 # Number of instructions committed +system.cpu0.committedOps 555986446 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 46253045 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4767 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93938653200 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.168026 # CPI: cycles per instruction +system.cpu0.ipc 0.461249 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13422 # number of quiesce instructions executed -system.cpu0.tickCycles 695520331 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 248838618 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5405789 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.914885 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 150600436 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5406301 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.856465 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 15947 # number of quiesce instructions executed +system.cpu0.tickCycles 756887334 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 270052763 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5859905 # number of replacements +system.cpu0.dcache.tags.tagsinuse 507.688861 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 164189310 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5860417 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.016660 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4974406000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.914885 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978349 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978349 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.688861 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991580 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.991580 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 320300004 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 320300004 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77010804 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77010804 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69515704 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69515704 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 254236 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 254236 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 165535 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 165535 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1598340 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1598340 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1577518 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1577518 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 146526508 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 146526508 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 146780744 # number of overall hits -system.cpu0.dcache.overall_hits::total 146780744 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3243116 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3243116 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2266198 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2266198 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 618205 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 618205 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 821296 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 821296 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 155401 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 155401 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 174722 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 174722 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5509314 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3678685500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3678685500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2406500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2406500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 90875265500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 90875265500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 90875265500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 90875265500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80253920 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80253920 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 71781902 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 71781902 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 872441 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 872441 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 986831 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 986831 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1753741 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1753741 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1752240 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1752240 # 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Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 84695912 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 84695912 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 74803438 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 74803438 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 285827 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 285827 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 206325 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 206325 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1857926 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1857926 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1831957 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1831957 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 159499350 # 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number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4164201 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4776692 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4776692 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 30167 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 30167 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29885 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29885 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60052 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60052 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38218904500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38218904500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23577025500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23577025500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13456556000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13456556000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50843266000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50843266000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1513106500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1513106500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3501575000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3501575000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2054500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2054500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61795930000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61795930000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75252486000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 75252486000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5426212000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5426212000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5134567500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5134567500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10560779500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10560779500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035483 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035483 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.702043 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.702043 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.832159 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.832159 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064782 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064782 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099670 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099670 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027390 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027390 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031239 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031239 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13421.373500 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13421.373500 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17907.698775 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17907.698775 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21970.210175 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21970.210175 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61913.377983 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61913.377983 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13318.427075 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.427075 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20049.672192 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20049.672192 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3953843 # number of writebacks +system.cpu0.dcache.writebacks::total 3953843 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 461349 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 461349 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 989528 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 989528 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 101 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43137 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43137 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 40 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 40 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1450877 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1450877 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1450877 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1450877 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3200307 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3200307 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1397575 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1397575 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 654192 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 654192 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 802895 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 802895 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 124081 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 124081 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191161 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 191161 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4597882 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4597882 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5252074 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5252074 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32791 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32791 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32852 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32852 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65643 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65643 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43347515000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43347515000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25679741500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25679741500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14396564000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14396564000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 54417843000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 54417843000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1641270500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1641270500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3869107000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3869107000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2035000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2035000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 69027256500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 69027256500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83423820500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 83423820500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5925160000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5925160000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5714063000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5714063000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11639223000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11639223000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036220 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036220 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018106 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018106 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.691824 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.691824 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.795480 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.795480 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061270 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061270 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.094486 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.094486 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027774 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027774 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031545 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031545 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13544.798983 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13544.798983 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18374.499759 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18374.499759 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22006.634138 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22006.634138 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 67777.035602 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 67777.035602 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13227.411933 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13227.411933 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20240.043733 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20240.043733 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14839.804803 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14839.804803 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15754.100537 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15754.100537 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179872.443398 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179872.443398 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171810.858290 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171810.858290 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175860.579165 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175860.579165 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15012.837759 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15012.837759 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15883.976597 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15883.976597 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180694.702815 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180694.702815 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173933.489590 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173933.489590 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177310.954710 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177310.954710 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9471710 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.926461 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 223265309 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9472222 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 23.570532 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 29829927000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926461 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999856 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 10143465 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.926573 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 243844472 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 10143977 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.038350 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 29838959000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926573 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999857 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 474947313 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 474947313 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 223265309 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 223265309 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 223265309 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 223265309 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 223265309 # number of overall hits -system.cpu0.icache.overall_hits::total 223265309 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9472232 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9472232 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9472232 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9472232 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9472232 # number of overall misses -system.cpu0.icache.overall_misses::total 9472232 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93317915500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 93317915500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 93317915500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 93317915500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 93317915500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 93317915500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 232737541 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 232737541 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 232737541 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 232737541 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 232737541 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 232737541 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040699 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.040699 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040699 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.040699 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040699 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.040699 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9851.734575 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9851.734575 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9851.734575 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9851.734575 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9851.734575 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9851.734575 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 518120904 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 518120904 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 243844472 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 243844472 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 243844472 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 243844472 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 243844472 # number of overall hits +system.cpu0.icache.overall_hits::total 243844472 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 10143987 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 10143987 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 10143987 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 10143987 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 10143987 # number of overall misses +system.cpu0.icache.overall_misses::total 10143987 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100406017500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 100406017500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 100406017500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 100406017500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 100406017500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 100406017500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 253988459 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 253988459 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 253988459 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 253988459 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 253988459 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 253988459 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039939 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039939 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039939 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039939 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039939 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.039939 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9898.082233 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9898.082233 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9898.082233 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9898.082233 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9898.082233 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9898.082233 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -843,256 +864,258 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10143987 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52292 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52292 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88581800000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 88581800000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88581800000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 88581800000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88581800000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 88581800000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95334024500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 95334024500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95334024500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 95334024500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95334024500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 95334024500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040699 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.040699 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.040699 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9351.734628 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9351.734628 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9351.734628 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039939 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039939 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039939 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9398.082283 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9398.082283 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9398.082283 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7001248 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7002240 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 870 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7957449 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7958709 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1099 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 934040 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2602937 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16189.396586 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 26055882 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2619045 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.948619 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 27364878000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6164.786775 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.653187 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.660205 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5461.877118 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3523.510222 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 883.909079 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.376269 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004618 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004862 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.333367 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.215058 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053950 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988122 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1484 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14552 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 652 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 737 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 69 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 1036699 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2852729 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16231.938482 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 28072062 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2868819 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.785233 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 27361359000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6837.547665 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 84.005962 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 92.461189 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5084.590207 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3169.997386 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 963.336073 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.417331 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005127 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005643 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.310339 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.193481 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.058797 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.990719 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1316 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14706 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 30 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 636 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 493 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1133 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5245 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7645 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 403 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.090576 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # 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average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26628.258994 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26628.258994 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 76028.640923 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 76028.640923 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29193.102099 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27056.580674 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29193.102099 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29581.343345 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178383 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26975.398363 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45363.741930 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20262.523814 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20262.523814 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15383.814337 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15383.814337 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 283999.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 283999.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42293.793764 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42293.793764 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24227.493856 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27323.244934 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27323.244934 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 78134.775269 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 78134.775269 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30317.319438 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27943.350118 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30317.319438 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32502.371679 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171868.034607 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 115744.642792 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164309.988288 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164309.988288 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172689.838675 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117792.238167 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166432.743821 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166432.743821 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168106.757477 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128663.671402 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169558.383986 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 131341.548311 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 876246 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14005082 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 29885 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 6885213 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 13979886 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 878417 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 473566 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 319318 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 460407 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1465787 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1113779 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9472232 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5781099 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 926693 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 819709 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28518742 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17480007 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 376075 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1070420 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 47445244 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609569408 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 544120273 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1382192 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3906208 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1158978081 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 10243316 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 41099849 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.261354 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.439372 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 878258 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 15087550 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32852 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 7538926 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 15047066 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 979875 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 473443 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 345382 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 491005 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1529585 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1182209 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10143987 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6286308 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 908183 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 801455 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30533828 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18915495 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 338792 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1107688 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 50895803 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 652561728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 589425738 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1225096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4043800 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1247256362 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 11033818 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 44172113 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.260955 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.439155 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 30358253 73.86% 73.86% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 10741596 26.14% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 32645184 73.90% 73.90% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 11526929 26.10% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 41099849 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 19306972981 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 44172113 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 20686801483 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 182073987 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 184431489 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14288744572 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15296388050 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7674112954 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8393036752 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 203313475 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 185661487 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 582176435 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 602239946 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 125904408 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89122664 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5902634 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 94266188 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 68486701 # Number of BTB hits +system.cpu1.branchPred.lookups 126920633 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90998639 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5685011 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 95306954 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 70103943 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.652456 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15015861 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1004863 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.555958 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14523133 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 944517 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1364,65 +1385,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 261999 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 261999 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7478 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 69980 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 261999 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 261999 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 261999 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 77458 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19301.763536 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17918.383858 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 10994.886931 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 74315 95.94% 95.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2659 3.43% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 247 0.32% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 165 0.21% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 5 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 16 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 10 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 77458 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1501931648 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1501931648 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1501931648 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 69980 90.35% 90.35% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 7478 9.65% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 77458 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261999 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 273163 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 273163 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10101 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83297 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 273163 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 273163 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 273163 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 93398 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20769.759524 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18788.534327 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16072.129923 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 92090 98.60% 98.60% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1102 1.18% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 44 0.05% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 68 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 64 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 93398 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1497259648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1497259648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1497259648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 83297 89.18% 89.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10101 10.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 93398 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 273163 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261999 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77458 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 273163 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93398 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77458 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 339457 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93398 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 366561 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 82663207 # DTB read hits -system.cpu1.dtb.read_misses 218762 # DTB read misses -system.cpu1.dtb.write_hits 71167787 # DTB write hits -system.cpu1.dtb.write_misses 43237 # DTB write misses +system.cpu1.dtb.read_hits 80454143 # DTB read hits +system.cpu1.dtb.read_misses 224980 # DTB read misses +system.cpu1.dtb.write_hits 71458601 # DTB write hits +system.cpu1.dtb.write_misses 48183 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35788 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 902 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6887 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37844 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 998 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7832 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9904 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 82881969 # DTB read accesses -system.cpu1.dtb.write_accesses 71211024 # DTB write accesses +system.cpu1.dtb.perms_faults 11981 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 80679123 # DTB read accesses +system.cpu1.dtb.write_accesses 71506784 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 153830994 # DTB hits -system.cpu1.dtb.misses 261999 # DTB misses -system.cpu1.dtb.accesses 154092993 # DTB accesses +system.cpu1.dtb.hits 151912744 # DTB hits +system.cpu1.dtb.misses 273163 # DTB misses +system.cpu1.dtb.accesses 152185907 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1452,191 +1469,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 59152 # Table walker walks requested -system.cpu1.itb.walker.walksLong 59152 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 461 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48561 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 59152 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 59152 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 59152 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 49022 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21340.612378 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 19735.982166 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 12453.289543 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 45897 93.63% 93.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 2624 5.35% 98.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 160 0.33% 99.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 295 0.60% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 9 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 10 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 49022 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1502514148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1502514148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1502514148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 48561 99.06% 99.06% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 461 0.94% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 49022 # Table walker page sizes translated +system.cpu1.itb.walker.walks 69906 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69906 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 595 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61795 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 69906 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69906 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69906 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 62390 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 23626.751082 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21282.847568 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17788.570372 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 60952 97.70% 97.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1278 2.05% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.13% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 62390 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1498102148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1498102148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1498102148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61795 99.05% 99.05% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 595 0.95% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 62390 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59152 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59152 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69906 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69906 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49022 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49022 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 108174 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 225695696 # ITB inst hits -system.cpu1.itb.inst_misses 59152 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62390 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62390 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 132296 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 226287653 # ITB inst hits +system.cpu1.itb.inst_misses 69906 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25916 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26941 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 201769 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 214530 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 225754848 # ITB inst accesses -system.cpu1.itb.hits 225695696 # DTB hits -system.cpu1.itb.misses 59152 # DTB misses -system.cpu1.itb.accesses 225754848 # DTB accesses -system.cpu1.numCycles 837975509 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 226357559 # ITB inst accesses +system.cpu1.itb.hits 226287653 # DTB hits +system.cpu1.itb.misses 69906 # DTB misses +system.cpu1.itb.accesses 226357559 # DTB accesses +system.cpu1.numCycles 843613035 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 416666374 # Number of instructions committed -system.cpu1.committedOps 490559113 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 42698463 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4659 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93986622085 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.011143 # CPI: cycles per instruction -system.cpu1.ipc 0.497230 # IPC: instructions per cycle +system.cpu1.committedInsts 411727692 # Number of instructions committed +system.cpu1.committedOps 485444606 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 45963671 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5033 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94121734017 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.048959 # CPI: cycles per instruction +system.cpu1.ipc 0.488053 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5009 # number of quiesce instructions executed -system.cpu1.tickCycles 670350336 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 167625173 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 4806043 # number of replacements -system.cpu1.dcache.tags.tagsinuse 444.186980 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 146495712 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4806555 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.478318 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8387638822500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 444.186980 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867553 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.867553 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 309963007 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 309963007 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 75874550 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 75874550 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 66435000 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 66435000 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 232604 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 232604 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 157450 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 157450 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1693988 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1693988 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1671438 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1671438 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 142309550 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 142309550 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 142542154 # number of overall hits -system.cpu1.dcache.overall_hits::total 142542154 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3161753 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3161753 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1996683 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1996683 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 552089 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 552089 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 421817 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 421817 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158395 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 158395 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 179133 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 179133 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5158436 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5158436 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5710525 # number of overall misses -system.cpu1.dcache.overall_misses::total 5710525 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43703345000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 43703345000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 33230827500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 33230827500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 13699084500 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 13699084500 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2222797000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2222797000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3749543500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3749543500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3215500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3215500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 76934172500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 76934172500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 76934172500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 76934172500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 79036303 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 79036303 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 68431683 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 68431683 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 784693 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 784693 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 579267 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 579267 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1852383 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1852383 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1850571 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1850571 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 147467986 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 147467986 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 148252679 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 148252679 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040004 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040004 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029178 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029178 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.703573 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.703573 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.728191 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.728191 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.085509 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.085509 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096799 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096799 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034980 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034980 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038519 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.038519 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13822.504478 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13822.504478 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16643.016192 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16643.016192 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32476.368899 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 32476.368899 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14033.252312 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14033.252312 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20931.617848 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20931.617848 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5855 # number of quiesce instructions executed +system.cpu1.tickCycles 670689322 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 172923713 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4998697 # number of replacements +system.cpu1.dcache.tags.tagsinuse 442.736384 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 144280355 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4999208 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.860643 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8387679361000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.736384 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.864720 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.864720 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 306336541 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 306336541 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73634827 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73634827 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 66559153 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 66559153 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 217159 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 217159 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 114949 # 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number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634590 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 634590 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446274 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 446274 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 155480 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 155480 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187648 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 187648 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5372476 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5372476 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6007066 # number of overall misses +system.cpu1.dcache.overall_misses::total 6007066 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46997405500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 46997405500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36924614000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 36924614000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 13123924500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 13123924500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2384254000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2384254000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3955578000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3955578000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3296000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3296000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 83922019500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 83922019500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 83922019500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 83922019500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 76804419 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 76804419 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 68762037 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 68762037 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 851749 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 851749 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 561223 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 561223 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1821659 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1821659 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1819985 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1819985 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 145566456 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 145566456 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 146418205 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 146418205 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041268 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.041268 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745043 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745043 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.795181 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.795181 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.085351 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.085351 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103104 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103104 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036907 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.036907 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041027 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041027 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14827.588377 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14827.588377 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16761.942072 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16761.942072 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 29407.773027 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 29407.773027 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15334.795472 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15334.795472 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21079.777029 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21079.777029 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14914.243872 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14914.243872 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13472.346676 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13472.346676 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15620.734183 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15620.734183 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13970.550598 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13970.550598 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1645,161 +1658,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3028608 # number of writebacks -system.cpu1.dcache.writebacks::total 3028608 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 352163 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 352163 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 814004 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 814004 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37997 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 37997 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 57 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 57 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1166167 # 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number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 8420 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 16669 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 16669 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35216853500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35216853500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 19067594000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 19067594000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11091696000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11091696000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 13273963000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 13273963000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1514299000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1514299000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3568894000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3568894000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2841500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2841500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 54284447500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 54284447500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 65376143500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 65376143500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1096081500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1096081500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1226588000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1226588000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2322669500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2322669500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035548 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035548 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017283 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017283 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.703146 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.703146 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.728091 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.728091 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064996 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064996 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096768 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096768 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027072 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027072 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030651 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030651 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12534.516958 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12534.516958 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16122.374710 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16122.374710 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20102.610946 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20102.610946 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31472.862464 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 31472.862464 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.443147 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12577.443147 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19929.493623 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19929.493623 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3232302 # number of writebacks +system.cpu1.dcache.writebacks::total 3232302 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357442 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 357442 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 916671 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 916671 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 62 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 62 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39535 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39535 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 40 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 40 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1274113 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1274113 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1274113 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1274113 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2812150 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2812150 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1286213 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1286213 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634154 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 634154 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446212 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 446212 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115945 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115945 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187608 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 187608 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4098363 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4098363 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4732517 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4732517 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5214 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5214 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5003 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5003 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10217 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10217 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37676406000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37676406000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20748839500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20748839500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13118141500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13118141500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12673625000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 12673625000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1579299000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1579299000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3766730000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3766730000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3027000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3027000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 58425245500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 58425245500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 71543387000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 71543387000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 574067000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 574067000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 612660500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 612660500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1186727500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1186727500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036614 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036614 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018705 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018705 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.744532 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.744532 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.795071 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.795071 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063648 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063648 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103082 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103082 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028155 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028155 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032322 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032322 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13397.722739 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13397.722739 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16131.728959 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16131.728959 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20686.050234 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20686.050234 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 28402.698717 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 28402.698717 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13621.104834 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13621.104834 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20077.661933 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20077.661933 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13597.392235 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13597.392235 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14387.282701 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14387.282701 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 132874.469633 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 132874.469633 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145675.534442 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 145675.534442 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 139340.662307 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 139340.662307 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14255.751748 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14255.751748 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15117.407291 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15117.407291 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110101.074031 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110101.074031 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 122458.624825 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 122458.624825 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116152.246256 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116152.246256 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 8962341 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.974355 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 216525917 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8962853 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.158147 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8375817756000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.974355 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990184 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990184 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8492244 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.981743 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 217573051 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8492756 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.618663 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8375822912000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.981743 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 459940393 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 459940393 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 216525917 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 216525917 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 216525917 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 216525917 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 216525917 # number of overall hits -system.cpu1.icache.overall_hits::total 216525917 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8962853 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8962853 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8962853 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8962853 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8962853 # number of overall misses -system.cpu1.icache.overall_misses::total 8962853 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 87475415500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 87475415500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 87475415500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 87475415500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 87475415500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 87475415500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 225488770 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 225488770 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 225488770 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 225488770 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 225488770 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 225488770 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039749 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.039749 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039749 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.039749 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039749 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.039749 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9759.773534 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9759.773534 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9759.773534 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9759.773534 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9759.773534 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9759.773534 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 460624372 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 460624372 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 217573051 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 217573051 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 217573051 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 217573051 # 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number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 83328642500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 83328642500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 226065808 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 226065808 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 226065808 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 226065808 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 226065808 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 226065808 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037568 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037568 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037568 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037568 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037568 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037568 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9811.730455 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9811.730455 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9811.730455 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9811.730455 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9811.730455 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9811.730455 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1808,254 +1821,257 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8962853 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8962853 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8962853 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8962853 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8962853 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8962853 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8492757 # 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average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94000 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94000 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 79082264500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 79082264500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 79082264500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 79082264500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 79082264500 # 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average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90010.752688 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6768411 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6768469 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 54 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6929819 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6929951 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 118 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 863435 # 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Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 886.808482 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.313913 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004441 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004579 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.265563 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.183849 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.054126 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.826472 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1213 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14689 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 401 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 707 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 75 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 26 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 662 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5268 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8016 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 626 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074036 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.896545 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 461861904 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 461861904 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 450787 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 134849 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 585636 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3028606 # 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average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15250.222823 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15250.222823 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 398416.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 398416.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29763.899302 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29763.899302 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 21893.896751 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 22795.864026 # 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average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24184.423623 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25097.274457 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86000 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124871.863256 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124438.503956 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 138175.178147 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 138175.178147 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86000 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 131591.757154 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 131338.802052 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.187211 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33705.774715 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41619.107045 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20070.782644 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20070.782644 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15177.422589 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.422589 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 421916.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 421916.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31663.900997 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31663.900997 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22230.931390 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25745.144886 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25745.144886 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39124.087029 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39124.087029 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26908.552600 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25242.843263 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26908.552600 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29622.038954 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102090.621404 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101738.741285 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114956.825904 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 114956.825904 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 108390.868161 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108152.909796 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 832335 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13281124 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 8420 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 6193652 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 13562835 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 802874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 900589 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 12966269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5003 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 6817398 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 13255066 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 909243 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 426908 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 320139 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 432313 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1723284 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 998712 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8962853 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5808138 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 527324 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 420340 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26886674 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15523980 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 318688 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1026227 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 43755569 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 573628544 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 486175782 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1136136 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3690912 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1064631374 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 10738560 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 39200977 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.285389 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.451600 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 440871 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344666 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 456246 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1853750 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1095537 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8492756 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6090536 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 551879 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 445151 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25476691 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16156139 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 386266 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1103974 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 43123070 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 543542336 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511133259 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1419024 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4021304 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1060115923 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 11712363 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 39696559 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.307834 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.461597 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 28013450 71.46% 71.46% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 11187527 28.54% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 27476611 69.22% 69.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 12219948 30.78% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 39200977 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 17410316483 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 39696559 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 17378215985 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 171564976 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 190636988 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13446378573 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12741161217 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7120820957 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7401084853 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 176677986 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 208902970 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 564893937 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 601334453 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40371 # Transaction distribution -system.iobus.trans_dist::ReadResp 40371 # Transaction distribution -system.iobus.trans_dist::WriteReq 136979 # Transaction distribution -system.iobus.trans_dist::WriteResp 136979 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47802 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40366 # Transaction distribution +system.iobus.trans_dist::ReadResp 40366 # Transaction distribution +system.iobus.trans_dist::WriteReq 136635 # Transaction distribution +system.iobus.trans_dist::WriteResp 136635 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47764 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2299,18 +2320,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231676 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231676 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231224 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47822 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47784 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2320,18 +2341,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155959 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513101 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36314000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496803 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36259000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2351,7 +2372,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22142000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2359,71 +2380,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 570865133 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569722386 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92952000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148116000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147920000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115819 # number of replacements -system.iocache.tags.tagsinuse 11.287255 # Cycle average of tags in use +system.iocache.tags.replacements 115594 # number of replacements +system.iocache.tags.tagsinuse 11.293777 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115835 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115610 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9174218723000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.836610 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.450645 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239788 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465665 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705453 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9174240356000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.830924 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.462853 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466428 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705861 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042899 # Number of tag accesses -system.iocache.tags.data_accesses 1042899 # Number of data accesses +system.iocache.tags.tag_accesses 1040865 # Number of tag accesses +system.iocache.tags.data_accesses 1040865 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8884 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8921 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses -system.iocache.demand_misses::total 8894 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8884 # number of demand (read+write) misses +system.iocache.demand_misses::total 8924 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8854 # number of overall misses -system.iocache.overall_misses::total 8894 # number of overall misses +system.iocache.overall_misses::realview.ide 8884 # number of overall misses +system.iocache.overall_misses::total 8924 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1658968057 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1664163057 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1643383037 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1648578037 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12654105076 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12654105076 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12626572349 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12626572349 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1658968057 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1664532057 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1643383037 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1648947037 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1658968057 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1664532057 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1643383037 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1648947037 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8884 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8921 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8884 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8924 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8884 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8924 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2438,54 +2459,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187369.331037 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187173.890114 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184982.331945 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184797.448380 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118280.351043 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118280.351043 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118306.089770 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118306.089770 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 187369.331037 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 187152.243872 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 184982.331945 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 184776.673801 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 187369.331037 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 187152.243872 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32802 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 184982.331945 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 184776.673801 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32047 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3449 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3474 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.510583 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.224813 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106950 # number of writebacks -system.iocache.writebacks::total 106950 # number of writebacks +system.iocache.writebacks::writebacks 106695 # number of writebacks +system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8884 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8921 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8854 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8884 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8924 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8854 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8894 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8884 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8924 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1216268057 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1219613057 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1199183037 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1202528037 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7304905076 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7304905076 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7290172349 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7290172349 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1216268057 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1219832057 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1199183037 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1202747037 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1216268057 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1219832057 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1199183037 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1202747037 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2500,614 +2521,613 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137369.331037 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137173.890114 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134982.331945 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134797.448380 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68280.351043 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68280.351043 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68306.089770 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68306.089770 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 137369.331037 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 137152.243872 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 134982.331945 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 134776.673801 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 137369.331037 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 137152.243872 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 134982.331945 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 134776.673801 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1146599 # number of replacements -system.l2c.tags.tagsinuse 63894.227459 # Cycle average of tags in use -system.l2c.tags.total_refs 5787888 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1208030 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.791179 # Average number of references to valid blocks. +system.l2c.tags.replacements 1417273 # number of replacements +system.l2c.tags.tagsinuse 63778.929439 # Cycle average of tags in use +system.l2c.tags.total_refs 6059487 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1477461 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.101284 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 20522.379023 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 161.905583 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 188.170352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7049.393840 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11329.558347 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10071.994886 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 91.721739 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 112.803397 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4897.031985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4344.569454 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5124.698853 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.313147 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002470 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002871 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.107565 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.172875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.153686 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001400 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001721 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.074723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.066293 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.078197 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.974949 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10689 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 178 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50564 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 577 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 2554 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7550 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 172 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1822 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 12846 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 35586 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163101 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002716 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.771545 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 67839853 # Number of tag accesses -system.l2c.tags.data_accesses 67839853 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2183647 # number of Writeback hits -system.l2c.Writeback_hits::total 2183647 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 31153 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 25605 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 56758 # 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Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 195 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50473 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 311 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9149 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 195 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1751 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5310 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43220 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.145264 # 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average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82838.998772 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75193.955857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86023.056630 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82838.998772 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75193.955857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86023.056630 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.606790 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.561367 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.584325 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.612171 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592415 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.602866 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.762808 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.410035 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.659941 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.188623 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.189908 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.424609 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166445 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.202368 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.188623 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.468787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.424609 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.240129 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.292574 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.188623 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.468787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.424609 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.240129 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.292574 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20763.848676 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20748.656488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20756.630372 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20820.245144 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.859554 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20804.792992 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84092.699617 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74998.374967 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82445.049668 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80225.346258 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80567.388288 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96087.167208 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83288.652898 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77690.847518 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90020.839209 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83288.652898 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77690.847518 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90020.839209 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153867.338482 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 106897.235358 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96814.419762 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147308.265016 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 121174.524941 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141563.686203 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154689.304992 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84123.177283 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97112.990662 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149431.465360 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 97955.526684 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142628.292167 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150603.202225 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 114109.977800 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 110091.472766 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152057.942203 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90897.846304 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 110548.279438 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90799 # Transaction distribution -system.membus.trans_dist::ReadResp 698902 # Transaction distribution -system.membus.trans_dist::WriteReq 38305 # Transaction distribution -system.membus.trans_dist::WriteResp 38305 # Transaction distribution -system.membus.trans_dist::Writeback 981364 # Transaction distribution -system.membus.trans_dist::CleanEvict 209019 # Transaction distribution -system.membus.trans_dist::UpgradeReq 434160 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 274076 # Transaction distribution -system.membus.trans_dist::UpgradeResp 111283 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 609626 # Transaction distribution -system.membus.trans_dist::ReadExResp 589528 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 608103 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122944 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 90388 # Transaction distribution +system.membus.trans_dist::ReadResp 903121 # Transaction distribution +system.membus.trans_dist::WriteReq 37855 # Transaction distribution +system.membus.trans_dist::WriteResp 37855 # Transaction distribution +system.membus.trans_dist::Writeback 1188917 # Transaction distribution +system.membus.trans_dist::CleanEvict 251117 # Transaction distribution +system.membus.trans_dist::UpgradeReq 423385 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 299485 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111205 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 657294 # Transaction distribution +system.membus.trans_dist::ReadExResp 636531 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 812733 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122698 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25274 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403229 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4551499 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343039 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 343039 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4894538 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155959 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5171308 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5317856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342726 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342726 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5660582 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50548 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 135367808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 135575639 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7275904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7275904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 142851543 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 619953 # Total snoops (count) -system.membus.snoop_fanout::samples 3354848 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47596 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 164770304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 164975029 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7270144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7270144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 172245173 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 635192 # Total snoops (count) +system.membus.snoop_fanout::samples 3870084 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3354848 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3870084 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3354848 # Request fanout histogram -system.membus.reqLayer0.occupancy 109588500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3870084 # Request fanout histogram +system.membus.reqLayer0.occupancy 109645497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21072500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 19606499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6982752656 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8359681063 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6858580357 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8175730132 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229669194 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229316266 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3151,56 +3171,56 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 90801 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4609563 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38305 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3165042 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1502795 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 483481 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 285744 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 769225 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 105 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1092976 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1092976 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4526002 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8264892 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6572319 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 14837211 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254099969 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185036822 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 439136791 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2966852 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12598332 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.109406 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.312147 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 90390 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4911274 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37855 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3585089 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1614217 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 477552 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 311291 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 788843 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 110 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1123188 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1123188 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4828127 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8913245 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6867211 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15780456 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 273644474 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200023995 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 473668469 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3257042 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13541412 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.121741 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.326987 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11220005 89.06% 89.06% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1378327 10.94% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11892865 87.83% 87.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1648547 12.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12598332 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8167142441 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 13541412 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8755054077 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2478499 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4888169243 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5258284103 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4052371405 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4190040133 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini index ecd472250..8ee0c60d1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -179,7 +179,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -638,7 +638,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -748,7 +748,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -836,7 +836,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1251,9 +1251,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout index 067811cf5..8160d6530 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 10:47:25 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 14 2015 23:30:17 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51694136923000 because m5_exit instruction encountered +Exiting @ tick 51694125219000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 8fffe3d01..f3053af8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.694137 # Number of seconds simulated -sim_ticks 51694136923000 # Number of ticks simulated -final_tick 51694136923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.694125 # Number of seconds simulated +sim_ticks 51694125219000 # Number of ticks simulated +final_tick 51694125219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173196 # Simulator instruction rate (inst/s) -host_op_rate 203514 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9441127725 # Simulator tick rate (ticks/s) -host_mem_usage 675004 # Number of bytes of host memory used -host_seconds 5475.42 # Real time elapsed on the host -sim_insts 948323287 # Number of instructions simulated -sim_ops 1114322939 # Number of ops (including micro ops) simulated +host_inst_rate 131034 # Simulator instruction rate (inst/s) +host_op_rate 153967 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7136466436 # Simulator tick rate (ticks/s) +host_mem_usage 718208 # Number of bytes of host memory used +host_seconds 7243.66 # Real time elapsed on the host +sim_insts 949163000 # Number of instructions simulated +sim_ops 1115282140 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 407232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 344384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10254400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 100902664 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 404352 # Number of bytes read from this memory -system.physmem.bytes_read::total 112313032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10254400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10254400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 94405184 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 407680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 346624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10124864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 101217736 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 409088 # Number of bytes read from this memory +system.physmem.bytes_read::total 112505992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10124864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10124864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 94737216 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 94425764 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5381 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 160225 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1576617 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6318 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1754904 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1475081 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 94757796 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6370 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 158201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1581540 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6392 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1757919 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1480269 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1477654 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 198367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1951917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2172645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1826226 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1482842 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 195861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1958012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2176379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 195861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 195861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1832650 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1826624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1826226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 198367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1952315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3999270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1754904 # Number of read requests accepted -system.physmem.writeReqs 1477654 # Number of write requests accepted -system.physmem.readBursts 1754904 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1477654 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 112259136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 54720 # Total number of bytes read from write queue -system.physmem.bytesWritten 94423744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 112313032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 94425764 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 855 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2252 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 146151 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 109407 # Per bank write bursts -system.physmem.perBankRdBursts::1 112864 # Per bank write bursts -system.physmem.perBankRdBursts::2 109220 # Per bank write bursts -system.physmem.perBankRdBursts::3 104188 # Per bank write bursts -system.physmem.perBankRdBursts::4 106449 # Per bank write bursts -system.physmem.perBankRdBursts::5 113846 # Per bank write bursts -system.physmem.perBankRdBursts::6 104146 # Per bank write bursts -system.physmem.perBankRdBursts::7 106564 # Per bank write bursts -system.physmem.perBankRdBursts::8 99467 # Per bank write bursts -system.physmem.perBankRdBursts::9 160932 # Per bank write bursts -system.physmem.perBankRdBursts::10 104576 # Per bank write bursts -system.physmem.perBankRdBursts::11 109948 # Per bank write bursts -system.physmem.perBankRdBursts::12 102336 # Per bank write bursts -system.physmem.perBankRdBursts::13 105581 # Per bank write bursts -system.physmem.perBankRdBursts::14 99543 # Per bank write bursts -system.physmem.perBankRdBursts::15 104982 # Per bank write bursts -system.physmem.perBankWrBursts::0 93507 # Per bank write bursts -system.physmem.perBankWrBursts::1 95050 # Per bank write bursts -system.physmem.perBankWrBursts::2 93111 # Per bank write bursts -system.physmem.perBankWrBursts::3 91031 # Per bank write bursts -system.physmem.perBankWrBursts::4 92702 # Per bank write bursts -system.physmem.perBankWrBursts::5 96804 # Per bank write bursts -system.physmem.perBankWrBursts::6 89915 # Per bank write bursts -system.physmem.perBankWrBursts::7 93502 # Per bank write bursts -system.physmem.perBankWrBursts::8 87351 # Per bank write bursts -system.physmem.perBankWrBursts::9 94209 # Per bank write bursts -system.physmem.perBankWrBursts::10 90719 # Per bank write bursts -system.physmem.perBankWrBursts::11 94851 # Per bank write bursts -system.physmem.perBankWrBursts::12 89273 # Per bank write bursts -system.physmem.perBankWrBursts::13 92330 # Per bank write bursts -system.physmem.perBankWrBursts::14 88747 # Per bank write bursts -system.physmem.perBankWrBursts::15 92269 # Per bank write bursts +system.physmem.bw_write::total 1833048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1832650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 195861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1958410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4009426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1757919 # Number of read requests accepted +system.physmem.writeReqs 1482842 # Number of write requests accepted +system.physmem.readBursts 1757919 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1482842 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 112457536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49280 # Total number of bytes read from write queue +system.physmem.bytesWritten 94756288 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 112505992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 94757796 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 770 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 146200 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 105973 # Per bank write bursts +system.physmem.perBankRdBursts::1 111407 # Per bank write bursts +system.physmem.perBankRdBursts::2 105002 # Per bank write bursts +system.physmem.perBankRdBursts::3 101812 # Per bank write bursts +system.physmem.perBankRdBursts::4 108332 # Per bank write bursts +system.physmem.perBankRdBursts::5 117578 # Per bank write bursts +system.physmem.perBankRdBursts::6 104534 # Per bank write bursts +system.physmem.perBankRdBursts::7 108687 # Per bank write bursts +system.physmem.perBankRdBursts::8 103848 # Per bank write bursts +system.physmem.perBankRdBursts::9 161007 # Per bank write bursts +system.physmem.perBankRdBursts::10 107405 # Per bank write bursts +system.physmem.perBankRdBursts::11 110838 # Per bank write bursts +system.physmem.perBankRdBursts::12 104563 # Per bank write bursts +system.physmem.perBankRdBursts::13 103815 # Per bank write bursts +system.physmem.perBankRdBursts::14 100822 # Per bank write bursts +system.physmem.perBankRdBursts::15 101526 # Per bank write bursts +system.physmem.perBankWrBursts::0 90430 # Per bank write bursts +system.physmem.perBankWrBursts::1 94995 # Per bank write bursts +system.physmem.perBankWrBursts::2 91678 # Per bank write bursts +system.physmem.perBankWrBursts::3 90022 # Per bank write bursts +system.physmem.perBankWrBursts::4 94229 # Per bank write bursts +system.physmem.perBankWrBursts::5 99888 # Per bank write bursts +system.physmem.perBankWrBursts::6 89385 # Per bank write bursts +system.physmem.perBankWrBursts::7 93994 # Per bank write bursts +system.physmem.perBankWrBursts::8 90076 # Per bank write bursts +system.physmem.perBankWrBursts::9 95745 # Per bank write bursts +system.physmem.perBankWrBursts::10 91874 # Per bank write bursts +system.physmem.perBankWrBursts::11 95898 # Per bank write bursts +system.physmem.perBankWrBursts::12 91438 # Per bank write bursts +system.physmem.perBankWrBursts::13 92023 # Per bank write bursts +system.physmem.perBankWrBursts::14 89075 # Per bank write bursts +system.physmem.perBankWrBursts::15 89817 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 31 # Number of times write queue was full causing retry -system.physmem.totGap 51694135218000 # Total gap between requests +system.physmem.numWrRetry 27 # Number of times write queue was full causing retry +system.physmem.totGap 51694123514000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1754889 # Read request sizes (log2) +system.physmem.readPktSize::6 1757904 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1475081 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1420187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 327570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 878 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1480269 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1422025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 328688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,164 +159,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 15753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 18367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 69542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 87805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 88303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 88136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 87821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 90771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 91285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 93842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 93403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 89996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 90062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 102154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 88485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 90293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 86850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 688077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 300.376987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.587339 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.638975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 270609 39.33% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 164654 23.93% 63.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 63521 9.23% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36566 5.31% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 27027 3.93% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 18739 2.72% 84.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14736 2.14% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13602 1.98% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 78623 11.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 688077 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 86230 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.341007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 270.950677 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 86227 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 15568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 71947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 88213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 88480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 88386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 88377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 91264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 92065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 94405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 93246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 93724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 90170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 90391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 100271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 88772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 90332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 87233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 83 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 690739 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 299.988042 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.369601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.443819 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 271817 39.35% 39.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 165800 24.00% 63.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 63380 9.18% 72.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36796 5.33% 77.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 26984 3.91% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18833 2.73% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14857 2.15% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13605 1.97% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 78667 11.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 690739 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 86593 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.291686 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 270.345126 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 86590 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 86230 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 86230 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.109718 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.738195 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.845815 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 83739 97.11% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 148 0.17% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 433 0.50% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 182 0.21% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 327 0.38% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 491 0.57% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 146 0.17% 99.11% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 86593 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 86593 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.097999 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.728630 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.809360 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 84121 97.15% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 149 0.17% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 413 0.48% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 198 0.23% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 310 0.36% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 507 0.59% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 123 0.14% 99.11% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 35 0.04% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 38 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.02% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 25 0.03% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 26 0.03% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 445 0.52% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 41 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 34 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 31 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 32 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 86230 # Writes before turning the bus around for reads -system.physmem.totQLat 26659687931 # Total ticks spent queuing -system.physmem.totMemAccLat 59548106681 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8770245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15198.94 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::48-51 41 0.05% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 24 0.03% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 40 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 29 0.03% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 413 0.48% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 31 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 42 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 40 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 31 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 86593 # Writes before turning the bus around for reads +system.physmem.totQLat 26847024830 # Total ticks spent queuing +system.physmem.totMemAccLat 59793568580 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8785745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15278.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33948.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34028.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing -system.physmem.readRowHits 1434287 # Number of row buffer hits during reads -system.physmem.writeRowHits 1107055 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes -system.physmem.avgGap 15991711.59 # Average gap between requests -system.physmem.pageHitRate 78.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2644873560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1443135375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6760088400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4831630560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3376409683920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1310236671105 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29867151449250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34569477532170 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.731116 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49685803332014 # Time in different power states -system.physmem_0.memoryStateTime::REF 1726180820000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing +system.physmem.readRowHits 1436721 # Number of row buffer hits during reads +system.physmem.writeRowHits 1110255 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.99 # Row buffer hit rate for writes +system.physmem.avgGap 15951229.82 # Average gap between requests +system.physmem.pageHitRate 78.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2651919480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1446979875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6733888200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4825144080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1308234674070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29868898243500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34569199516005 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.725939 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49688706621634 # Time in different power states +system.physmem_0.memoryStateTime::REF 1726180300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 282152299236 # Time in different power states +system.physmem_0.memoryStateTime::ACT 279237825366 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2556988560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1395182250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6921447000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4728773520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3376409683920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1305311169150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29871472073250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34568795317650 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.717918 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49692977337193 # Time in different power states -system.physmem_1.memoryStateTime::REF 1726180820000 # Time in different power states +system.physmem_1.actEnergy 2570067360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1402318500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6971827200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4768930080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1306063695690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29870802610500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34568988116130 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.721850 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49691848230640 # Time in different power states +system.physmem_1.memoryStateTime::REF 1726180300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 274978307807 # Time in different power states +system.physmem_1.memoryStateTime::ACT 276092348110 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -340,15 +341,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 260235992 # Number of BP lookups -system.cpu.branchPred.condPredicted 182594285 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12181539 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193306639 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136184729 # Number of BTB hits +system.cpu.branchPred.lookups 260286663 # Number of BP lookups +system.cpu.branchPred.condPredicted 182589592 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12077009 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 191806323 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136128585 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.450104 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31573215 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2152291 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.971896 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31602025 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2167880 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -379,61 +380,61 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 586554 # Table walker walks requested -system.cpu.dtb.walker.walksLong 586554 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22200 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191198 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 586554 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 586554 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 586554 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 213398 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 26171.173113 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 22678.472578 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15672.620914 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 210833 98.80% 98.80% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2191 1.03% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 145 0.07% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 108 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 74 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 36 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 213398 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 582770 # Table walker walks requested +system.cpu.dtb.walker.walksLong 582770 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22376 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191329 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 582770 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 582770 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 582770 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 213705 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26351.678716 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22931.447770 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15578.711548 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 211142 98.80% 98.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2168 1.01% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 149 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 124 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 84 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 213705 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -58656296 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -58656296 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -58656296 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 191199 89.60% 89.60% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 22200 10.40% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 213399 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 586554 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 191330 89.53% 89.53% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 22376 10.47% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 213706 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 582770 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 586554 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213399 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 582770 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213706 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213399 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 799953 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213706 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 796476 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183104972 # DTB read hits -system.cpu.dtb.read_misses 484611 # DTB read misses -system.cpu.dtb.write_hits 162443368 # DTB write hits -system.cpu.dtb.write_misses 101943 # DTB write misses +system.cpu.dtb.read_hits 183257458 # DTB read hits +system.cpu.dtb.read_misses 481031 # DTB read misses +system.cpu.dtb.write_hits 162586595 # DTB write hits +system.cpu.dtb.write_misses 101739 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80156 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 829 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15457 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 80339 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1450 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15121 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23578 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183589583 # DTB read accesses -system.cpu.dtb.write_accesses 162545311 # DTB write accesses +system.cpu.dtb.perms_faults 23575 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 183738489 # DTB read accesses +system.cpu.dtb.write_accesses 162688334 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 345548340 # DTB hits -system.cpu.dtb.misses 586554 # DTB misses -system.cpu.dtb.accesses 346134894 # DTB accesses +system.cpu.dtb.hits 345844053 # DTB hits +system.cpu.dtb.misses 582770 # DTB misses +system.cpu.dtb.accesses 346426823 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -463,46 +464,42 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 136663 # Table walker walks requested -system.cpu.itb.walker.walksLong 136663 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1080 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 119012 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136663 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136663 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136663 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 120092 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28563.884355 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 25001.850654 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17459.523046 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 59524 49.57% 49.57% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 57595 47.96% 97.52% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 1126 0.94% 98.46% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 1581 1.32% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 30 0.02% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 128 0.11% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 37 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 22 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 13 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 15 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 120092 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 136614 # Table walker walks requested +system.cpu.itb.walker.walksLong 136614 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1073 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118911 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136614 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136614 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136614 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 119984 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28837.324143 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 25253.165818 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17670.490053 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 116985 97.50% 97.50% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2707 2.26% 99.76% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 180 0.15% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 56 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 24 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 119984 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -59528796 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -59528796 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -59528796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 119012 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1080 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 120092 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 118911 99.11% 99.11% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1073 0.89% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 119984 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136663 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136663 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136614 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136614 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120092 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 120092 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 256755 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 453103030 # ITB inst hits -system.cpu.itb.inst_misses 136663 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119984 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 119984 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256598 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 452975639 # ITB inst hits +system.cpu.itb.inst_misses 136614 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -511,140 +508,139 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57609 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 57698 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 364302 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 370160 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 453239693 # ITB inst accesses -system.cpu.itb.hits 453103030 # DTB hits -system.cpu.itb.misses 136663 # DTB misses -system.cpu.itb.accesses 453239693 # DTB accesses -system.cpu.numCycles 2508251480 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 453112253 # ITB inst accesses +system.cpu.itb.hits 452975639 # DTB hits +system.cpu.itb.misses 136614 # DTB misses +system.cpu.itb.accesses 453112253 # DTB accesses +system.cpu.numCycles 2511767999 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 948323287 # Number of instructions committed -system.cpu.committedOps 1114322939 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97332960 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7744 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100881187078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.644933 # CPI: cycles per instruction -system.cpu.ipc 0.378081 # IPC: instructions per cycle +system.cpu.committedInsts 949163000 # Number of instructions committed +system.cpu.committedOps 1115282140 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97160712 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7743 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100877722288 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.646298 # CPI: cycles per instruction +system.cpu.ipc 0.377886 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16604 # number of quiesce instructions executed -system.cpu.tickCycles 1790178903 # Number of cycles that the object actually ticked -system.cpu.idleCycles 718072577 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11134622 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.957818 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 329114421 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11135134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.556395 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 19481 # number of quiesce instructions executed +system.cpu.tickCycles 1790897935 # Number of cycles that the object actually ticked +system.cpu.idleCycles 720870064 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11142195 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.957822 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 329410408 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11142707 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.562871 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4277412500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.957818 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.957822 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999918 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999918 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1383337751 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1383337751 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 168246441 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 168246441 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 151606594 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 151606594 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 524249 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 524249 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336460 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336460 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4018923 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4018923 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4332342 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4332342 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 319853035 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 319853035 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320377284 # number of overall hits -system.cpu.dcache.overall_hits::total 320377284 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6626426 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6626426 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4317891 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4317891 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1480828 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1480828 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1245336 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1245336 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 315150 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 315150 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1384553632 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1384553632 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 168394927 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 168394927 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 151754199 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 151754199 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 523439 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 523439 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336679 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336679 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4017108 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4017108 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4334477 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4334477 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 320149126 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320149126 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320672565 # number of overall hits +system.cpu.dcache.overall_hits::total 320672565 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6628843 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6628843 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4317749 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4317749 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1481094 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1481094 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1245106 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1245106 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 319103 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 319103 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 10944317 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10944317 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12425145 # number of overall misses -system.cpu.dcache.overall_misses::total 12425145 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 107226750500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 107226750500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 152543350000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 152543350000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 58512566000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 58512566000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4781324500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4781324500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 10946592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10946592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12427686 # number of overall misses +system.cpu.dcache.overall_misses::total 12427686 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 107264639000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 107264639000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 153170066000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 153170066000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 58641269000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 58641269000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4837420500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4837420500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 115500 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 115500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 259770100500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 259770100500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 259770100500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 259770100500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 174872867 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 174872867 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 155924485 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 155924485 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2005077 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2005077 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1581796 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1581796 # 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miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027692 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738539 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.738539 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787292 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787292 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072715 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072715 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 260434705000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 260434705000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 260434705000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 260434705000 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033211 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033211 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015477 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015477 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787198 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787198 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056560 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056560 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168281893500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168281893500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191938684500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191938684500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5830552000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5830552000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5692063000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5692063000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11522615000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11522615000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033202 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033202 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.735180 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.735180 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787057 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787057 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057334 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057334 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024852 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024852 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029129 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029129 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15135.191542 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15135.191542 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33153.740312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33153.740312 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16054.878330 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16054.878330 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 45987.727536 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 45987.727536 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13605.363961 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13605.363961 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024842 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024842 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029117 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15133.962918 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15133.962918 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33280.319641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33280.319641 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16052.726721 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.726721 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 46099.699588 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 46099.699588 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13620.932450 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13620.932450 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 56750 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 56750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20424.550586 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20424.550586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19760.448808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19760.448808 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173016.602867 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173016.602867 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168867.965111 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168867.965111 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170942.037801 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170942.037801 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20459.712643 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20459.712643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19790.084320 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19790.084320 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173018.546544 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173018.546544 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168868.869968 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168868.869968 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170943.462006 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170943.462006 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24460747 # number of replacements -system.cpu.icache.tags.tagsinuse 511.918526 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 428265010 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24461259 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.507889 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26893649500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.918526 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 24575522 # number of replacements +system.cpu.icache.tags.tagsinuse 511.918698 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 428017274 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24576034 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.416043 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26893274500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.918698 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999841 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999841 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 477187547 # Number of tag accesses -system.cpu.icache.tags.data_accesses 477187547 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 428265010 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 428265010 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 428265010 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 428265010 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 428265010 # number of overall hits -system.cpu.icache.overall_hits::total 428265010 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24461269 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24461269 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24461269 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24461269 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24461269 # number of overall misses -system.cpu.icache.overall_misses::total 24461269 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 325762917500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 325762917500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 325762917500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 325762917500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 325762917500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 325762917500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 452726279 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 452726279 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 452726279 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 452726279 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 452726279 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 452726279 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054031 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054031 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054031 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 428017274 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 428017274 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 428017274 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 428017274 # number of overall hits +system.cpu.icache.overall_hits::total 428017274 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24576044 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24576044 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24576044 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24576044 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24576044 # number of overall misses +system.cpu.icache.overall_misses::total 24576044 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 327136040500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 327136040500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 327136040500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 327136040500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 327136040500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 327136040500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 452593318 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 452593318 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 452593318 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 452593318 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 452593318 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 452593318 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054301 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054301 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054301 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054301 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054301 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054301 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13311.175733 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13311.175733 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13311.175733 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13311.175733 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13311.175733 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13311.175733 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -810,225 +806,225 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24461269 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24461269 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24461269 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24461269 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24461269 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24461269 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24576044 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 24576044 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24576044 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24576044 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24576044 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24576044 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52295 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 52295 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52295 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 52295 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 301301649500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 301301649500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 301301649500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 301301649500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 301301649500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 301301649500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302559997500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 302559997500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302559997500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 302559997500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302559997500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 302559997500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4042938500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4042938500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4042938500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 4042938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054031 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054031 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054031 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.054031 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054031 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.054031 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12317.498716 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12317.498716 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12317.498716 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12317.498716 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12317.498716 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12317.498716 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054301 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.054301 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.054301 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12311.175773 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12311.175773 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12311.175773 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12311.175773 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12311.175773 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12311.175773 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77310.230424 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77310.230424 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1604829 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65266.156442 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 67107084 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1667914 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 40.234139 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 24502559000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 35881.888844 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 344.047128 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 429.269400 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8228.433015 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20382.518055 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.547514 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005250 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006550 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125556 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.311013 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8203.980766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20343.466323 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.549352 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005114 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006619 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125183 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.310417 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996685 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 219 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63009 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 275 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 504 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2442 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5503 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54305 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958389 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 585371330 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 585371330 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 972902 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 283103 # 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number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 972902 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 283103 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 24353307 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8855373 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 34464685 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 972902 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 283103 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 24353307 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8855373 # number of overall hits -system.cpu.l2cache.overall_hits::total 34464685 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6363 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5381 # 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Number of tag accesses +system.cpu.l2cache.tags.data_accesses 587356710 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 972528 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 286301 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1258829 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8554549 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8554549 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 10855 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 10855 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1654669 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1654669 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24470106 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 24470106 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7204785 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7204785 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 700263 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 700263 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 972528 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 286301 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 24470106 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8859454 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 34588389 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 972528 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 286301 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 24470106 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8859454 # number of overall hits +system.cpu.l2cache.overall_hits::total 34588389 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6370 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5416 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 11786 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 38716 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 38716 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 705767 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 705767 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107959 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 107959 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 328857 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 416253000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7593134000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75381930000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 83880739500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 489422500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 416253000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7593134000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75381930000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 83880739500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3232365500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5409182000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8641547500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5303781000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5303781000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5409250000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8641615500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5303815500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5303815500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3232365500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10712963000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13945328500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006498 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018653 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009264 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10713065500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13945431000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782948 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782948 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781021 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781021 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.298531 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.298531 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004413 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004413 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043694 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043694 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.436442 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.436442 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006498 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018653 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004413 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104611 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.032407 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006498 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018653 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004413 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104611 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.032407 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76815.368891 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76968.239101 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.283868 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.283868 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.300240 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300240 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004310 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.437519 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.437519 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104902 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032341 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104902 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.032341 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76843.331071 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.735510 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.735510 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71684.748649 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71684.748649 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71444.560747 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71444.560747 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74373.452116 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74373.452116 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77882.458584 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77882.458584 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76815.368891 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71444.560747 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72539.320396 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72481.993463 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76815.368891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71444.560747 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72539.320396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72481.993463 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71714.440252 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71714.440252 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71679.322584 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71679.322584 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74519.325709 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74519.325709 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77950.919052 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77950.919052 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71679.322584 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72601.440049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72560.189046 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71679.322584 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72601.440049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72560.189046 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160514.614677 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.121404 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157349.541638 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157349.541638 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160516.632541 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.912157 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157350.565165 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157350.565165 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158931.890336 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116501.353372 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158933.410972 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116502.209672 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1796538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33784448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1789463 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33899423 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 10027137 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 27284097 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 10034845 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 27401014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49574 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49408 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2364132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2364132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24461269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7534742 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1351850 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1245186 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73484098 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33638682 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 696808 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2281485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 110101073 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1568867840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1180529566 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2307872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7834120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2759539398 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2279468 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 74907361 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.047344 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.212374 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 49576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2364622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2364622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24576044 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7542009 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1351619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1244955 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73828388 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33661752 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 699908 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2274176 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 110464224 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576213440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1181188062 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2333736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7831184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2767566422 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2271727 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 75147333 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.047128 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.211913 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 71360927 95.27% 95.27% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 3546434 4.73% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 71605763 95.29% 95.29% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 3541570 4.71% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 74907361 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 45104615497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 75147333 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 45226020496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1167000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36773946781 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36946016966 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15533347490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15544978992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 408345956 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 408213455 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1302236467 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1295285984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40325 # Transaction distribution -system.iobus.trans_dist::ReadResp 40325 # Transaction distribution +system.iobus.trans_dist::ReadReq 40306 # Transaction distribution +system.iobus.trans_dist::ReadResp 40306 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1247,11 +1243,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1268,11 +1264,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1301,71 +1297,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568973549 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568890575 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115486 # number of replacements -system.iocache.tags.tagsinuse 10.447136 # Cycle average of tags in use +system.iocache.tags.replacements 115467 # number of replacements +system.iocache.tags.tagsinuse 10.447125 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115483 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13147036427000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519010 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928125 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13147039080000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519011 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928115 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.219938 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433008 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652946 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433007 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652945 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039893 # Number of tag accesses -system.iocache.tags.data_accesses 1039893 # Number of data accesses +system.iocache.tags.tag_accesses 1039722 # Number of tag accesses +system.iocache.tags.data_accesses 1039722 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8840 # number of demand (read+write) misses -system.iocache.demand_misses::total 8880 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8821 # number of demand (read+write) misses +system.iocache.demand_misses::total 8861 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8840 # number of overall misses -system.iocache.overall_misses::total 8880 # number of overall misses +system.iocache.overall_misses::realview.ide 8821 # number of overall misses +system.iocache.overall_misses::total 8861 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1592056146 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1597125146 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1605437158 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1610506158 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12612249403 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12612249403 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12610481417 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12610481417 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1592056146 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1597476146 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1605437158 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1610857158 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1592056146 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1597476146 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1605437158 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1610857158 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8840 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8880 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8821 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8861 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8840 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8880 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8821 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8861 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1380,54 +1376,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 180096.849095 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 179917.218204 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182001.718399 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 181813.745541 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118242.794223 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118242.794223 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.218940 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118226.218940 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 180096.849095 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 179895.962387 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 181791.802054 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 180096.849095 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 179895.962387 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 29944 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 181791.802054 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31114 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3370 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3332 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.885460 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.337935 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8840 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8880 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8821 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8861 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8840 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8880 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8821 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8861 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150056146 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1153275146 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1164387158 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1167606158 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279049403 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7279049403 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277281417 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7277281417 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1150056146 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1153476146 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1164387158 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1167807158 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1150056146 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1153476146 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1164387158 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1167807158 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1442,72 +1438,72 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130096.849095 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 129917.218204 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132001.718399 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 131813.745541 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68242.794223 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68242.794223 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.218940 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.218940 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130096.849095 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 129895.962387 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130096.849095 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 129895.962387 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 85994 # Transaction distribution -system.membus.trans_dist::ReadResp 543407 # Transaction distribution +system.membus.trans_dist::ReadResp 540915 # Transaction distribution system.membus.trans_dist::WriteReq 33707 # Transaction distribution system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::Writeback 1475081 # Transaction distribution -system.membus.trans_dist::CleanEvict 242486 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39492 # Transaction distribution +system.membus.trans_dist::Writeback 1480269 # Transaction distribution +system.membus.trans_dist::CleanEvict 239619 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39541 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39494 # Transaction distribution -system.membus.trans_dist::ReadExReq 1248409 # Transaction distribution -system.membus.trans_dist::ReadExResp 1248409 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 457413 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39543 # Transaction distribution +system.membus.trans_dist::ReadExReq 1253823 # Transaction distribution +system.membus.trans_dist::ReadExResp 1253823 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 454921 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5186779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5316437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341268 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341268 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5657705 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5195008 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5324666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5666061 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13844 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199510060 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 199680478 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7228736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7228736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 206909214 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3224 # Total snoops (count) -system.membus.snoop_fanout::samples 3692024 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 200030316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 200200734 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7233472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 207434206 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3131 # Total snoops (count) +system.membus.snoop_fanout::samples 3697223 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3692024 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3697223 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3692024 # Request fanout histogram -system.membus.reqLayer0.occupancy 102515000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3697223 # Request fanout histogram +system.membus.reqLayer0.occupancy 102366500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5516000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5756000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9935800091 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9961724084 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9380119144 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9396279986 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228946369 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228925719 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1551,13 +1547,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini index ef60c64b3..7fb6c1d15 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -352,7 +352,7 @@ type=ExeTracer eventq_index=0 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -693,7 +693,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -803,7 +803,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -891,7 +891,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1306,9 +1306,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr index 18ae58d7b..95cf6c86b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr @@ -11,84 +11,89 @@ warn: 12461855003000: Instruction results do not match! (Values may not actually warn: 12461858210000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: 13850221736500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13887901759500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13889201357500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13891026528000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13912972124000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13922135264000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13972304377500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 14214756028000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14214756243500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14222804811500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14230560980500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14230561210500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14230561417000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14238296234000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14238296464000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14238296670500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14243468378000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14243468608000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14249670454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14249670684500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14259219992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14259220222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14259220428500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14270200247500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14270200481500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14270200711500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14270200918000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14279912002500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14279912512000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14279912746000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14279912976000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14279913182500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14295232623000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14295232862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14300292322000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14300292552000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14307240927500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14307241161500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14307241391500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14307241598000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14317300126000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14317300896500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14317301130500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14317301360500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14317301567000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14379824982500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14379825231000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14379825446500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14437325800500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14437326869000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14437327084500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14565495184000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565581739000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14565581956000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565582249000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 -warn: 14565582808000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565583286500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565583575500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565584084500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565585151500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565585961500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566302033500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566302294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 -warn: 14566302499000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566373295000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14566373505000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566373776000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 -warn: 14566374346500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566374602000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14566374825500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566375114500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566375623500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566376687000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566377185000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566377487000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14614511931000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 -warn: 14614512222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14614512481000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14614512725500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14614512987500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14614513217000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 13846883856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13889111424500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13890567287500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13890857543500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14120809755000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14122306502500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14122718805500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14129885647500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14130112878000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14130333669000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14130937323000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14131157192000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14131378652000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14143275616000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14210692350500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14453290384000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14453290599500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14461368009500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14469164155500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14469164395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14469164601500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14477036010500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14477036254000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14477036493500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14477036700000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14482248599500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14482248839000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14488506207500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14488506438000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14498157332500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14498158077500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14498158308000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14498158514500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14509187190500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14509187421000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14509187627500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14518942903500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14518943414000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14518943648500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14518943879000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14518944085500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14534430251500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14534430481500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14539499143500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14539499377500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14539499607500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14546501559500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14546502303000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14546502533000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14546502739500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14556606981000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14556607490500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14556607724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14556607954500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14556608161000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14619728573500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14619728789000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14678031922000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14678032489500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14678032742000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14678032990500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14678033206000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14803922617500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804021218000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804021536500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804745192000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804745453000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 +warn: 14804745657500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804816537000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14804816747000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804817018000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 +warn: 14804817588500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804817844000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14804818067500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804818356500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804818865500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804819928000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804820419500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804820721500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14853183049500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14853362963500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 14853363240000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14853363492000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14853363736500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14853363998500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14853364228000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout index 703b25032..ddf9e75e0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 11:01:08 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:50:46 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51323721423000 because m5_exit instruction encountered +Exiting @ tick 51562169701000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 597734940..e2a586128 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.323721 # Number of seconds simulated -sim_ticks 51323721423000 # Number of ticks simulated -final_tick 51323721423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.562170 # Number of seconds simulated +sim_ticks 51562169701000 # Number of ticks simulated +final_tick 51562169701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88242 # Simulator instruction rate (inst/s) -host_op_rate 103686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5307363437 # Simulator tick rate (ticks/s) -host_mem_usage 679356 # Number of bytes of host memory used -host_seconds 9670.29 # Real time elapsed on the host -sim_insts 853325819 # Number of instructions simulated -sim_ops 1002674190 # Number of ops (including micro ops) simulated +host_inst_rate 60233 # Simulator instruction rate (inst/s) +host_op_rate 70799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2812244888 # Simulator tick rate (ticks/s) +host_mem_usage 727556 # Number of bytes of host memory used +host_seconds 18334.88 # Real time elapsed on the host +sim_insts 1104366834 # Number of instructions simulated +sim_ops 1298086167 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 203200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 189632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5727200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 73778504 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory -system.physmem.bytes_read::total 80318312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5727200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5727200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68723904 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 657984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 557504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6634080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 148649160 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 417792 # Number of bytes read from this memory +system.physmem.bytes_read::total 156916520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6634080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6634080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 139624832 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68744484 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3175 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105440 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1152802 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1270939 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1073811 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 139645412 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10281 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 119610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2322656 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6528 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2467786 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2181638 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1076384 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 3959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 111590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1437513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1564935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 111590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1339028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1339429 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1339028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 3959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 111590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1437914 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2904365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1270939 # Number of read requests accepted -system.physmem.writeReqs 1076384 # Number of write requests accepted -system.physmem.readBursts 1270939 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1076384 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 81299584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 40512 # Total number of bytes read from write queue -system.physmem.bytesWritten 68742976 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 80318312 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68744484 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 633 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 142017 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 76590 # Per bank write bursts -system.physmem.perBankRdBursts::1 80112 # Per bank write bursts -system.physmem.perBankRdBursts::2 82312 # Per bank write bursts -system.physmem.perBankRdBursts::3 76894 # Per bank write bursts -system.physmem.perBankRdBursts::4 75148 # Per bank write bursts -system.physmem.perBankRdBursts::5 84486 # Per bank write bursts -system.physmem.perBankRdBursts::6 75307 # Per bank write bursts -system.physmem.perBankRdBursts::7 76047 # Per bank write bursts -system.physmem.perBankRdBursts::8 76921 # Per bank write bursts -system.physmem.perBankRdBursts::9 104197 # Per bank write bursts -system.physmem.perBankRdBursts::10 75653 # Per bank write bursts -system.physmem.perBankRdBursts::11 81028 # Per bank write bursts -system.physmem.perBankRdBursts::12 74845 # Per bank write bursts -system.physmem.perBankRdBursts::13 77383 # Per bank write bursts -system.physmem.perBankRdBursts::14 76622 # Per bank write bursts -system.physmem.perBankRdBursts::15 76761 # Per bank write bursts -system.physmem.perBankWrBursts::0 64108 # Per bank write bursts -system.physmem.perBankWrBursts::1 67910 # Per bank write bursts -system.physmem.perBankWrBursts::2 69982 # Per bank write bursts -system.physmem.perBankWrBursts::3 67432 # Per bank write bursts -system.physmem.perBankWrBursts::4 65959 # Per bank write bursts -system.physmem.perBankWrBursts::5 70786 # Per bank write bursts -system.physmem.perBankWrBursts::6 64733 # Per bank write bursts -system.physmem.perBankWrBursts::7 66187 # Per bank write bursts -system.physmem.perBankWrBursts::8 67287 # Per bank write bursts -system.physmem.perBankWrBursts::9 71812 # Per bank write bursts -system.physmem.perBankWrBursts::10 65064 # Per bank write bursts -system.physmem.perBankWrBursts::11 69201 # Per bank write bursts -system.physmem.perBankWrBursts::12 65082 # Per bank write bursts -system.physmem.perBankWrBursts::13 66370 # Per bank write bursts -system.physmem.perBankWrBursts::14 66024 # Per bank write bursts -system.physmem.perBankWrBursts::15 66172 # Per bank write bursts +system.physmem.num_writes::total 2184211 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 12761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 10812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 128662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2882911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3043249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 128662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 128662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2707893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2708292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2707893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 10812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 128662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2883310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5751541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2467786 # Number of read requests accepted +system.physmem.writeReqs 2184211 # Number of write requests accepted +system.physmem.readBursts 2467786 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2184211 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 157889856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48448 # Total number of bytes read from write queue +system.physmem.bytesWritten 139644224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 156916520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 139645412 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 757 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 155211 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 149005 # Per bank write bursts +system.physmem.perBankRdBursts::1 156339 # Per bank write bursts +system.physmem.perBankRdBursts::2 155955 # Per bank write bursts +system.physmem.perBankRdBursts::3 150628 # Per bank write bursts +system.physmem.perBankRdBursts::4 148084 # Per bank write bursts +system.physmem.perBankRdBursts::5 159303 # Per bank write bursts +system.physmem.perBankRdBursts::6 149188 # Per bank write bursts +system.physmem.perBankRdBursts::7 152515 # Per bank write bursts +system.physmem.perBankRdBursts::8 150862 # Per bank write bursts +system.physmem.perBankRdBursts::9 179370 # Per bank write bursts +system.physmem.perBankRdBursts::10 150320 # Per bank write bursts +system.physmem.perBankRdBursts::11 155893 # Per bank write bursts +system.physmem.perBankRdBursts::12 152080 # Per bank write bursts +system.physmem.perBankRdBursts::13 155961 # Per bank write bursts +system.physmem.perBankRdBursts::14 150556 # Per bank write bursts +system.physmem.perBankRdBursts::15 150970 # Per bank write bursts +system.physmem.perBankWrBursts::0 132106 # Per bank write bursts +system.physmem.perBankWrBursts::1 138501 # Per bank write bursts +system.physmem.perBankWrBursts::2 137398 # Per bank write bursts +system.physmem.perBankWrBursts::3 135602 # Per bank write bursts +system.physmem.perBankWrBursts::4 133392 # Per bank write bursts +system.physmem.perBankWrBursts::5 140433 # Per bank write bursts +system.physmem.perBankWrBursts::6 132940 # Per bank write bursts +system.physmem.perBankWrBursts::7 137025 # Per bank write bursts +system.physmem.perBankWrBursts::8 135656 # Per bank write bursts +system.physmem.perBankWrBursts::9 141181 # Per bank write bursts +system.physmem.perBankWrBursts::10 134433 # Per bank write bursts +system.physmem.perBankWrBursts::11 138339 # Per bank write bursts +system.physmem.perBankWrBursts::12 136301 # Per bank write bursts +system.physmem.perBankWrBursts::13 138853 # Per bank write bursts +system.physmem.perBankWrBursts::14 135122 # Per bank write bursts +system.physmem.perBankWrBursts::15 134659 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 51323720227500 # Total gap between requests +system.physmem.numWrRetry 21 # Number of times write queue was full causing retry +system.physmem.totGap 51562168447500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1249654 # Read request sizes (log2) +system.physmem.readPktSize::6 2446501 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1073811 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 646219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 339232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 151287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 128129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2181638 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1276105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 831313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 193469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 160610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 946 # What read queue length does an incoming req see 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write queue length does an incoming req see -system.physmem.wrQLenPdf::35 637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see 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an incoming req see -system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 481355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.708207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.914901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.146013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 186832 38.81% 38.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 113175 23.51% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45398 9.43% 71.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23450 4.87% 76.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18101 3.76% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11671 2.42% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10460 2.17% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8315 1.73% 86.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 63953 13.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 481355 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61522 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.647411 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 265.936082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 61519 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 20208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 23029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 68337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 107857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 119474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 131451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 131860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 135328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 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write queue length does an incoming req see +system.physmem.wrQLenPdf::47 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 140 # What write queue length does an incoming req see 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23.23% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89990 9.59% 70.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51985 5.54% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 41514 4.43% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 28050 2.99% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24686 2.63% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20558 2.19% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 114387 12.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 938073 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 129462 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 19.055908 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 183.344638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 129459 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61522 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.458942 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.948779 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.823778 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 58490 95.07% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 664 1.08% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 448 0.73% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 190 0.31% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 308 0.50% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 527 0.86% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 143 0.23% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 33 0.05% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 36 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.03% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 32 0.05% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 22 0.04% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 426 0.69% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 45 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 33 0.05% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 31 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 129462 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 129462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.853911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.595936 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.789289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 125866 97.22% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1229 0.95% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 433 0.33% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 197 0.15% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 330 0.25% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 524 0.40% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 121 0.09% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 23 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 39 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.01% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 43 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 23 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 425 0.33% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 36 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 42 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 37 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 35 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61522 # Writes before turning the bus around for reads -system.physmem.totQLat 31530968444 # Total ticks spent queuing -system.physmem.totMemAccLat 55349205944 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6351530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24821.55 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 129462 # Writes before turning the bus around for reads +system.physmem.totQLat 61876185756 # Total ticks spent queuing +system.physmem.totMemAccLat 108132979506 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 12335145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25081.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43571.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.56 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43831.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.31 # Average write queue length when enqueuing -system.physmem.readRowHits 1047361 # Number of row buffer hits during reads -system.physmem.writeRowHits 815697 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.94 # Row buffer hit rate for writes -system.physmem.avgGap 21864788.20 # Average gap between requests -system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1828287720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 997577625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4889757600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3480388560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1226219398425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29718601656750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34308233025720 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.467372 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49439480717043 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713811840000 # Time in different power states +system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing +system.physmem.readRowHits 2056722 # Number of row buffer hits during reads +system.physmem.writeRowHits 1654173 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.81 # Row buffer hit rate for writes +system.physmem.avgGap 11083878.27 # Average gap between requests +system.physmem.pageHitRate 79.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3550765680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1937421750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 9523885800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 7046332560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1313489115900 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29785116936750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34488454558920 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.871313 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49548907375208 # Time in different power states +system.physmem_0.memoryStateTime::REF 1721774080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 170428636707 # Time in different power states +system.physmem_0.memoryStateTime::ACT 291487862292 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1810756080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 988011750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5018598000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3479837760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1228704019020 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29716422156750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34308639338400 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.475289 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49435820968594 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713811840000 # Time in different power states +system.physmem_1.actEnergy 3541066200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1932129375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 9718893600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 7092645120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1316895447015 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29782128927000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34489099208790 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.883816 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49543906734220 # Time in different power states +system.physmem_1.memoryStateTime::REF 1721774080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 174088371406 # Time in different power states +system.physmem_1.memoryStateTime::ACT 296486485780 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -340,15 +337,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 225557622 # Number of BP lookups -system.cpu.branchPred.condPredicted 150824960 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12221670 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159273353 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104130221 # Number of BTB hits +system.cpu.branchPred.lookups 288825634 # Number of BP lookups +system.cpu.branchPred.condPredicted 198097109 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13566789 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 207338959 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136913226 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.378307 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30957399 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 344598 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 66.033526 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37451224 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 402112 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -379,45 +376,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 199616 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 199616 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 199616 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 199616 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 199616 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walks 346524 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 346524 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 346524 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 346524 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 346524 # Table walker wait (enqueue to first request) latency system.cpu.checker.dtb.walker.walksPending::samples 1622408500 # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::0 1622408500 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::total 1622408500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 155025 91.25% 91.25% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 14865 8.75% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 169890 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 199616 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkPageSizes::4K 271954 90.33% 90.33% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 29125 9.67% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 301079 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 346524 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 199616 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 169890 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 346524 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 301079 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 169890 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 369506 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 301079 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 647603 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 160527490 # DTB read hits -system.cpu.checker.dtb.read_misses 148526 # DTB read misses -system.cpu.checker.dtb.write_hits 145616651 # DTB write hits -system.cpu.checker.dtb.write_misses 51090 # DTB write misses -system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.checker.dtb.read_hits 204557812 # DTB read hits +system.cpu.checker.dtb.read_misses 253438 # DTB read misses +system.cpu.checker.dtb.write_hits 188384851 # DTB write hits +system.cpu.checker.dtb.write_misses 93086 # DTB write misses +system.cpu.checker.dtb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 72318 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 87812 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 7517 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 10297 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 19125 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 160676016 # DTB read accesses -system.cpu.checker.dtb.write_accesses 145667741 # DTB write accesses +system.cpu.checker.dtb.perms_faults 24573 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 204811250 # DTB read accesses +system.cpu.checker.dtb.write_accesses 188477937 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 306144141 # DTB hits -system.cpu.checker.dtb.misses 199616 # DTB misses -system.cpu.checker.dtb.accesses 306343757 # DTB accesses +system.cpu.checker.dtb.hits 392942663 # DTB hits +system.cpu.checker.dtb.misses 346524 # DTB misses +system.cpu.checker.dtb.accesses 393289187 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -447,46 +444,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 120521 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 120521 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 120521 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 120521 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 120521 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walks 130770 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 130770 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 130770 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 130770 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 130770 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walksPending::samples 1621807000 # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::0 1621807000 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::total 1621807000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 108578 98.83% 98.83% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1286 1.17% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 109864 # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::4K 116506 98.90% 98.90% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1293 1.10% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 117799 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120521 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120521 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 130770 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 130770 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109864 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109864 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 230385 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 853734937 # ITB inst hits -system.cpu.checker.itb.inst_misses 120521 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 117799 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 117799 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 248569 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 1104906556 # ITB inst hits +system.cpu.checker.itb.inst_misses 130770 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 52057 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 60682 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 853855458 # ITB inst accesses -system.cpu.checker.itb.hits 853734937 # DTB hits -system.cpu.checker.itb.misses 120521 # DTB misses -system.cpu.checker.itb.accesses 853855458 # DTB accesses -system.cpu.checker.numCycles 1003246954 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 1105037326 # ITB inst accesses +system.cpu.checker.itb.hits 1104906556 # DTB hits +system.cpu.checker.itb.misses 130770 # DTB misses +system.cpu.checker.itb.accesses 1105037326 # DTB accesses +system.cpu.checker.numCycles 1298799784 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -518,87 +515,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 951838 # Table walker walks requested -system.cpu.dtb.walker.walksLong 951838 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16475 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156308 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 435006 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 516832 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 1986.510123 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-32767 508349 98.36% 98.36% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-65535 5443 1.05% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-98303 1244 0.24% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::98304-131071 1085 0.21% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-163839 165 0.03% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::163840-196607 178 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-229375 121 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::229376-262143 54 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-294911 95 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::294912-327679 7 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-360447 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::360448-393215 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-425983 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::425984-458751 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 516832 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 485267 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 475094 97.90% 97.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 9290 1.91% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 546 0.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 199 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 82 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 20 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 485267 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 776250627376 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.722476 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.519579 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 774163165376 99.73% 99.73% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1120728500 0.14% 99.88% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 435636500 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 187638500 0.02% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 148036000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 113935000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 26323500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 52542500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2621500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 776250627376 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 156309 90.46% 90.46% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16475 9.54% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 172784 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 1430156 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1430156 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30793 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273791 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 677378 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 752778 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2375.228819 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 746726 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4359 0.58% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 685 0.09% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 394 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 311 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 120 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 171 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 752778 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 802636 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 783977 97.68% 97.68% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 16023 2.00% 99.67% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1555 0.19% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 316 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 129 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 37 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 22 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 802636 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1044763922448 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.739319 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.520240 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1040800473448 99.62% 99.62% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2579873000 0.25% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 637994000 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 271834500 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 201274500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 132884500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 46819000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 89469000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3255500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 45000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1044763922448 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 273792 89.89% 89.89% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 30793 10.11% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 304585 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1430156 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951838 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172784 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1430156 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304585 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172784 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1124622 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304585 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1734741 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 170417440 # DTB read hits -system.cpu.dtb.read_misses 677013 # DTB read misses -system.cpu.dtb.write_hits 148384109 # DTB write hits -system.cpu.dtb.write_misses 274825 # DTB write misses -system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 217117628 # DTB read hits +system.cpu.dtb.read_misses 1002788 # DTB read misses +system.cpu.dtb.write_hits 192115888 # DTB write hits +system.cpu.dtb.write_misses 427368 # DTB write misses +system.cpu.dtb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72556 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 87986 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10696 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 15675 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 70061 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171094453 # DTB read accesses -system.cpu.dtb.write_accesses 148658934 # DTB write accesses +system.cpu.dtb.perms_faults 85972 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 218120416 # DTB read accesses +system.cpu.dtb.write_accesses 192543256 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 318801549 # DTB hits -system.cpu.dtb.misses 951838 # DTB misses -system.cpu.dtb.accesses 319753387 # DTB accesses +system.cpu.dtb.hits 409233516 # DTB hits +system.cpu.dtb.misses 1430156 # DTB misses +system.cpu.dtb.accesses 410663672 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -628,877 +622,877 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 162167 # Table walker walks requested -system.cpu.itb.walker.walksLong 162167 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 122178 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17760 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144407 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1087.128740 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 7079.961036 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143546 99.40% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 491 0.34% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 245 0.17% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 86 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 177415 # Table walker walks requested +system.cpu.itb.walker.walksLong 177415 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1441 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 130680 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 19804 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 157611 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1499.045117 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 10189.386950 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 155888 98.91% 98.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 579 0.37% 99.27% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 739 0.47% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 292 0.19% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 35 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 38 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144407 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 141371 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27408.566821 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 138940 98.28% 98.28% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2106 1.49% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 209 0.15% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 62 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 157611 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 151925 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29463.087050 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 146250 96.26% 96.26% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 4800 3.16% 99.42% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 534 0.35% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 196 0.13% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 80 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 44 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 15 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 141371 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 655988501088 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.936740 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.243710 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 41542191152 6.33% 6.33% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 614402729936 93.66% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 43110500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 467500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 151925 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 920206753364 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.948994 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.220270 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 46987798652 5.11% 5.11% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 873167595712 94.89% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 50573500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 783500 0.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 655988501088 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 122178 98.84% 98.84% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 123611 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 920206753364 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 130680 98.91% 98.91% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1441 1.09% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 132121 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162167 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 162167 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177415 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 177415 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123611 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 123611 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 285778 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 358625455 # ITB inst hits -system.cpu.itb.inst_misses 162167 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 132121 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 132121 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 309536 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 461294711 # ITB inst hits +system.cpu.itb.inst_misses 177415 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53363 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 62159 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372145 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 458083 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 358787622 # ITB inst accesses -system.cpu.itb.hits 358625455 # DTB hits -system.cpu.itb.misses 162167 # DTB misses -system.cpu.itb.accesses 358787622 # DTB accesses -system.cpu.numCycles 1590418745 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 461472126 # ITB inst accesses +system.cpu.itb.hits 461294711 # DTB hits +system.cpu.itb.misses 177415 # DTB misses +system.cpu.itb.accesses 461472126 # DTB accesses +system.cpu.numCycles 2141240199 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 646410999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1006402404 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225557622 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135087620 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 866562323 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26107474 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3678311 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 25439 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9275413 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1023850 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 676 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 358236204 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6112300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 49056 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1540030748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.765724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.157325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 785638694 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1289733601 # Number of instructions fetch has processed +system.cpu.fetch.Branches 288825634 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174364450 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1267374465 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29210356 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4418623 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12152128 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1217886 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 633 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 460817774 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6728045 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 53516 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2085435848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.725171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.139838 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 979927440 63.63% 63.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215057699 13.96% 77.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70955696 4.61% 82.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 274089913 17.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1366680941 65.53% 65.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 278589155 13.36% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 86788366 4.16% 83.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 353377386 16.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1540030748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.141823 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632791 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 525466953 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 519947088 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 434864784 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50506307 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9245616 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33796734 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3867997 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1090931528 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29050280 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9245616 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 570424085 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50840114 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 363017689 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 440398811 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 106104433 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1071115355 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6801917 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5040663 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 343395 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 645255 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 54344412 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20434 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1018974666 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1651092433 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1266893179 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1473696 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 953236782 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65737881 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27206823 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23528426 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 103688094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 174464093 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 151959443 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9931077 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9032567 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1035787653 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27506074 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1051526043 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3293799 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60619533 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33780075 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 314140 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1540030748 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.682795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.925415 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2085435848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.134887 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.602330 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 612239538 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 852574124 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 529946172 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80118083 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10557931 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41219534 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4107385 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1403247413 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32566835 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10557931 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 674962554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 85247440 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 550746700 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 547461697 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 216459526 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1379612307 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 7971383 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7360618 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 963827 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1074082 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 133209723 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22971 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1329803577 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2195861380 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1637517470 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1437183 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1251935276 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 77868298 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43546894 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39087703 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 166786807 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 221659276 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 196613901 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12565776 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11015266 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1326936815 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 43849103 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1356961205 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4098709 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 72699747 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41430931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 372473 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2085435848 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.650685 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.914510 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 888949202 57.72% 57.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 336251490 21.83% 79.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 235798342 15.31% 94.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72468185 4.71% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6544331 0.42% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19198 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1239320860 59.43% 59.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 449936886 21.58% 81.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 291017288 13.95% 94.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 95682212 4.59% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9449903 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28699 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1540030748 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2085435848 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58035888 35.01% 35.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 99674 0.06% 35.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26738 0.02% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 574 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44566242 26.88% 61.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63041416 38.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 73477453 34.17% 34.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90486 0.04% 34.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26768 0.01% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 385 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 57876005 26.91% 61.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83594438 38.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 724142674 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2543730 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122779 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 376 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121012 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 174312709 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150282706 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 937288786 69.07% 69.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2936989 0.22% 69.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 129444 0.01% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 114407 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 221949724 16.36% 85.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194541406 14.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1051526043 # Type of FU issued -system.cpu.iq.rate 0.661163 # Inst issue rate -system.cpu.iq.fu_busy_cnt 165770532 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157648 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3809671307 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1123107931 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1033541701 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2475857 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 947397 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 910004 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1215741366 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1555198 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4333965 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1356961205 # Type of FU issued +system.cpu.iq.rate 0.633727 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215065535 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.158491 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5016097714 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1442740685 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1335189379 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2424787 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 927446 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 888349 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1570502436 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1524273 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5709357 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13839303 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14833 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143349 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6338712 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16902439 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24350 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 184211 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8196884 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2540349 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1552925 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3577769 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1870440 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9245616 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6389360 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5797347 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1063516239 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10557931 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12374030 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7706525 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1371058602 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 174464093 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 151959443 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23100216 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59008 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5663632 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143349 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3667729 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5111764 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8779493 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1040328227 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 170406440 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10257681 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 221659276 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 196613901 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 38550114 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178028 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7343410 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 184211 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4239042 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5703306 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 9942348 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1343677933 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 217120223 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11882036 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222512 # number of nop insts executed -system.cpu.iew.exec_refs 318786335 # number of memory reference insts executed -system.cpu.iew.exec_branches 197400349 # Number of branches executed -system.cpu.iew.exec_stores 148379895 # Number of stores executed -system.cpu.iew.exec_rate 0.654122 # Inst execution rate -system.cpu.iew.wb_sent 1035262700 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1034451705 # cumulative count of insts written-back -system.cpu.iew.wb_producers 440415620 # num instructions producing a value -system.cpu.iew.wb_consumers 712619707 # num instructions consuming a value +system.cpu.iew.exec_nop 272684 # number of nop insts executed +system.cpu.iew.exec_refs 409245203 # number of memory reference insts executed +system.cpu.iew.exec_branches 255119365 # Number of branches executed +system.cpu.iew.exec_stores 192124980 # Number of stores executed +system.cpu.iew.exec_rate 0.627523 # Inst execution rate +system.cpu.iew.wb_sent 1337102879 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1336077728 # cumulative count of insts written-back +system.cpu.iew.wb_producers 573421420 # num instructions producing a value +system.cpu.iew.wb_consumers 940568778 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.650427 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618023 # average fanout of values written-back +system.cpu.iew.wb_rate 0.623974 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.609654 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51498978 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27191934 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8413549 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1528028900 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.656188 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.286676 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 62140410 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 43476630 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9519542 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2071346493 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.626687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.267080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1013092181 66.30% 66.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 289858237 18.97% 85.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121052617 7.92% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36682667 2.40% 95.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28563883 1.87% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14105791 0.92% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8655946 0.57% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4198069 0.27% 99.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11819509 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1395640231 67.38% 67.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 393909449 19.02% 86.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150461425 7.26% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44316735 2.14% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35977476 1.74% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18232281 0.88% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10892931 0.53% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5452952 0.26% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16463013 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1528028900 # Number of insts commited each cycle -system.cpu.commit.committedInsts 853325819 # Number of instructions committed -system.cpu.commit.committedOps 1002674190 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2071346493 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1104366834 # Number of instructions committed +system.cpu.commit.committedOps 1298086167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 306245520 # Number of memory references committed -system.cpu.commit.loads 160624789 # Number of loads committed -system.cpu.commit.membars 6977905 # Number of memory barriers committed -system.cpu.commit.branches 190474151 # Number of branches committed -system.cpu.commit.fp_insts 896785 # Number of committed floating point instructions. -system.cpu.commit.int_insts 921116747 # Number of committed integer instructions. -system.cpu.commit.function_calls 25400785 # Number of function calls committed. +system.cpu.commit.refs 393173853 # Number of memory references committed +system.cpu.commit.loads 204756836 # Number of loads committed +system.cpu.commit.membars 9104821 # Number of memory barriers committed +system.cpu.commit.branches 246834909 # Number of branches committed +system.cpu.commit.fp_insts 874964 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1186447841 # Number of committed integer instructions. +system.cpu.commit.function_calls 30876862 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 694059947 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2158876 0.22% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98131 0.01% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111674 0.01% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 160624789 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 145620731 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 902159630 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2542825 0.20% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 103949 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105868 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 204756836 15.77% 85.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 188417017 14.51% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1002674190 # Class of committed instruction -system.cpu.commit.bw_lim_events 11819509 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2562796067 # The number of ROB reads -system.cpu.rob.rob_writes 2120254358 # The number of ROB writes -system.cpu.timesIdled 8129447 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50387997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101057024238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 853325819 # Number of Instructions Simulated -system.cpu.committedOps 1002674190 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.863788 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.863788 # CPI: Total CPI of All Threads -system.cpu.ipc 0.536542 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.536542 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1231590969 # number of integer regfile reads -system.cpu.int_regfile_writes 735370650 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462122 # number of floating regfile reads -system.cpu.fp_regfile_writes 782688 # number of floating regfile writes -system.cpu.cc_regfile_reads 226859046 # number of cc regfile reads -system.cpu.cc_regfile_writes 227515194 # number of cc regfile writes -system.cpu.misc_regfile_reads 2534481060 # number of misc regfile reads -system.cpu.misc_regfile_writes 27245755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9758519 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983709 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 284707567 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9759031 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.173754 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 1298086167 # Class of committed instruction +system.cpu.commit.bw_lim_events 16463013 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3405665880 # The number of ROB reads +system.cpu.rob.rob_writes 2734432791 # The number of ROB writes +system.cpu.timesIdled 9009507 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 55804351 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100983102115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1104366834 # Number of Instructions Simulated +system.cpu.committedOps 1298086167 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.938885 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.938885 # CPI: Total CPI of All Threads +system.cpu.ipc 0.515760 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.515760 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1596434625 # number of integer regfile reads +system.cpu.int_regfile_writes 940526506 # number of integer regfile writes +system.cpu.fp_regfile_reads 1424965 # number of floating regfile reads +system.cpu.fp_regfile_writes 765828 # number of floating regfile writes +system.cpu.cc_regfile_reads 311708448 # number of cc regfile reads +system.cpu.cc_regfile_writes 312593649 # number of cc regfile writes +system.cpu.misc_regfile_reads 3410532874 # number of misc regfile reads +system.cpu.misc_regfile_writes 44362921 # number of misc regfile writes +system.cpu.dcache.tags.replacements 13614186 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983787 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 360288791 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13614698 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.463223 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983709 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983787 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1243872376 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1243872376 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 147964440 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147964440 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128940955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128940955 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 380183 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 380183 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 324678 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 324678 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3327415 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3327415 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3725844 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3725844 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 276905395 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 276905395 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 277285578 # number of overall hits -system.cpu.dcache.overall_hits::total 277285578 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9612542 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9612542 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11385353 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11385353 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1184834 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1184834 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1232047 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1232047 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 450033 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 450033 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1595334423 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1595334423 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 186468319 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 186468319 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 162903680 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 162903680 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 463393 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 463393 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 334025 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 334025 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4787397 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4787397 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5271269 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5271269 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 349371999 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 349371999 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 349835392 # number of overall hits +system.cpu.dcache.overall_hits::total 349835392 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12723000 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12723000 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18625078 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18625078 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2035956 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2035956 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1270469 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1270469 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 547335 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 547335 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20997895 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20997895 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22182729 # number of overall misses -system.cpu.dcache.overall_misses::total 22182729 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 144669003500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 330867751444 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 63675897168 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 63675897168 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6433485000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6433485000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 31348078 # number of demand (read+write) misses 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number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 251000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 475536754944 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 475536754944 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 475536754944 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 475536754944 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 157576982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 157576982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 140326308 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 140326308 # number of WriteReq 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# average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_latency::cpu.data 1182718575621 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1182718575621 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1182718575621 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1182718575621 # number of overall miss cycles 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accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032649 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752773 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752773 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786888 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786888 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061107 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061107 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 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-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 254057212172 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 286430230672 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829096500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829096500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5708243467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5708243467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11537339967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11537339967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016978 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016978 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.811901 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.811901 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787350 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787350 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053223 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053223 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031648 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031648 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780 # average WriteReq mshr uncacheable latency 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+system.cpu.icache.tags.sampled_refs 16757054 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.450785 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.944879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999892 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 511.945135 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999893 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 373257734 # Number of tag accesses -system.cpu.icache.tags.data_accesses 373257734 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 342405629 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 342405629 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 342405629 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 342405629 # number of demand (read+write) hits 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208403044384 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208403044384 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 358214908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 358214908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 358214908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 358214908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 358214908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 358214908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044134 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044134 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044134 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044134 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044134 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044134 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13182.324405 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13182.324405 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 15030 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 477553750 # Number of tag accesses +system.cpu.icache.tags.data_accesses 477553750 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 443237235 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 443237235 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 443237235 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 443237235 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 443237235 # number of overall hits +system.cpu.icache.overall_hits::total 443237235 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17559241 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17559241 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17559241 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17559241 # number of demand (read+write) misses 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demand (read+write) accesses +system.cpu.icache.demand_accesses::total 460796476 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 460796476 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 460796476 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038106 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.038106 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.038106 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.038106 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.038106 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.038106 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13220.446937 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13220.446937 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13220.446937 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 15959 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1210 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1225 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 12.421488 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.027755 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 766453 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 766453 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 766453 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 766453 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 766453 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 766453 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15042826 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15042826 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15042826 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15042826 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15042826 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15042826 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 801966 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 801966 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 801966 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 801966 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 801966 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 801966 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16757275 # number of ReadReq MSHR misses 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uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12052321000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011427 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785148 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785148 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787568 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787568 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005596 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.402131 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.402131 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030479 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030479 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.432327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.432327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045172 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045172 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.467465 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.467465 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for demand accesses 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78619.287068 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency 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mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1633565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23227278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8622904 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 17438576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 44010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2244083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28317103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 12480720 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 20347986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 60667 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 44017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1983984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1983984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15042826 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6558947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1331632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1224968 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45167572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29499463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 732865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1940611 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77340511 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 963068272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1029563294 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2422088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6336984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2001390638 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1864369 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 52693428 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.056141 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.230194 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 60674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3036433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3036433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16757275 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9323830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1369962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1263298 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50310988 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41099763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 807461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3043712 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 95261924 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1072793136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1449869810 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2707560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10589056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2535959562 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3104722 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 65657900 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.072586 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.259455 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 49735173 94.39% 94.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2958255 5.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 60892075 92.74% 92.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 4765825 7.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 52693428 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 33222815494 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 65657900 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 41856500497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1182000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22592032956 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25164199957 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13487423434 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19241199390 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 430634727 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 469526277 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1148958035 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1720822991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40295 # Transaction distribution -system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.iobus.trans_dist::ReadReq 40298 # Transaction distribution +system.iobus.trans_dist::ReadResp 40298 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1713,11 +1707,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1734,11 +1728,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1767,71 +1761,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568813596 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568892559 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147714000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.423947 # Cycle average of tags in use +system.iocache.tags.replacements 115458 # number of replacements +system.iocache.tags.tagsinuse 10.449705 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13095311635000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544418 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879529 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429971 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651497 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13095311633000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.528028 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.921676 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220502 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432605 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653107 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039623 # Number of tag accesses -system.iocache.tags.data_accesses 1039623 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8810 # number of demand (read+write) misses -system.iocache.demand_misses::total 8850 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8810 # number of overall misses -system.iocache.overall_misses::total 8850 # number of overall misses +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1621911166 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1626980166 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1615020135 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1620089135 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12610487430 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12610487430 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12610143424 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12610143424 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1621911166 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1627331166 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1615020135 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1620440135 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1621911166 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1627331166 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1615020135 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1620440135 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8810 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8850 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8810 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8850 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1846,54 +1840,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183901.906409 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183060.919209 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183879.227797 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183038.533266 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183879.227797 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31681 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183038.533266 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31319 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3345 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.471151 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.276955 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8810 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8850 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8810 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8850 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1181411166 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1184630166 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174370135 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1177589135 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277287430 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7277287430 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7276943424 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7276943424 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1181411166 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1184831166 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1174370135 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1177790135 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1181411166 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1184831166 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1174370135 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1177790135 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1908,72 +1902,72 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54973 # Transaction distribution -system.membus.trans_dist::ReadResp 407867 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::Writeback 1073811 # Transaction distribution -system.membus.trans_dist::CleanEvict 187846 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35358 # Transaction distribution +system.membus.trans_dist::ReadReq 54987 # Transaction distribution +system.membus.trans_dist::ReadResp 601962 # Transaction distribution +system.membus.trans_dist::WriteReq 33703 # Transaction distribution +system.membus.trans_dist::WriteResp 33703 # Transaction distribution +system.membus.trans_dist::Writeback 2181638 # Transaction distribution +system.membus.trans_dist::CleanEvict 277040 # Transaction distribution +system.membus.trans_dist::UpgradeReq 48552 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35361 # Transaction distribution -system.membus.trans_dist::ReadExReq 899707 # Transaction distribution -system.membus.trans_dist::ReadExResp 899707 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 352894 # Transaction distribution +system.membus.trans_dist::UpgradeResp 48555 # Transaction distribution +system.membus.trans_dist::ReadExReq 1902507 # Transaction distribution +system.membus.trans_dist::ReadExResp 1902507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 546975 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3753956 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3883578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4225292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7371150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7500814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341657 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341657 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7842471 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 141818700 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 141988686 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7244096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7244096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 149232782 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2955 # Total snoops (count) -system.membus.snoop_fanout::samples 2747442 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 289319820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 289489890 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7242112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 296732002 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2989 # Total snoops (count) +system.membus.snoop_fanout::samples 5154600 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2747442 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5154600 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2747442 # Request fanout histogram -system.membus.reqLayer0.occupancy 104159500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5154600 # Request fanout histogram +system.membus.reqLayer0.occupancy 104456000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5443500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5495500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7279924206 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14230820482 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6776038462 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13100845399 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228860056 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228852771 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1984,11 +1978,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2017,17 +2011,17 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16150 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 20008 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini index def82d401..cd4c4065f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -201,7 +201,7 @@ instShiftAmt=2 numThreads=1 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -542,7 +542,7 @@ opLat=4 pipelined=true [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -652,7 +652,7 @@ sys=system port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -835,7 +835,7 @@ instShiftAmt=2 numThreads=1 [system.cpu1.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -1176,7 +1176,7 @@ opLat=4 pipelined=true [system.cpu1.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -1286,7 +1286,7 @@ sys=system port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -1399,7 +1399,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1434,7 +1434,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1849,9 +1849,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr index 4c70e8d66..ebddc1020 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr @@ -11,3 +11,5 @@ warn: allocating bonus target for snoop warn: allocating bonus target for snoop warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: allocating bonus target for snoop +warn: allocating bonus target for snoop diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout index 0fe5c8030..b9e9b0535 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 11:05:08 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 14 2015 23:59:20 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47309826639000 because m5_exit instruction encountered +Exiting @ tick 47309815475000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 6bf45e0f6..9055480cb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.309827 # Number of seconds simulated -sim_ticks 47309826639000 # Number of ticks simulated -final_tick 47309826639000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.309815 # Number of seconds simulated +sim_ticks 47309815475000 # Number of ticks simulated +final_tick 47309815475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115168 # Simulator instruction rate (inst/s) -host_op_rate 135435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5759542779 # Simulator tick rate (ticks/s) -host_mem_usage 728780 # Number of bytes of host memory used -host_seconds 8214.16 # Real time elapsed on the host -sim_insts 946011818 # Number of instructions simulated -sim_ops 1112485532 # Number of ops (including micro ops) simulated +host_inst_rate 80227 # Simulator instruction rate (inst/s) +host_op_rate 94350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4125416978 # Simulator tick rate (ticks/s) +host_mem_usage 770696 # Number of bytes of host memory used +host_seconds 11467.89 # Real time elapsed on the host +sim_insts 920033396 # Number of instructions simulated +sim_ops 1081995375 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 184448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 167936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 5084832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 44767048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 19339456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 176320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 161792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2535456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 18891728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 20722048 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 420544 # Number of bytes read from this memory -system.physmem.bytes_read::total 112451608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 5084832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2535456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7620288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 93755328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 174848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 152512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4545760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 43325128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 19040640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 136192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 127232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2550688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 17518992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 15564544 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439744 # Number of bytes read from this memory +system.physmem.bytes_read::total 103576280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4545760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2550688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7096448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 86607680 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 93775912 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2624 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 95403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 699498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 302179 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2755 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2528 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39660 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 295196 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 323782 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1773078 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1464927 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 86628264 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2732 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 676968 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 297510 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2128 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 273747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 243196 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6871 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1634401 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1353245 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1467501 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 107479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 946253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 408783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 399319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 438007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2376919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 107479 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 161072 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1981731 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1355819 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 96085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 915775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 402467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2689 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 370304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 328992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2189319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 96085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 149999 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1830649 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1982166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1981731 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 107479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 946688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 408783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 399319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 438007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4359084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1773078 # Number of read requests accepted -system.physmem.writeReqs 1467501 # Number of write requests accepted -system.physmem.readBursts 1773078 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1467501 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 113443520 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue -system.physmem.bytesWritten 93774528 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 112451608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 93775912 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1831084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1830649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 96085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 916210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 402467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2689 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 370304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 328992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4020403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1634401 # Number of read requests accepted +system.physmem.writeReqs 1355819 # Number of write requests accepted +system.physmem.readBursts 1634401 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1355819 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 104570688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue +system.physmem.bytesWritten 86627008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 103576280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 86628264 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 224875 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 113386 # Per bank write bursts -system.physmem.perBankRdBursts::1 120644 # Per bank write bursts -system.physmem.perBankRdBursts::2 108661 # Per bank write bursts -system.physmem.perBankRdBursts::3 115173 # Per bank write bursts -system.physmem.perBankRdBursts::4 103078 # Per bank write bursts -system.physmem.perBankRdBursts::5 114921 # Per bank write bursts -system.physmem.perBankRdBursts::6 108340 # Per bank write bursts -system.physmem.perBankRdBursts::7 105879 # Per bank write bursts -system.physmem.perBankRdBursts::8 98747 # Per bank write bursts -system.physmem.perBankRdBursts::9 127278 # Per bank write bursts -system.physmem.perBankRdBursts::10 99197 # Per bank write bursts -system.physmem.perBankRdBursts::11 111650 # Per bank write bursts -system.physmem.perBankRdBursts::12 107228 # Per bank write bursts -system.physmem.perBankRdBursts::13 113583 # Per bank write bursts -system.physmem.perBankRdBursts::14 112177 # Per bank write bursts -system.physmem.perBankRdBursts::15 112613 # Per bank write bursts -system.physmem.perBankWrBursts::0 94420 # Per bank write bursts -system.physmem.perBankWrBursts::1 97266 # Per bank write bursts -system.physmem.perBankWrBursts::2 90974 # Per bank write bursts -system.physmem.perBankWrBursts::3 94616 # Per bank write bursts -system.physmem.perBankWrBursts::4 87287 # Per bank write bursts -system.physmem.perBankWrBursts::5 94599 # Per bank write bursts -system.physmem.perBankWrBursts::6 89304 # Per bank write bursts -system.physmem.perBankWrBursts::7 90590 # Per bank write bursts -system.physmem.perBankWrBursts::8 84448 # Per bank write bursts -system.physmem.perBankWrBursts::9 90113 # Per bank write bursts -system.physmem.perBankWrBursts::10 85465 # Per bank write bursts -system.physmem.perBankWrBursts::11 93225 # Per bank write bursts -system.physmem.perBankWrBursts::12 88655 # Per bank write bursts -system.physmem.perBankWrBursts::13 95246 # Per bank write bursts -system.physmem.perBankWrBursts::14 93025 # Per bank write bursts -system.physmem.perBankWrBursts::15 95994 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 224542 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 101664 # Per bank write bursts +system.physmem.perBankRdBursts::1 108898 # Per bank write bursts +system.physmem.perBankRdBursts::2 93497 # Per bank write bursts +system.physmem.perBankRdBursts::3 100406 # Per bank write bursts +system.physmem.perBankRdBursts::4 99202 # Per bank write bursts +system.physmem.perBankRdBursts::5 111502 # Per bank write bursts +system.physmem.perBankRdBursts::6 102695 # Per bank write bursts +system.physmem.perBankRdBursts::7 105017 # Per bank write bursts +system.physmem.perBankRdBursts::8 95660 # Per bank write bursts +system.physmem.perBankRdBursts::9 119055 # Per bank write bursts +system.physmem.perBankRdBursts::10 95976 # Per bank write bursts +system.physmem.perBankRdBursts::11 99461 # Per bank write bursts +system.physmem.perBankRdBursts::12 97685 # Per bank write bursts +system.physmem.perBankRdBursts::13 98791 # Per bank write bursts +system.physmem.perBankRdBursts::14 102404 # Per bank write bursts +system.physmem.perBankRdBursts::15 102004 # Per bank write bursts +system.physmem.perBankWrBursts::0 83138 # Per bank write bursts +system.physmem.perBankWrBursts::1 88505 # Per bank write bursts +system.physmem.perBankWrBursts::2 79517 # Per bank write bursts +system.physmem.perBankWrBursts::3 83751 # Per bank write bursts +system.physmem.perBankWrBursts::4 82730 # Per bank write bursts +system.physmem.perBankWrBursts::5 91993 # Per bank write bursts +system.physmem.perBankWrBursts::6 85763 # Per bank write bursts +system.physmem.perBankWrBursts::7 87476 # Per bank write bursts +system.physmem.perBankWrBursts::8 80354 # Per bank write bursts +system.physmem.perBankWrBursts::9 84626 # Per bank write bursts +system.physmem.perBankWrBursts::10 82451 # Per bank write bursts +system.physmem.perBankWrBursts::11 83951 # Per bank write bursts +system.physmem.perBankWrBursts::12 82076 # Per bank write bursts +system.physmem.perBankWrBursts::13 85332 # Per bank write bursts +system.physmem.perBankWrBursts::14 85178 # Per bank write bursts +system.physmem.perBankWrBursts::15 86706 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 83 # Number of times write queue was full causing retry -system.physmem.totGap 47309825190500 # Total gap between requests +system.physmem.numWrRetry 54 # Number of times write queue was full causing retry +system.physmem.totGap 47309813973500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1751720 # Read request sizes (log2) +system.physmem.readPktSize::6 1613043 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1464927 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 608524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 449703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 194607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 195607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 116312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 71048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 40112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 36551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 32712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 10303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 5634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1353245 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 578892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 412924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 179105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 178845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 107013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 63608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 8546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,170 +188,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 23447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 53186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 72210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 82749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 88726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 95528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 97547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 101638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 103246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 108748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 123417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 115282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 109625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 98032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 19221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 22339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 41881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 50025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 77253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 82334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 88348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 89969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 94025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 94875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 99373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 112446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 104983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 99994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 89665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 136 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 281 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1119709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 185.063798 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 114.156365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.940793 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 674939 60.28% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 219039 19.56% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 70659 6.31% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 37987 3.39% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28223 2.52% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 14545 1.30% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15798 1.41% 94.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9595 0.86% 95.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 48924 4.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1119709 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 84177 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.057367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 250.150754 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 84175 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 146 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1028414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 185.914855 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 114.442896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.413322 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 618503 60.14% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 202037 19.65% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 65034 6.32% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35244 3.43% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24806 2.41% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13355 1.30% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14362 1.40% 94.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8867 0.86% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46206 4.49% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1028414 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 77347 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.124284 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 260.957500 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 77345 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 84177 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 84177 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.406501 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.998569 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.063432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 78913 93.75% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2654 3.15% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 594 0.71% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 256 0.30% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 356 0.42% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 499 0.59% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 111 0.13% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 36 0.04% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 47 0.06% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 28 0.03% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 36 0.04% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 26 0.03% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 418 0.50% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 37 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 46 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 46 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 77347 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 77347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.499670 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.056595 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.288618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 72278 93.45% 93.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2489 3.22% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 567 0.73% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 275 0.36% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 300 0.39% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 491 0.63% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 126 0.16% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 49 0.06% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 40 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 44 0.06% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 35 0.05% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 27 0.03% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 405 0.52% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 43 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 50 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 52 0.07% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 16 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 23 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 84177 # Writes before turning the bus around for reads -system.physmem.totQLat 95142418476 # Total ticks spent queuing -system.physmem.totMemAccLat 128377824726 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8862775000 # Total ticks spent in databus transfers -system.physmem.avgQLat 53675.30 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::148-151 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 77347 # Writes before turning the bus around for reads +system.physmem.totQLat 84737173288 # Total ticks spent queuing +system.physmem.totMemAccLat 115373117038 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8169585000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51861.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 72425.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.98 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70611.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing -system.physmem.readRowHits 1427545 # Number of row buffer hits during reads -system.physmem.writeRowHits 690525 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.13 # Row buffer hit rate for writes -system.physmem.avgGap 14599188.97 # Average gap between requests -system.physmem.pageHitRate 65.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4299372000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2345887500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6942631800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4789082880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3090047684880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1174100419575 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27355981545000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31638506623635 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.751312 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45508743621503 # Time in different power states -system.physmem_0.memoryStateTime::REF 1579778980000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.70 # Average write queue length when enqueuing +system.physmem.readRowHits 1319893 # Number of row buffer hits during reads +system.physmem.writeRowHits 639153 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.22 # Row buffer hit rate for writes +system.physmem.avgGap 15821516.13 # Average gap between requests +system.physmem.pageHitRate 65.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3982161960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2172806625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6418448400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4425017040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1165891095180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27363173363250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31636109560215 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.700864 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45520771842112 # Time in different power states +system.physmem_0.memoryStateTime::REF 1579778460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 221302763997 # Time in different power states +system.physmem_0.memoryStateTime::ACT 209258446888 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4165628040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2272912125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6883242600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4705588080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3090047684880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1168667714520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27360747075750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31637489845995 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.729820 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45516677078545 # Time in different power states -system.physmem_1.memoryStateTime::REF 1579778980000 # Time in different power states +system.physmem_1.actEnergy 3792625200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2069388750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6326026200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4345967520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1161508413915 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27367017820500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31635106909845 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.679671 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45527169156111 # Time in different power states +system.physmem_1.memoryStateTime::REF 1579778460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 213370138955 # Time in different power states +system.physmem_1.memoryStateTime::ACT 202865647889 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -385,15 +378,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 147637418 # Number of BP lookups -system.cpu0.branchPred.condPredicted 98315773 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7247820 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 103619610 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 67413734 # Number of BTB hits +system.cpu0.branchPred.lookups 147707110 # Number of BP lookups +system.cpu0.branchPred.condPredicted 98263896 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7114286 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 103765470 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 67713845 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.058857 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20080737 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 195189 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.256626 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20037326 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 200169 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -424,84 +417,90 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 596316 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 596316 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13005 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90766 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 267964 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 328352 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 1967.306427 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12140.663837 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 326191 99.34% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1511 0.46% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 485 0.15% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 70 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 71 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 17 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 575296 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 575296 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12884 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88904 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 257665 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 317631 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2022.074357 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12176.572384 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 315561 99.35% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1443 0.45% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 466 0.15% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 74 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 64 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 16 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 328352 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 293288 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 18414.921511 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15494.626324 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16461.439983 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 290000 98.88% 98.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2364 0.81% 99.68% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 368 0.13% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 346 0.12% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 119 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 72 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 12 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 293288 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 554812439744 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.594659 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.537153 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 553701545244 99.80% 99.80% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 589103000 0.11% 99.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 238633000 0.04% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 116174000 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 85227000 0.02% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 46829500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 15433000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 19112000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 363500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 19500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 554812439744 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90767 87.47% 87.47% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13005 12.53% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 103772 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 596316 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 317631 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 284896 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 18154.968831 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15325.984047 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16062.585690 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 269179 94.48% 94.48% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 12793 4.49% 98.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1124 0.39% 99.37% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 999 0.35% 99.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 121 0.04% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 154 0.05% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 275 0.10% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 60 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 49 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 59 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 25 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 23 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 18 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::491520-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 284896 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 550505269948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.606717 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.533946 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 549425097448 99.80% 99.80% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 576911000 0.10% 99.91% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 232215500 0.04% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 109337500 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 81684000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 43624500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 15920500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 20013500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 440500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 25500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 550505269948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 88905 87.34% 87.34% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 12884 12.66% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 101789 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 575296 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 596316 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 103772 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 575296 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101789 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 103772 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 700088 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101789 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 677085 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 107674804 # DTB read hits -system.cpu0.dtb.read_misses 416109 # DTB read misses -system.cpu0.dtb.write_hits 89240851 # DTB write hits -system.cpu0.dtb.write_misses 180207 # DTB write misses -system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 107498760 # DTB read hits +system.cpu0.dtb.read_misses 398450 # DTB read misses +system.cpu0.dtb.write_hits 89911233 # DTB write hits +system.cpu0.dtb.write_misses 176846 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37572 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 168 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7516 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36343 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 6513 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 38101 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 108090913 # DTB read accesses -system.cpu0.dtb.write_accesses 89421058 # DTB write accesses +system.cpu0.dtb.perms_faults 39209 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 107897210 # DTB read accesses +system.cpu0.dtb.write_accesses 90088079 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 196915655 # DTB hits -system.cpu0.dtb.misses 596316 # DTB misses -system.cpu0.dtb.accesses 197511971 # DTB accesses +system.cpu0.dtb.hits 197409993 # DTB hits +system.cpu0.dtb.misses 575296 # DTB misses +system.cpu0.dtb.accesses 197985289 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -531,326 +530,332 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 85428 # Table walker walks requested -system.cpu0.itb.walker.walksLong 85428 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 771 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61190 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10178 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 75250 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1283.993355 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 9203.446829 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 74460 98.95% 98.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 428 0.57% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 166 0.22% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 158 0.21% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 10 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 75250 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72139 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 23671.051720 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 20466.529400 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 20605.197168 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 70248 97.38% 97.38% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1514 2.10% 99.48% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 196 0.27% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 111 0.15% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 47 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72139 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 421639244068 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.834946 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.371382 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 69614918048 16.51% 16.51% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 352004823020 83.48% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 17379000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 2056500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 67500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 421639244068 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61190 98.76% 98.76% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 771 1.24% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 61961 # Table walker page sizes translated +system.cpu0.itb.walker.walks 88373 # Table walker walks requested +system.cpu0.itb.walker.walksLong 88373 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1010 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63733 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10354 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 78019 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1154.635409 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8302.318133 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 77325 99.11% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 373 0.48% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 149 0.19% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 144 0.18% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 78019 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 75097 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 22974.939079 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 20231.234781 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18518.097642 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 68416 91.10% 91.10% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 5120 6.82% 97.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 490 0.65% 98.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 809 1.08% 99.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 63 0.08% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 55 0.07% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 56 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 27 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 16 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 17 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 75097 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 413042823976 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.838558 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.368059 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 66699023100 16.15% 16.15% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 346328877376 83.85% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 13315500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1543000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 65000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 413042823976 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 63733 98.44% 98.44% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1010 1.56% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64743 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85428 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85428 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88373 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88373 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61961 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61961 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 147389 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 231535487 # ITB inst hits -system.cpu0.itb.inst_misses 85428 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64743 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64743 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 153116 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 231997623 # ITB inst hits +system.cpu0.itb.inst_misses 88373 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26943 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26272 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 216195 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 223051 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 231620915 # ITB inst accesses -system.cpu0.itb.hits 231535487 # DTB hits -system.cpu0.itb.misses 85428 # DTB misses -system.cpu0.itb.accesses 231620915 # DTB accesses -system.cpu0.numCycles 805724204 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 232085996 # ITB inst accesses +system.cpu0.itb.hits 231997623 # DTB hits +system.cpu0.itb.misses 88373 # DTB misses +system.cpu0.itb.accesses 232085996 # DTB accesses +system.cpu0.numCycles 807086065 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 95731684 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 652075833 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 147637418 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 87494471 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 667504198 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15546378 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1866411 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 305738 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6228904 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 744813 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 860245 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 231319013 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1833472 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28917 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 781015182 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.979576 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.220669 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 93861008 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 652896475 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 147707110 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 87751171 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 672171434 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15342460 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1905506 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 292447 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6425780 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 696882 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 817665 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 231773404 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1782410 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 29765 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 783841952 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.977378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.220143 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 414945915 53.13% 53.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 142136658 18.20% 71.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 48870776 6.26% 77.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 175061833 22.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 417241550 53.23% 53.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 142387565 18.17% 71.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 48916006 6.24% 77.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 175296831 22.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 781015182 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.183236 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.809304 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 113248081 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 377378437 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 245811555 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39067395 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5509714 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 21219272 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2308032 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 677494422 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 25172258 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5509714 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 150635102 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 57564950 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 243777898 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 246916319 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 76611199 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 659282826 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6463914 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10193503 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 302591 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 345572 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 40114273 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11761 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 627680154 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1013922393 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 779757811 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 794183 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 565536193 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 62143943 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16063927 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14023847 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 79290060 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 107984972 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 92881396 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9789553 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8248701 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 636103677 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16216212 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 639991449 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2906968 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 58559234 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 38038909 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 288402 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 781015182 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.819435 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.071222 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 783841952 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.183013 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.808955 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 111750908 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 381172853 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 246402586 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39053255 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5462350 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21288781 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2252861 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 678905918 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 24756446 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5462350 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 148938841 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 55630896 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 250198036 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 247704695 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 75907134 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 660737654 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6369939 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10029778 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 264844 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 301380 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 39545548 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 629064095 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1015658028 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 780465434 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 875541 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 567964584 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 61099508 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16110257 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14023115 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 79266160 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 107669777 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 93504359 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9663954 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8219387 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 637670623 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16186083 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 641968825 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2865871 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 57572234 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 37073972 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 286236 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 783841952 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.819003 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.071442 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 434056489 55.58% 55.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 142602713 18.26% 73.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 124298977 15.92% 89.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 71442121 9.15% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8609991 1.10% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4891 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 436124999 55.64% 55.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 142425457 18.17% 73.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 124936152 15.94% 89.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 71756087 9.15% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8593482 1.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5775 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 781015182 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 783841952 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 67040735 45.54% 45.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 53703 0.04% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 26002 0.02% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 14 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 38206404 25.96% 71.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 41875543 28.45% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67185359 45.52% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 54880 0.04% 45.56% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 27644 0.02% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 23 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37910313 25.69% 71.26% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 42413379 28.74% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 436779538 68.25% 68.25% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1517289 0.24% 68.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 81855 0.01% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 23 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 47604 0.01% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 110932479 17.33% 85.84% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 90632632 14.16% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 438393066 68.29% 68.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1458143 0.23% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 76119 0.01% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 8 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 85008 0.01% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 110671978 17.24% 85.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 91284446 14.22% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 639991449 # Type of FU issued -system.cpu0.iq.rate 0.794306 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 147202401 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.230007 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2209837146 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 710527601 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 621905864 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1270303 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 504170 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 467307 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 786402566 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 791283 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2962367 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 641968825 # Type of FU issued +system.cpu0.iq.rate 0.795416 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 147591598 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.229905 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2216794106 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 710999195 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 623995458 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1442965 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 583548 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 537913 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 788669354 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 891059 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2946784 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13371443 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 16751 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 153989 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6295959 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13030035 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 16500 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 154978 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6224286 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2934112 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4671160 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2912970 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4614756 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5509714 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7058035 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 5778589 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 652441938 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5462350 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6648440 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 5673367 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 653983600 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 107984972 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 92881396 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13772451 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 68630 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5639093 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 153989 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2201982 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3098287 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5300269 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 631633854 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 107665614 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7773689 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 107669777 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 93504359 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13738155 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 65760 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5541873 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 154978 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2183890 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3035421 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5219311 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 633716914 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 107489609 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7688831 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 122049 # number of nop insts executed -system.cpu0.iew.exec_refs 196907522 # number of memory reference insts executed -system.cpu0.iew.exec_branches 119104624 # Number of branches executed -system.cpu0.iew.exec_stores 89241908 # Number of stores executed -system.cpu0.iew.exec_rate 0.783933 # Inst execution rate -system.cpu0.iew.wb_sent 623170550 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 622373171 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 301982038 # num instructions producing a value -system.cpu0.iew.wb_consumers 495557723 # num instructions consuming a value +system.cpu0.iew.exec_nop 126894 # number of nop insts executed +system.cpu0.iew.exec_refs 197402015 # number of memory reference insts executed +system.cpu0.iew.exec_branches 119462239 # Number of branches executed +system.cpu0.iew.exec_stores 89912406 # Number of stores executed +system.cpu0.iew.exec_rate 0.785191 # Inst execution rate +system.cpu0.iew.wb_sent 625355277 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 624533371 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 303033924 # num instructions producing a value +system.cpu0.iew.wb_consumers 497197749 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.772439 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609378 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.773813 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609484 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 51133197 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15927810 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4984345 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 771348242 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.769770 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.572751 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 50242588 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15899847 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4905406 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 774311548 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.770083 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.572660 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 513096769 66.52% 66.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 132148168 17.13% 83.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 58179832 7.54% 91.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 19360594 2.51% 93.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 14004722 1.82% 95.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9477117 1.23% 96.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6473381 0.84% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3935015 0.51% 98.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14672644 1.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 515220918 66.54% 66.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 132191074 17.07% 83.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 58451829 7.55% 91.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19702970 2.54% 93.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 14118724 1.82% 95.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9514083 1.23% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6460440 0.83% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3939203 0.51% 98.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14712307 1.90% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 771348242 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 504955538 # Number of instructions committed -system.cpu0.commit.committedOps 593760630 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 774311548 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 507069048 # Number of instructions committed +system.cpu0.commit.committedOps 596284470 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 181198957 # Number of memory references committed -system.cpu0.commit.loads 94613526 # Number of loads committed -system.cpu0.commit.membars 4060839 # Number of memory barriers committed -system.cpu0.commit.branches 113014510 # Number of branches committed -system.cpu0.commit.fp_insts 458000 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 545152087 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14971844 # Number of function calls committed. +system.cpu0.commit.refs 181919815 # Number of memory references committed +system.cpu0.commit.loads 94639742 # Number of loads committed +system.cpu0.commit.membars 4012038 # Number of memory barriers committed +system.cpu0.commit.branches 113466884 # Number of branches committed +system.cpu0.commit.fp_insts 524978 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 547272509 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14945710 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 411193864 69.25% 69.25% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1260833 0.21% 69.46% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 65173 0.01% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 413008446 69.26% 69.26% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1219700 0.20% 69.47% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 60724 0.01% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction @@ -873,818 +878,821 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 41761 0.01% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 94613526 15.93% 85.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 86585431 14.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 75743 0.01% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 94639742 15.87% 85.36% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 87280073 14.64% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 593760630 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14672644 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1397369391 # The number of ROB reads -system.cpu0.rob.rob_writes 1299419087 # The number of ROB writes -system.cpu0.timesIdled 1071653 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24709022 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93813929115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 504955538 # Number of Instructions Simulated -system.cpu0.committedOps 593760630 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.595634 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.595634 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.626710 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.626710 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 746722296 # number of integer regfile reads -system.cpu0.int_regfile_writes 443322911 # number of integer regfile writes -system.cpu0.fp_regfile_reads 778801 # number of floating regfile reads -system.cpu0.fp_regfile_writes 335108 # number of floating regfile writes -system.cpu0.cc_regfile_reads 136612374 # number of cc regfile reads -system.cpu0.cc_regfile_writes 137527114 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1389482326 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16167899 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6374252 # number of replacements -system.cpu0.dcache.tags.tagsinuse 504.525126 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 168612051 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6374762 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.449937 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 596284470 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14712307 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1401646047 # The number of ROB reads +system.cpu0.rob.rob_writes 1302545204 # The number of ROB writes +system.cpu0.timesIdled 1046717 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 23244113 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93812546108 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 507069048 # Number of Instructions Simulated +system.cpu0.committedOps 596284470 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.591669 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.591669 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.628271 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.628271 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 748239233 # number of integer regfile reads +system.cpu0.int_regfile_writes 444460602 # number of integer regfile writes +system.cpu0.fp_regfile_reads 860614 # number of floating regfile reads +system.cpu0.fp_regfile_writes 470540 # number of floating regfile writes +system.cpu0.cc_regfile_reads 137535879 # number of cc regfile reads +system.cpu0.cc_regfile_writes 138377705 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1393834331 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16112974 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6187008 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.050028 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169602823 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6187519 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.410473 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1887138000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.525126 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985401 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.985401 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.050028 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986426 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986426 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 375986188 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 375986188 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 87724319 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 87724319 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75477797 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75477797 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 231729 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 231729 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 266468 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 266468 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2022541 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2022541 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2052696 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2052696 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 163202116 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 163202116 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 163433845 # number of overall hits -system.cpu0.dcache.overall_hits::total 163433845 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7197565 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7197565 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7724152 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7724152 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 724383 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 724383 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 844788 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 844788 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 278463 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 278463 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 208196 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 208196 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14921717 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14921717 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15646100 # number of overall misses -system.cpu0.dcache.overall_misses::total 15646100 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108620779500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 108620779500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 138974834179 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 138974834179 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 74732911806 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 74732911806 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4099802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4099802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4408839000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4408839000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3050500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3050500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 247595613679 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 247595613679 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 247595613679 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 247595613679 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 94921884 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 94921884 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 83201949 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 83201949 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 956112 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 956112 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1111256 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1111256 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2301004 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2301004 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2260892 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2260892 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 178123833 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 178123833 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 179079945 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 179079945 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075826 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.075826 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092836 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.092836 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.757634 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.757634 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760210 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760210 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.121018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.121018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092086 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092086 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.083772 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.083772 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087369 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.087369 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15091.323177 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15091.323177 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17992.244868 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17992.244868 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88463.510142 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88463.510142 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14722.968581 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14722.968581 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21176.386674 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21176.386674 # average StoreCondReq miss latency +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 376921548 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 376921548 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 87937173 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 87937173 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76339825 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76339825 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228046 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 228046 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 267132 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 267132 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1986809 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1986809 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2024617 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2024617 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 164276998 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164276998 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 164505044 # number of overall hits +system.cpu0.dcache.overall_hits::total 164505044 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6895567 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6895567 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7624089 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7624089 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 725854 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 725854 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 804065 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 804065 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 277240 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 277240 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200055 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 200055 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14519656 # number of demand (read+write) misses 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ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 94832740 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 83963914 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 83963914 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 953900 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 953900 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1071197 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1071197 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2264049 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2264049 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2224672 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2224672 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 178796654 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 178796654 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 179750554 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 179750554 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.072713 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.072713 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.090802 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.090802 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760933 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760933 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.750623 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.750623 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.122453 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.122453 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089926 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089926 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081208 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.081208 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.084815 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.084815 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14797.581838 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14797.581838 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17885.266313 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17885.266313 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90040.846243 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90040.846243 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14763.021209 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14763.021209 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21144.257829 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21144.257829 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16592.970747 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16592.970747 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15824.749534 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15824.749534 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 23148520 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 20510394 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 766944 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 746852 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 30.182803 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 27.462461 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16418.886175 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16418.886175 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15637.166560 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15637.166560 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 22487796 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 20190626 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 731543 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 741822 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 30.740224 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 27.217616 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4317679 # number of writebacks -system.cpu0.dcache.writebacks::total 4317679 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3700903 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3700903 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6185217 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6185217 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 5102 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 5102 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141775 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141775 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9886120 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9886120 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9886120 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9886120 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3496662 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3496662 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1538935 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1538935 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 717217 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 717217 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 839686 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 839686 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 136688 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136688 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 208181 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 208181 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5035597 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5035597 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5752814 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5752814 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21352 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21352 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 23308 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 23308 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 44660 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 44660 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50025996500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50025996500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29968345030 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29968345030 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17752964500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17752964500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 73677446306 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 73677446306 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1889285500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1889285500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4200723000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4200723000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2985500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2985500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 79994341530 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 79994341530 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97747306030 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 97747306030 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3896297500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3896297500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4053651000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4053651000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7949948500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7949948500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036837 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036837 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018496 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018496 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.750139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.755619 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.755619 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059404 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059404 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092079 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092079 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028270 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032124 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14306.786444 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14306.786444 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19473.431321 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19473.431321 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24752.570700 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24752.570700 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87744.045162 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87744.045162 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.882682 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.882682 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20178.224718 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20178.224718 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4210788 # number of writebacks +system.cpu0.dcache.writebacks::total 4210788 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3513002 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3513002 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6114706 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6114706 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4602 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4602 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 143782 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 143782 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9627708 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9627708 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9627708 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9627708 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3382565 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3382565 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1509383 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1509383 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 718663 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 718663 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 799463 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 799463 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 133458 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 133458 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200041 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 200041 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4891948 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4891948 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5610611 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5610611 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32342 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31823 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64165 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48415097500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48415097500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29340240291 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29340240291 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16426692500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16426692500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 71393732534 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 71393732534 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1844525500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1844525500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4030091500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4030091500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5165500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5165500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77755337791 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 77755337791 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94182030291 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 94182030291 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5817539000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5817539000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5518707000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5518707000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11336246000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11336246000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035669 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035669 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017977 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017977 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753394 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.753394 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746327 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746327 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058947 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058947 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089919 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089919 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027360 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027360 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031213 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031213 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14313.131455 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14313.131455 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19438.565487 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19438.565487 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.295422 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.295422 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89302.109709 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89302.109709 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.018598 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.018598 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20146.327503 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20146.327503 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15885.771147 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15885.771147 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16991.216130 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16991.216130 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182479.275946 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182479.275946 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173916.723872 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173916.723872 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 178010.490372 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178010.490372 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15894.555255 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15894.555255 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16786.412441 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16786.412441 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179875.672500 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179875.672500 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173418.816579 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173418.816579 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176673.357750 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176673.357750 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6538162 # number of replacements +system.cpu0.icache.tags.replacements 6407339 # number of replacements system.cpu0.icache.tags.tagsinuse 511.955601 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 224372588 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6538674 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.314693 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 224970066 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6407851 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.108505 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 17322639000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.955601 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999913 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 309 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 330 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 469120906 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 469120906 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 224372588 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 224372588 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 224372588 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 224372588 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 224372588 # number of overall hits -system.cpu0.icache.overall_hits::total 224372588 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6918516 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6918516 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6918516 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6918516 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6918516 # number of overall misses -system.cpu0.icache.overall_misses::total 6918516 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 73530599413 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 73530599413 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 73530599413 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 73530599413 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 73530599413 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 73530599413 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 231291104 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 231291104 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 231291104 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 231291104 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 231291104 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 231291104 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029913 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029913 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029913 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029913 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029913 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029913 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10628.088366 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10628.088366 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10628.088366 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10628.088366 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10628.088366 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10628.088366 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10842770 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 750 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 802318 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.514305 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 75 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 469899085 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 469899085 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 224970066 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 224970066 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 224970066 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 224970066 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 224970066 # number of overall hits +system.cpu0.icache.overall_hits::total 224970066 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6775541 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6775541 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6775541 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6775541 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6775541 # number of overall misses +system.cpu0.icache.overall_misses::total 6775541 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71079582898 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 71079582898 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 71079582898 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 71079582898 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 71079582898 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 71079582898 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 231745607 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 231745607 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 231745607 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 231745607 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 231745607 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 231745607 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029237 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029237 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029237 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029237 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029237 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029237 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10490.613650 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10490.613650 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10490.613650 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10490.613650 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10215206 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 732 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 767906 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.302678 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 379817 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 379817 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 379817 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 379817 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 379817 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 379817 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6538699 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6538699 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6538699 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6538699 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6538699 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6538699 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 367670 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 367670 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 367670 # number of demand (read+write) MSHR hits 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uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 66562536735 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 66562536735 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 66562536735 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 66562536735 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 66562536735 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 66562536735 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64388034562 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 64388034562 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64388034562 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 64388034562 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64388034562 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 64388034562 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1863746498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1863746498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028270 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028270 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10179.782971 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10179.782971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10179.782971 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027650 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027650 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027650 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10048.272595 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8420678 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8427841 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 6477 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8228747 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8235731 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 6331 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1085415 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2879166 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16210.435264 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 21867253 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2894850 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.553847 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1065389 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2775717 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16223.891094 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 21402394 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2791423 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.667198 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 16000650500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7399.715112 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 85.098490 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 94.687899 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4348.179928 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3389.288950 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 893.464886 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.451643 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005194 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005779 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.265392 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206866 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054533 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989406 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1404 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14188 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 251 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 619 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 434 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 68 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4744 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4803 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3671 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.085693 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.865967 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 440722520 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 440722520 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 580486 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180915 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 761401 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4317669 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4317669 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 115526 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 115526 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36643 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 36643 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 998559 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 998559 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5850201 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5850201 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3218899 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3218899 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 227084 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 227084 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 580486 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 180915 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5850201 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4217458 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10829060 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 580486 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 180915 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5850201 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4217458 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10829060 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13187 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9856 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 23043 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140809 # number of UpgradeReq misses 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-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 611195 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 611195 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13187 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9856 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 688482 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1424197 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2135722 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13187 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9856 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 688482 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1424197 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2135722 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 534558500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 449764500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 984323000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3072018500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 3072018500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3550746499 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3550746499 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2885498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2885498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16106273500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 16106273500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 21873259998 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 21873259998 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41772472980 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 41772472980 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 70023878999 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 70023878999 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 534558500 # number of demand (read+write) miss cycles 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ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 190771 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 784444 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4317674 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4317674 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 256335 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 256335 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 208173 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 208173 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 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system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.549316 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.549316 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823978 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823978 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.549700 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.549700 # mshr miss rate for UpgradeReq accesses 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-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257991 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.729107 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.729107 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022208 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050626 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.105292 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248054 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.162806 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022208 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050626 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.105292 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248054 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212980 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212980 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.103137 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254009 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254009 # mshr miss rate for ReadSharedReq accesses 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-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20509.164876 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20509.164876 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15278.770448 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15278.770448 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311937.250000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311937.250000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43035.628890 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43035.628890 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25770.418735 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30857.020661 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30857.020661 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108568.802099 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108568.802099 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33277.342309 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30865.934246 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33277.342309 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38829.564388 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.222515 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35423.908129 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58294.042246 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20555.263521 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20555.263521 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15357.239340 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15357.239340 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 427799.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 427799.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43096.290701 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43096.290701 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25030.464450 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30340.875210 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30340.875210 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 109654.401762 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 109654.401762 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30369.702703 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38213.150697 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174473.679281 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127313.288468 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166183.497812 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166183.497812 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171871.683879 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 135407.459542 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165748.199950 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165748.199950 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170147.043596 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 141049.935819 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168834.706881 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 146705.665489 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 984567 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11961948 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 972246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11719640 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 23308 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 8463420 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 11561533 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1016095 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 502894 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 380729 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 540434 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1691199 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1306018 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6538699 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6804200 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 945007 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 838279 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19656927 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20547872 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414026 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1295337 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 41914162 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 418816352 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 645201790 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1526168 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4749384 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1070293694 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 11878703 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 38928585 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.320254 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.466574 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31823 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 8100286 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 11177309 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1018919 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 495790 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 366670 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 532232 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 139 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1670081 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1283370 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6407871 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6502663 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 904766 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 798038 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19264194 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20025393 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 428101 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1250579 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 40968267 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 410442912 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629983858 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1576264 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4556320 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1046559354 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 11261603 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 37657626 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.313855 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.464058 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 26461563 67.97% 67.97% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 12467022 32.03% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 25838573 68.61% 68.61% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 11819053 31.39% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 38928585 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 18022605428 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 37657626 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 17602075916 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 218178978 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 231593980 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9834328997 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9637654372 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9151913574 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8931019988 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 223594319 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 231432265 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 702320680 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 681669728 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 127974219 # Number of BP lookups -system.cpu1.branchPred.condPredicted 85721226 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6122377 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91131353 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 60172902 # Number of BTB hits +system.cpu1.branchPred.lookups 121094303 # Number of BP lookups +system.cpu1.branchPred.condPredicted 80706133 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6142160 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 84960891 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 56341743 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 66.028760 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17085083 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 181731 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 66.314915 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16429988 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 173246 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1714,89 +1722,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 610901 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 610901 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 15580 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 103695 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 293448 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 317453 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2113.928676 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 12461.929670 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 312797 98.53% 98.53% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 2424 0.76% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 700 0.22% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 857 0.27% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 351 0.11% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 153 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 53 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 19 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 21 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 582230 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 582230 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14388 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94420 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 278308 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 303922 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 1994.445943 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 12173.491739 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 299685 98.61% 98.61% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 2211 0.73% 99.33% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 696 0.23% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 740 0.24% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 294 0.10% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 141 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 47 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 22 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::360448-393215 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 317453 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 338102 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 18568.539967 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 16066.889111 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14911.003076 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 335377 99.19% 99.19% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1909 0.56% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 302 0.09% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 312 0.09% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 121 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 38 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::491520-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 303922 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 314895 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18136.229537 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15585.359240 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14753.917468 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 312363 99.20% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1838 0.58% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 299 0.09% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 215 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 97 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 338102 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 438848021252 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.580073 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.553130 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 437543459752 99.70% 99.70% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 782991500 0.18% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 243923500 0.06% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 110155500 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 88476500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 41634500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 16681500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 20049000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 649500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 438848021252 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 103695 86.94% 86.94% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 15580 13.06% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 119275 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 610901 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 314895 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 417361955272 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.556480 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.556703 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 416192825272 99.72% 99.72% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 674141500 0.16% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 223425500 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 105228000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 86739500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 43806500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 16133000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 19234500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 421500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 417361955272 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94420 86.78% 86.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 14388 13.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 108808 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 582230 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 610901 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 119275 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 582230 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108808 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 119275 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 730176 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108808 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 691038 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 94901630 # DTB read hits -system.cpu1.dtb.read_misses 438242 # DTB read misses -system.cpu1.dtb.write_hits 77470080 # DTB write hits -system.cpu1.dtb.write_misses 172659 # DTB write misses -system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 89807249 # DTB read hits +system.cpu1.dtb.read_misses 419450 # DTB read misses +system.cpu1.dtb.write_hits 72180592 # DTB write hits +system.cpu1.dtb.write_misses 162780 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 42323 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7630 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 41875 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 370 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6410 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 42941 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 95339872 # DTB read accesses -system.cpu1.dtb.write_accesses 77642739 # DTB write accesses +system.cpu1.dtb.perms_faults 41502 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90226699 # DTB read accesses +system.cpu1.dtb.write_accesses 72343372 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 172371710 # DTB hits -system.cpu1.dtb.misses 610901 # DTB misses -system.cpu1.dtb.accesses 172982611 # DTB accesses +system.cpu1.dtb.hits 161987841 # DTB hits +system.cpu1.dtb.misses 582230 # DTB misses +system.cpu1.dtb.accesses 162570071 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1826,1161 +1835,1148 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 86285 # Table walker walks requested -system.cpu1.itb.walker.walksLong 86285 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1166 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62692 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9855 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 76430 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1337.426403 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 10105.936208 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 75617 98.94% 98.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 383 0.50% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 204 0.27% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 174 0.23% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 76430 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 73713 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 23336.867310 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 20402.005732 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19525.264050 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 72001 97.68% 97.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1393 1.89% 99.57% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 144 0.20% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 112 0.15% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 36 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 81350 # Table walker walks requested +system.cpu1.itb.walker.walksLong 81350 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 844 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59039 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9413 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 71937 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1124.310160 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8422.739912 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 71675 99.64% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 232 0.32% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 71937 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 69296 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 22634.596514 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19851.891028 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18070.710028 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 67837 97.89% 97.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1226 1.77% 99.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 116 0.17% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 73713 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 417370190772 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.853526 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.353735 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 61155433348 14.65% 14.65% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 356194673424 85.34% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 18786000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1262500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 417370190772 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 62692 98.17% 98.17% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1166 1.83% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63858 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 69296 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 391589144496 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.846934 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.360225 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 59961618480 15.31% 15.31% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 331606536516 84.68% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 19274500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1690500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 24500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 391589144496 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 59039 98.59% 98.59% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 844 1.41% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 59883 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86285 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86285 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81350 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81350 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63858 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63858 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 150143 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 203133106 # ITB inst hits -system.cpu1.itb.inst_misses 86285 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59883 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59883 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 141233 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 191639831 # ITB inst hits +system.cpu1.itb.inst_misses 81350 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 30560 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29949 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 224551 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 209776 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 203219391 # ITB inst accesses -system.cpu1.itb.hits 203133106 # DTB hits -system.cpu1.itb.misses 86285 # DTB misses -system.cpu1.itb.accesses 203219391 # DTB accesses -system.cpu1.numCycles 708901373 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 191721181 # ITB inst accesses +system.cpu1.itb.hits 191639831 # DTB hits +system.cpu1.itb.misses 81350 # DTB misses +system.cpu1.itb.accesses 191721181 # DTB accesses +system.cpu1.numCycles 657106376 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 79210227 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 569056404 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 127974219 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 77257985 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 596249525 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13297978 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1936888 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 233747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6483042 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 760521 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 721953 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 202886748 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1527721 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28660 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 692244892 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.964370 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.215604 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 80139865 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 537547218 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 121094303 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 72771731 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 544595085 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13230640 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1750818 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 245014 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5964311 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 783127 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 735374 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 191409476 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1578665 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27162 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 640828914 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.984123 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.220773 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 371999522 53.74% 53.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 125145403 18.08% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 42864856 6.19% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 152235111 21.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 338710091 52.85% 52.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 117550572 18.34% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 40600676 6.34% 77.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 143967575 22.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 692244892 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.180525 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.802730 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 98103528 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 343550458 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 207545620 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 38285921 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4759365 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18045337 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1925812 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 590182189 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20993149 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4759365 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 132299037 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 44198902 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 235238981 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 211136719 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 64611888 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 574391592 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5359861 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9789729 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 401271 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 868513 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 28581746 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 10968 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 549201958 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 896745625 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 678703153 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 702078 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 496570478 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 52631474 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 16637084 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 14688391 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76542594 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 94434816 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 80595349 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8923483 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7689116 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 551758554 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 16802636 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 558923093 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2479703 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 49836281 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 32327580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 272404 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 692244892 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.807407 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.056587 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 640828914 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.184284 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.818052 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 96524622 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 306596217 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 198367702 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 34666699 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4673674 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17189225 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1979171 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 555902892 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21032284 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4673674 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 128741707 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 40944507 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 207984500 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 200380023 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 58104503 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 540647070 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5273833 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8920508 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 357666 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 869250 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 25304278 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 12220 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 515542885 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 838360476 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 639083471 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 635892 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 463444914 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 52097965 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14931648 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13102843 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 69578208 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 89907304 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 75221964 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8553187 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7364919 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 519731744 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15160501 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 524719232 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2440222 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 49181333 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32199370 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 264903 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 640828914 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.818813 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.060738 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 382813800 55.30% 55.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 135617529 19.59% 74.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 105540069 15.25% 90.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 60873310 8.79% 98.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7395424 1.07% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4760 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 351184657 54.80% 54.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 125580577 19.60% 74.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 99945390 15.60% 89.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 57229371 8.93% 98.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6884833 1.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4086 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 692244892 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 640828914 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 54751854 43.35% 43.35% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 59874 0.05% 43.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 7206 0.01% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 34635726 27.43% 70.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 36835867 29.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 51884545 43.66% 43.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 60325 0.05% 43.71% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 6398 0.01% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 32949736 27.73% 71.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 33928397 28.55% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 22 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 381080184 68.18% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1279374 0.23% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67457 0.01% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 77518 0.01% 68.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 97747450 17.49% 85.92% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 78671088 14.08% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 357316080 68.10% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1302107 0.25% 68.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 73183 0.01% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 41368 0.01% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 92637950 17.65% 86.02% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 73348522 13.98% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 558923093 # Type of FU issued -system.cpu1.iq.rate 0.788436 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 126290549 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.225953 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1937670345 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 618057050 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 542680096 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1190983 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 486822 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 443064 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 684478646 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 734974 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2497447 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 524719232 # Type of FU issued +system.cpu1.iq.rate 0.798530 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 118829423 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226463 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1810487568 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 583794764 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 509259381 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1049453 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 417103 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 385439 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 642894662 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 653971 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2364683 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11391566 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16442 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 147287 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5480411 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11367007 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 15961 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 139264 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5290675 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2518337 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4561530 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2384785 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4103064 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4759365 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7377288 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1779487 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 568686865 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4673674 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6987028 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1738087 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 535009487 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 94434816 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 80595349 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 14436432 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67561 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1633321 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 147287 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1861843 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2641662 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4503505 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 551808656 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 94901612 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6513481 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 89907304 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 75221964 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12892176 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 53410 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1616074 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 139264 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1829419 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2640296 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4469715 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 517720791 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 89804186 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6423141 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 125675 # number of nop insts executed -system.cpu1.iew.exec_refs 172371354 # number of memory reference insts executed -system.cpu1.iew.exec_branches 103407043 # Number of branches executed -system.cpu1.iew.exec_stores 77469742 # Number of stores executed -system.cpu1.iew.exec_rate 0.778400 # Inst execution rate -system.cpu1.iew.wb_sent 543849746 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 543123160 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 263131919 # num instructions producing a value -system.cpu1.iew.wb_consumers 431737287 # num instructions consuming a value +system.cpu1.iew.exec_nop 117242 # number of nop insts executed +system.cpu1.iew.exec_refs 161982461 # number of memory reference insts executed +system.cpu1.iew.exec_branches 97046647 # Number of branches executed +system.cpu1.iew.exec_stores 72178275 # Number of stores executed +system.cpu1.iew.exec_rate 0.787880 # Inst execution rate +system.cpu1.iew.wb_sent 510319956 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 509644820 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 247330259 # num instructions producing a value +system.cpu1.iew.wb_consumers 405058762 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.766148 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.609472 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.775590 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610603 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 43653536 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 16530232 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4232753 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 683948716 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.758427 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.554925 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 43050408 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14895598 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4200514 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 632658676 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.767730 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.562752 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 453202569 66.26% 66.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 123078137 18.00% 84.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 49564580 7.25% 91.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16593049 2.43% 93.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11718092 1.71% 95.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8048900 1.18% 96.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5489767 0.80% 97.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3345988 0.49% 98.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12907634 1.89% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 417403815 65.98% 65.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 113799591 17.99% 83.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 46934435 7.42% 91.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15547292 2.46% 93.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10981139 1.74% 95.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7643765 1.21% 96.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5190686 0.82% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3150553 0.50% 98.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12007400 1.90% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 683948716 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 441056280 # Number of instructions committed -system.cpu1.commit.committedOps 518724902 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 632658676 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 412964348 # Number of instructions committed +system.cpu1.commit.committedOps 485710905 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 158158187 # Number of memory references committed -system.cpu1.commit.loads 83043249 # Number of loads committed -system.cpu1.commit.membars 3695786 # Number of memory barriers committed -system.cpu1.commit.branches 98284315 # Number of branches committed -system.cpu1.commit.fp_insts 431344 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 475340146 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12767541 # Number of function calls committed. +system.cpu1.commit.refs 148471585 # Number of memory references committed +system.cpu1.commit.loads 78540296 # Number of loads committed +system.cpu1.commit.membars 3510647 # Number of memory barriers committed +system.cpu1.commit.branches 92021861 # Number of branches committed +system.cpu1.commit.fp_insts 377145 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 445805015 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12220081 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 359393863 69.28% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1051243 0.20% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 53001 0.01% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 68608 0.01% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 83043249 16.01% 85.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 75114938 14.48% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 336089825 69.20% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1056611 0.22% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 57564 0.01% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 35320 0.01% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 78540296 16.17% 85.60% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 69931289 14.40% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 518724902 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12907634 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1229236643 # The number of ROB reads -system.cpu1.rob.rob_writes 1133012460 # The number of ROB writes -system.cpu1.timesIdled 937113 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 16656481 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 93910751930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 441056280 # Number of Instructions Simulated -system.cpu1.committedOps 518724902 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.607281 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.607281 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.622169 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.622169 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 651831389 # number of integer regfile reads -system.cpu1.int_regfile_writes 384949596 # number of integer regfile writes -system.cpu1.fp_regfile_reads 687947 # number of floating regfile reads -system.cpu1.fp_regfile_writes 437000 # number of floating regfile writes -system.cpu1.cc_regfile_reads 121245693 # number of cc regfile reads -system.cpu1.cc_regfile_writes 121813302 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1231894475 # number of misc regfile reads -system.cpu1.misc_regfile_writes 16565900 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5500590 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.004525 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 146156295 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5501102 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 26.568548 # Average number of references to valid blocks. +system.cpu1.commit.op_class_0::total 485710905 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12007400 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1145678392 # The number of ROB reads +system.cpu1.rob.rob_writes 1065656273 # The number of ROB writes +system.cpu1.timesIdled 931363 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 16277462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 93962526294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 412964348 # Number of Instructions Simulated +system.cpu1.committedOps 485710905 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.591194 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.591194 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.628459 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.628459 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 611833579 # number of integer regfile reads +system.cpu1.int_regfile_writes 362533704 # number of integer regfile writes +system.cpu1.fp_regfile_reads 622107 # number of floating regfile reads +system.cpu1.fp_regfile_writes 321740 # number of floating regfile writes +system.cpu1.cc_regfile_reads 111613116 # number of cc regfile reads +system.cpu1.cc_regfile_writes 112230966 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1145938750 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14868837 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5274603 # number of replacements +system.cpu1.dcache.tags.tagsinuse 426.947513 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 137535053 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5275114 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 26.072432 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8485200468500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.004525 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839853 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.839853 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 327866519 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 327866519 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 76697860 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76697860 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64975008 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64975008 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170492 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 170492 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 54492 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 54492 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753772 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1753772 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1761808 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1761808 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 141672868 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 141672868 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 141843360 # number of overall hits -system.cpu1.dcache.overall_hits::total 141843360 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6400758 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6400758 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7699637 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7699637 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 744836 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 744836 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409878 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 409878 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 258549 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 258549 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 208576 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 208576 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 14100395 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 14100395 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14845231 # number of overall misses -system.cpu1.dcache.overall_misses::total 14845231 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92687894000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 92687894000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138325220262 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 138325220262 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20294196326 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 20294196326 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4013433500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4013433500 # number of LoadLockedReq miss cycles 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accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72674645 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72674645 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 915328 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 915328 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 464370 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 464370 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2012321 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2012321 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1970384 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1970384 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 155773263 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 155773263 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 156688591 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 156688591 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077026 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.077026 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.105947 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.105947 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.813737 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.813737 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.882654 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.882654 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.128483 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.128483 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105856 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105856 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.090519 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.090519 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.094744 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.094744 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14480.768371 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14480.768371 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17965.161249 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17965.161249 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 49512.772889 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 49512.772889 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15522.912485 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15522.912485 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21059.956563 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21059.956563 # average StoreCondReq miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.947513 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.833882 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.833882 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 308540922 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 308540922 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 72744707 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 72744707 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 60628902 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 60628902 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 161948 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 161948 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50338 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 50338 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624470 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1624470 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1636906 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1636906 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 133373609 # number of demand (read+write) hits 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211466711879 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 211466711879 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 211466711879 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 78946081 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 78946081 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 67598311 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 67598311 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824938 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 824938 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498178 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 498178 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1879909 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1879909 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1837552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 146544392 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146544392 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 147369330 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 147369330 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.103100 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.103100 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.803685 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.803685 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.898956 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.898956 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135878 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135878 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089876 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.089876 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093871 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.093871 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14227.285356 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14227.285356 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17682.703710 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17682.703710 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45441.352914 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45441.352914 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14511.856060 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14511.856060 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21373.182122 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21373.182122 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16383.449844 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16383.449844 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15561.436145 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15561.436145 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 5682783 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 23004045 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 345925 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 792691 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 16.427789 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 29.020192 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16055.743374 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16055.743374 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15286.264411 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15286.264411 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 5662057 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 20000375 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 377912 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 710012 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.982475 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.169066 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3566261 # number of writebacks -system.cpu1.dcache.writebacks::total 3566261 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3293272 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3293272 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6267237 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 6267237 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 2938 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 2938 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 130878 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 130878 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9560509 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9560509 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9560509 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9560509 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3107486 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3107486 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1432400 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1432400 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 744751 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 744751 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 406940 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 406940 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127671 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127671 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 208566 # number of StoreCondReq MSHR misses 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-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31831 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43040497000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43040497000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26400232128 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26400232128 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15655161500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15655161500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19798456326 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19798456326 # number of WriteLineReq MSHR miss cycles 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of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 85095890628 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2604403500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2604403500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2300537000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2300537000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4904940500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4904940500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037395 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037395 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019710 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019710 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.813644 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.813644 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.876327 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.876327 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063445 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063445 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105850 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105850 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029144 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029144 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033727 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033727 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13850.584363 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13850.584363 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18430.768031 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18430.768031 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21020.665296 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21020.665296 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 48652.028127 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 48652.028127 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14400.615645 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14400.615645 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20061.306733 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20061.306733 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3411546 # number of writebacks +system.cpu1.dcache.writebacks::total 3411546 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3176462 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3176462 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5650771 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5650771 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3283 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3283 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 129585 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 129585 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8827233 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8827233 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8827233 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8827233 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3024912 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3024912 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1318638 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1318638 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 662904 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 662904 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 444557 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 444557 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125854 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125854 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 200639 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 200639 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4343550 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4343550 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5006454 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5006454 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6436 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6436 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6853 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13289 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13289 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40779010000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40779010000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24146673124 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24146673124 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13797097500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13797097500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19809664989 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19809664989 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1736527500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1736527500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4087933500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4087933500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5874000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5874000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64925683124 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 64925683124 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78722780624 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 78722780624 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 710484000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 710484000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 859770500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 859770500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1570254500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1570254500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.038316 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.038316 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019507 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019507 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.803580 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.803580 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.892366 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.892366 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066947 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066947 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109188 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109188 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029640 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029640 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033972 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033972 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.056639 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.056639 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18311.828663 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18311.828663 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20813.115474 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20813.115474 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44560.461288 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44560.461288 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13797.952389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13797.952389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20374.570746 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20374.570746 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15295.698863 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15295.698863 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16102.504416 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16102.504416 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 153788.219663 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 153788.219663 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154439.916756 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154439.916756 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 154093.195313 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 154093.195313 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14947.608091 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14947.608091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15724.259251 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15724.259251 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110392.169049 # average ReadReq mshr uncacheable latency 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of references to valid blocks. -system.cpu1.icache.tags.avg_refs 36.480010 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 5512111 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.811781 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 185560716 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5512623 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 33.661057 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8495886874000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.811782 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.811781 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980101 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.980101 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 411165528 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 411165528 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 197154720 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 197154720 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 197154720 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 197154720 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 197154720 # number of overall hits -system.cpu1.icache.overall_hits::total 197154720 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5725810 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5725810 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5725810 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5725810 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5725810 # number of overall misses -system.cpu1.icache.overall_misses::total 5725810 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 59819230732 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 59819230732 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 59819230732 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 59819230732 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 59819230732 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 59819230732 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 202880530 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 202880530 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 202880530 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 202880530 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 202880530 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 202880530 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028223 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.028223 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028223 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.028223 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028223 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.028223 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10447.295794 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10447.295794 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10447.295794 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10447.295794 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10447.295794 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10447.295794 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 8523796 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 288 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 664103 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.835051 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 96 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 388319278 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 388319278 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 185560716 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 185560716 # number of ReadReq hits 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ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 60453928731 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 60453928731 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 60453928731 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 60453928731 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 191403319 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 191403319 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 191403319 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 191403319 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 191403319 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 191403319 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030525 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030525 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030525 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030525 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030525 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030525 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10347.088230 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10347.088230 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10347.088230 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10347.088230 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 8745745 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 74 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 694595 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.591143 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 74 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 321342 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 321342 # number of ReadReq MSHR hits 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system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54260492010 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 54260492010 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54260492010 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 54260492010 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54260492010 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 54260492010 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54827935019 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 54827935019 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54827935019 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 54827935019 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54827935019 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 54827935019 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5791998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5791998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5791998 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5791998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026639 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.026639 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.026639 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10039.932147 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10039.932147 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10039.932147 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028801 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028801 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028801 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9945.858068 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7840068 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7844426 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 3981 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7331800 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7336274 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 4099 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 944222 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2377748 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13486.772220 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 18876475 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2393818 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.885510 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10140216096000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5055.984886 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.053821 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 84.713714 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 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+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.831171 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197282 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197282 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.115328 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.267084 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267084 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.637589 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.637589 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250766 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170837 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250766 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211179 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211179 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110111 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255144 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255144 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.606089 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.606089 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245188 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.164193 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245188 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.241473 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 36310.043470 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62702.817586 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19926.217494 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19926.217494 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15072.044681 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15072.044681 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 560899.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 560899.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 38652.446498 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 38652.446498 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22362.048081 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27036.453370 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27036.453370 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63037.326026 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63037.326026 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29172.766547 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27073.052707 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29172.766547 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37495.580260 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228851 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33424.770007 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52932.700330 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20059.330207 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20059.330207 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15391.014758 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15391.014758 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 306374.437500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 306374.437500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37091.720099 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37091.720099 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22534.887859 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26522.761925 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26522.761925 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 59492.976944 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 59492.976944 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28584.021913 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26636.716143 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28584.021913 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34066.188993 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145787.392973 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 145523.938360 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146938.876208 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146938.876208 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102389.838409 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102148.162387 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117956.515395 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117956.515395 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 146326.254280 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 146184.698100 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 110417.412898 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 110259.471399 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 997626 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10426628 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 14896 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 7712009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 10305258 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1022601 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 482744 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 380034 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 500528 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1988029 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1220428 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5404468 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6543941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 512654 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 405926 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16212466 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17789160 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 422162 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1316947 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 35740735 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 345886640 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 566771243 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1562912 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4846136 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 919066931 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 12378423 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 35388761 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.367817 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.482211 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 950963 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10318053 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6853 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 7301053 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 10168977 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 922205 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 460948 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364065 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 477238 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1860044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1122762 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5512640 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6310959 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 550275 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 443547 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16537003 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17033306 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 391276 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1237529 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 35199114 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352809840 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 540363378 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1419696 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4484152 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 899077066 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 11781593 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 34442064 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.358530 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.479569 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 22372180 63.22% 63.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 13016581 36.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 22093559 64.15% 64.15% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 12348505 35.85% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 35388761 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 15228808958 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 34442064 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14907193441 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 179948989 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 189176968 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8110869278 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8273171683 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8234240098 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7832975507 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 227095399 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 214052518 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 711723893 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 677527956 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40342 # Transaction distribution -system.iobus.trans_dist::ReadResp 40342 # Transaction distribution -system.iobus.trans_dist::WriteReq 136642 # Transaction distribution -system.iobus.trans_dist::WriteResp 136642 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47708 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40376 # Transaction distribution +system.iobus.trans_dist::ReadResp 40376 # Transaction distribution +system.iobus.trans_dist::WriteReq 136648 # Transaction distribution +system.iobus.trans_dist::WriteResp 136648 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47800 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2990,18 +2986,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231246 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231286 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47728 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3011,18 +3007,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155749 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339000 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339000 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496835 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36238000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36303000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -3042,7 +3038,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -3050,71 +3046,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569545477 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569813871 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92731000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92765000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147942000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147982000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115612 # number of replacements -system.iocache.tags.tagsinuse 11.307418 # Cycle average of tags in use +system.iocache.tags.replacements 115623 # number of replacements +system.iocache.tags.tagsinuse 11.307008 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115639 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9081354759000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.848836 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.458583 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 9081350424000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.848834 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.458174 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.240552 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466161 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706714 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466136 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706688 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040964 # Number of tag accesses -system.iocache.tags.data_accesses 1040964 # Number of data accesses +system.iocache.tags.tag_accesses 1041144 # Number of tag accesses +system.iocache.tags.data_accesses 1041144 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8895 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8932 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8915 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8952 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8895 # number of demand (read+write) misses -system.iocache.demand_misses::total 8935 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8915 # number of demand (read+write) misses +system.iocache.demand_misses::total 8955 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8895 # number of overall misses -system.iocache.overall_misses::total 8935 # number of overall misses +system.iocache.overall_misses::realview.ide 8915 # number of overall misses +system.iocache.overall_misses::total 8955 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1662593136 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1667788136 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1625113033 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1630308033 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12635360341 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12635360341 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12635282838 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12635282838 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1662593136 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1668157136 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1625113033 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1630677033 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1662593136 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1668157136 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1625113033 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1630677033 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8895 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8932 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8915 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8952 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8895 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8935 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8915 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8955 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8895 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8935 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8915 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8955 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3129,54 +3125,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186913.224958 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186720.570533 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182289.740101 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182116.625670 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118388.429850 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118388.429850 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118387.703677 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118387.703677 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186913.224958 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 186699.175825 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182096.821106 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186913.224958 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 186699.175825 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32654 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182096.821106 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 30957 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3475 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.652380 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.908489 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106702 # number of writebacks -system.iocache.writebacks::total 106702 # number of writebacks +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8895 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8932 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8915 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8952 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8895 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8935 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8915 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8955 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8895 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8935 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8915 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8955 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1217843136 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1221188136 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179363033 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1182708033 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7298960341 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7298960341 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7298882838 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7298882838 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1217843136 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1221407136 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1179363033 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1182927033 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1217843136 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1221407136 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1179363033 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1182927033 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3191,614 +3187,623 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136913.224958 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136720.570533 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132289.740101 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132116.625670 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68388.429850 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68388.429850 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68387.703677 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68387.703677 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136913.224958 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 136699.175825 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136913.224958 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 136699.175825 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1760747 # number of replacements -system.l2c.tags.tagsinuse 63871.601453 # Cycle average of tags in use -system.l2c.tags.total_refs 6095006 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1821172 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.346749 # Average number of references to valid blocks. +system.l2c.tags.replacements 1604376 # number of replacements +system.l2c.tags.tagsinuse 63973.571253 # Cycle average of tags in use +system.l2c.tags.total_refs 5805157 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1664778 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.487046 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 18326.572985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 182.034797 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 268.280441 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4619.393037 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9002.087865 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11374.868707 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 179.474155 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 242.215899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2745.232497 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8268.941513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8662.499555 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.279641 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004094 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.137361 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173567 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002739 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003696 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.041889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.126174 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.132179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.974603 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11384 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48804 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1357 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 826 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9193 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 233 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2623 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 40501 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.173706 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.744690 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 76795315 # Number of tag accesses -system.l2c.tags.data_accesses 76795315 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2680735 # number of Writeback hits -system.l2c.Writeback_hits::total 2680735 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 32943 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 31048 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 63991 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6336 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5767 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12103 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 174506 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 154775 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 329281 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6806 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4586 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 614111 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 638498 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 286433 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6534 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4346 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 583459 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 618336 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 287570 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3050679 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6806 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4586 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 614111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 813004 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 286433 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6534 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 583459 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 773111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 287570 # number of demand (read+write) hits -system.l2c.demand_hits::total 3379960 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6806 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4586 # number of overall hits -system.l2c.overall_hits::cpu0.inst 614111 # number of overall hits -system.l2c.overall_hits::cpu0.data 813004 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 286433 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6534 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4346 # number of overall hits -system.l2c.overall_hits::cpu1.inst 583459 # number of overall hits -system.l2c.overall_hits::cpu1.data 773111 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 287570 # number of overall hits -system.l2c.overall_hits::total 3379960 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 48112 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 44467 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 92579 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10023 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8706 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18729 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 523780 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 170521 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 694301 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2882 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2624 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 74362 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 179746 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 302363 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2755 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2528 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 39827 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 128012 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 323843 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 1058942 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2882 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2624 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 74362 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 703526 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 302363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2755 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2528 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 39827 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 298533 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 323843 # number of demand (read+write) misses -system.l2c.demand_misses::total 1753243 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2882 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2624 # number of overall misses -system.l2c.overall_misses::cpu0.inst 74362 # number of overall misses -system.l2c.overall_misses::cpu0.data 703526 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 302363 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2755 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2528 # number of overall misses -system.l2c.overall_misses::cpu1.inst 39827 # number of overall misses -system.l2c.overall_misses::cpu1.data 298533 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 323843 # number of overall misses -system.l2c.overall_misses::total 1753243 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 280230500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 263754000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 543984500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 55711000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 50228500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 105939500 # number of SCUpgradeReq miss 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accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 16359 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 14473 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 30832 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 698286 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 325296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1023582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9688 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7210 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 688473 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 818244 # number of ReadSharedReq accesses(hits+misses) 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(read+write) accesses -system.l2c.overall_accesses::cpu0.data 1516530 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 588796 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9289 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6874 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 623286 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1071644 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 611413 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 5133203 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.593572 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.588850 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.591295 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.612690 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.601534 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.607453 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.750094 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.524203 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.678305 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.297481 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.363939 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.108010 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.219673 # miss rate for ReadSharedReq accesses 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rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.296587 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.367763 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.063560 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.278540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529663 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.341450 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.297481 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.363939 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.463883 # mshr miss rate for overall accesses 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miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 89498.558805 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87864.778277 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112031.632054 # average ReadSharedReq mshr miss latency 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latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20771.451847 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20774.997677 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20773.261995 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 121029.954081 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99041.910769 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 115651.896802 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 86511.447609 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87880.554232 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109067.070667 # average ReadSharedReq mshr miss latency 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+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94526.941613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 111818.587900 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156472.227426 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153870.709913 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127801.984291 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114507.184053 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149180.347220 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 129937.567132 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141677.456104 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84414.128070 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 113814.066215 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148745.782390 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100954.399533 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140277.627805 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152666.603963 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151328.972695 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 128801.438939 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 125115.391242 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 92945.059080 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 124172.062714 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 59646 # Transaction distribution -system.membus.trans_dist::ReadResp 1127009 # Transaction distribution -system.membus.trans_dist::WriteReq 38204 # Transaction distribution -system.membus.trans_dist::WriteResp 38204 # Transaction distribution -system.membus.trans_dist::Writeback 1464927 # Transaction distribution -system.membus.trans_dist::CleanEvict 280718 # Transaction distribution -system.membus.trans_dist::UpgradeReq 444619 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 331926 # Transaction distribution -system.membus.trans_dist::UpgradeResp 118163 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 708914 # Transaction distribution -system.membus.trans_dist::ReadExResp 687449 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1067363 # Transaction distribution +system.membus.trans_dist::ReadReq 60137 # Transaction distribution +system.membus.trans_dist::ReadResp 1008264 # Transaction distribution +system.membus.trans_dist::WriteReq 38676 # Transaction distribution +system.membus.trans_dist::WriteResp 38676 # Transaction distribution +system.membus.trans_dist::Writeback 1353245 # Transaction distribution +system.membus.trans_dist::CleanEvict 256072 # Transaction distribution +system.membus.trans_dist::UpgradeReq 446472 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 317458 # Transaction distribution +system.membus.trans_dist::UpgradeResp 117838 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.membus.trans_dist::ReadExReq 689582 # Transaction distribution +system.membus.trans_dist::ReadExResp 667715 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 948127 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122682 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6087631 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6235467 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6577494 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155749 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27002 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5660502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5810264 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342643 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342643 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6152907 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 198978048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 199184601 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7249472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 206434073 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 682959 # Total snoops (count) -system.membus.snoop_fanout::samples 4505681 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182936448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 183146836 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7268096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190414932 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 670794 # Total snoops (count) +system.membus.snoop_fanout::samples 4218827 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4505681 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4218827 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4505681 # Request fanout histogram -system.membus.reqLayer0.occupancy 98301494 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4218827 # Request fanout histogram +system.membus.reqLayer0.occupancy 97993999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21116985 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22746984 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10136025529 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9381331556 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9507659574 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8783305125 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229108938 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229295864 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3842,60 +3847,60 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 59648 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5069827 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38204 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 4145743 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1638680 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 501758 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 344029 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 845787 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 136 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1170821 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1170821 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 5017419 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 60139 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4816420 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38676 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3889503 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1527175 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 497158 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 330081 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 827239 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 247 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1142368 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1142368 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4763508 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9001938 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7449274 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16451212 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 278573838 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 222195147 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 500768985 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3698425 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 14333755 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.138980 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.345926 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8767118 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899331 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15666449 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271825986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202528722 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 474354708 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3515812 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13605383 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.134927 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.341646 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12341651 86.10% 86.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1992104 13.90% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11769647 86.51% 86.51% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1835736 13.49% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 14333755 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9346036195 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 13605383 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8891301093 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2541000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2589000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5271518855 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5132723331 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4504542320 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4211299918 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4738 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 14670 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14252 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 7288 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini index 026d5a2a0..11a1cd43d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -201,7 +201,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -542,7 +542,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -652,7 +652,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -740,7 +740,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1155,9 +1155,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout index a2bc54e0f..231e72707 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 10:59:42 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:57:07 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51323721423000 because m5_exit instruction encountered +Exiting @ tick 51562169701000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 02e1510aa..591f883e9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.323721 # Number of seconds simulated -sim_ticks 51323721423000 # Number of ticks simulated -final_tick 51323721423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.562170 # Number of seconds simulated +sim_ticks 51562169701000 # Number of ticks simulated +final_tick 51562169701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120356 # Simulator instruction rate (inst/s) -host_op_rate 141420 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7238849372 # Simulator tick rate (ticks/s) -host_mem_usage 678076 # Number of bytes of host memory used -host_seconds 7090.04 # Real time elapsed on the host -sim_insts 853325819 # Number of instructions simulated -sim_ops 1002674190 # Number of ops (including micro ops) simulated +host_inst_rate 82472 # Simulator instruction rate (inst/s) +host_op_rate 96938 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3850541751 # Simulator tick rate (ticks/s) +host_mem_usage 726532 # Number of bytes of host memory used +host_seconds 13390.89 # Real time elapsed on the host +sim_insts 1104366834 # Number of instructions simulated +sim_ops 1298086167 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 203200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 189632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5727200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 73778504 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory -system.physmem.bytes_read::total 80318312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5727200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5727200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68723904 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 657984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 557504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6634080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 148649160 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 417792 # Number of bytes read from this memory +system.physmem.bytes_read::total 156916520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6634080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6634080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 139624832 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68744484 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3175 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105440 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1152802 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1270939 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1073811 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 139645412 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10281 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 119610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2322656 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6528 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2467786 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2181638 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1076384 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 3959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 111590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1437513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1564935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 111590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1339028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1339429 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1339028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 3959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 111590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1437914 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2904365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1270939 # Number of read requests accepted -system.physmem.writeReqs 1076384 # Number of write requests accepted -system.physmem.readBursts 1270939 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1076384 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 81299584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 40512 # Total number of bytes read from write queue -system.physmem.bytesWritten 68742976 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 80318312 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68744484 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 633 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 142017 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 76590 # Per bank write bursts -system.physmem.perBankRdBursts::1 80112 # Per bank write bursts -system.physmem.perBankRdBursts::2 82312 # Per bank write bursts -system.physmem.perBankRdBursts::3 76894 # Per bank write bursts -system.physmem.perBankRdBursts::4 75148 # Per bank write bursts -system.physmem.perBankRdBursts::5 84486 # Per bank write bursts -system.physmem.perBankRdBursts::6 75307 # Per bank write bursts -system.physmem.perBankRdBursts::7 76047 # Per bank write bursts -system.physmem.perBankRdBursts::8 76921 # Per bank write bursts -system.physmem.perBankRdBursts::9 104197 # Per bank write bursts -system.physmem.perBankRdBursts::10 75653 # Per bank write bursts -system.physmem.perBankRdBursts::11 81028 # Per bank write bursts -system.physmem.perBankRdBursts::12 74845 # Per bank write bursts -system.physmem.perBankRdBursts::13 77383 # Per bank write bursts -system.physmem.perBankRdBursts::14 76622 # Per bank write bursts -system.physmem.perBankRdBursts::15 76761 # Per bank write bursts -system.physmem.perBankWrBursts::0 64108 # Per bank write bursts -system.physmem.perBankWrBursts::1 67910 # Per bank write bursts -system.physmem.perBankWrBursts::2 69982 # Per bank write bursts -system.physmem.perBankWrBursts::3 67432 # Per bank write bursts -system.physmem.perBankWrBursts::4 65959 # Per bank write bursts -system.physmem.perBankWrBursts::5 70786 # Per bank write bursts -system.physmem.perBankWrBursts::6 64733 # Per bank write bursts -system.physmem.perBankWrBursts::7 66187 # Per bank write bursts -system.physmem.perBankWrBursts::8 67287 # Per bank write bursts -system.physmem.perBankWrBursts::9 71812 # Per bank write bursts -system.physmem.perBankWrBursts::10 65064 # Per bank write bursts -system.physmem.perBankWrBursts::11 69201 # Per bank write bursts -system.physmem.perBankWrBursts::12 65082 # Per bank write bursts -system.physmem.perBankWrBursts::13 66370 # Per bank write bursts -system.physmem.perBankWrBursts::14 66024 # Per bank write bursts -system.physmem.perBankWrBursts::15 66172 # Per bank write bursts +system.physmem.num_writes::total 2184211 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 12761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 10812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 128662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2882911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3043249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 128662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 128662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2707893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2708292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2707893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 10812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 128662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2883310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5751541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2467786 # Number of read requests accepted +system.physmem.writeReqs 2184211 # Number of write requests accepted +system.physmem.readBursts 2467786 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2184211 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 157889856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48448 # Total number of bytes read from write queue +system.physmem.bytesWritten 139644224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 156916520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 139645412 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 757 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 155211 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 149005 # Per bank write bursts +system.physmem.perBankRdBursts::1 156339 # Per bank write bursts +system.physmem.perBankRdBursts::2 155955 # Per bank write bursts +system.physmem.perBankRdBursts::3 150628 # Per bank write bursts +system.physmem.perBankRdBursts::4 148084 # Per bank write bursts +system.physmem.perBankRdBursts::5 159303 # Per bank write bursts +system.physmem.perBankRdBursts::6 149188 # Per bank write bursts +system.physmem.perBankRdBursts::7 152515 # Per bank write bursts +system.physmem.perBankRdBursts::8 150862 # Per bank write bursts +system.physmem.perBankRdBursts::9 179370 # Per bank write bursts +system.physmem.perBankRdBursts::10 150320 # Per bank write bursts +system.physmem.perBankRdBursts::11 155893 # Per bank write bursts +system.physmem.perBankRdBursts::12 152080 # Per bank write bursts +system.physmem.perBankRdBursts::13 155961 # Per bank write bursts +system.physmem.perBankRdBursts::14 150556 # Per bank write bursts +system.physmem.perBankRdBursts::15 150970 # Per bank write bursts +system.physmem.perBankWrBursts::0 132106 # Per bank write bursts +system.physmem.perBankWrBursts::1 138501 # Per bank write bursts +system.physmem.perBankWrBursts::2 137398 # Per bank write bursts +system.physmem.perBankWrBursts::3 135602 # Per bank write bursts +system.physmem.perBankWrBursts::4 133392 # Per bank write bursts +system.physmem.perBankWrBursts::5 140433 # Per bank write bursts +system.physmem.perBankWrBursts::6 132940 # Per bank write bursts +system.physmem.perBankWrBursts::7 137025 # Per bank write bursts +system.physmem.perBankWrBursts::8 135656 # Per bank write bursts +system.physmem.perBankWrBursts::9 141181 # Per bank write bursts +system.physmem.perBankWrBursts::10 134433 # Per bank write bursts +system.physmem.perBankWrBursts::11 138339 # Per bank write bursts +system.physmem.perBankWrBursts::12 136301 # Per bank write bursts +system.physmem.perBankWrBursts::13 138853 # Per bank write bursts +system.physmem.perBankWrBursts::14 135122 # Per bank write bursts +system.physmem.perBankWrBursts::15 134659 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 51323720227500 # Total gap between requests +system.physmem.numWrRetry 21 # Number of times write queue was full causing retry +system.physmem.totGap 51562168447500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1249654 # Read request sizes (log2) +system.physmem.readPktSize::6 2446501 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1073811 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 646219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 339232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 151287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 128129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2181638 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1276105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 831313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 193469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 160610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 946 # What read queue length does an incoming req see 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-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,164 +159,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 31518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 53343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 63532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 69167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 70329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 66867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 85010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 86471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 65847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 69713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 481355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.708207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.914901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.146013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 186832 38.81% 38.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 113175 23.51% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45398 9.43% 71.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23450 4.87% 76.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18101 3.76% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11671 2.42% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10460 2.17% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8315 1.73% 86.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 63953 13.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 481355 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61522 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.647411 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 265.936082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 61519 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 20208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 23029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 68337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 107857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 119474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 131451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 131860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 135328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 136231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 138984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 139007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 140497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 136343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 166652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 162914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 137438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 145049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 131294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 938073 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.175418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.850858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.830774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 348981 37.20% 37.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 217922 23.23% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89990 9.59% 70.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51985 5.54% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 41514 4.43% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 28050 2.99% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24686 2.63% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20558 2.19% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 114387 12.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 938073 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 129462 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 19.055908 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 183.344638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 129459 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61522 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.458942 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.948779 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.823778 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 58490 95.07% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 664 1.08% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 448 0.73% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 190 0.31% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 308 0.50% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 527 0.86% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 143 0.23% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 33 0.05% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 36 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.03% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 32 0.05% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 22 0.04% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 426 0.69% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 45 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 33 0.05% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 31 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 129462 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 129462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.853911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.595936 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.789289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 125866 97.22% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1229 0.95% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 433 0.33% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 197 0.15% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 330 0.25% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 524 0.40% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 121 0.09% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 23 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 39 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.01% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 43 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 23 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 425 0.33% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 36 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 42 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 37 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 35 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61522 # Writes before turning the bus around for reads -system.physmem.totQLat 31530968444 # Total ticks spent queuing -system.physmem.totMemAccLat 55349205944 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6351530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24821.55 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 129462 # Writes before turning the bus around for reads +system.physmem.totQLat 61876185756 # Total ticks spent queuing +system.physmem.totMemAccLat 108132979506 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 12335145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25081.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43571.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.56 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43831.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.31 # Average write queue length when enqueuing -system.physmem.readRowHits 1047361 # Number of row buffer hits during reads -system.physmem.writeRowHits 815697 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.94 # Row buffer hit rate for writes -system.physmem.avgGap 21864788.20 # Average gap between requests -system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1828287720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 997577625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4889757600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3480388560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1226219398425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29718601656750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34308233025720 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.467372 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49439480717043 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713811840000 # Time in different power states +system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing +system.physmem.readRowHits 2056722 # Number of row buffer hits during reads +system.physmem.writeRowHits 1654173 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.81 # Row buffer hit rate for writes +system.physmem.avgGap 11083878.27 # Average gap between requests +system.physmem.pageHitRate 79.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3550765680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1937421750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 9523885800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 7046332560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1313489115900 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29785116936750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34488454558920 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.871313 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49548907375208 # Time in different power states +system.physmem_0.memoryStateTime::REF 1721774080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 170428636707 # Time in different power states +system.physmem_0.memoryStateTime::ACT 291487862292 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1810756080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 988011750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5018598000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3479837760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1228704019020 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29716422156750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34308639338400 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.475289 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49435820968594 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713811840000 # Time in different power states +system.physmem_1.actEnergy 3541066200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1932129375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 9718893600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 7092645120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1316895447015 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29782128927000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34489099208790 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.883816 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49543906734220 # Time in different power states +system.physmem_1.memoryStateTime::REF 1721774080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 174088371406 # Time in different power states +system.physmem_1.memoryStateTime::ACT 296486485780 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -340,15 +337,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 225557622 # Number of BP lookups -system.cpu.branchPred.condPredicted 150824960 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12221670 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159273353 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104130221 # Number of BTB hits +system.cpu.branchPred.lookups 288825634 # Number of BP lookups +system.cpu.branchPred.condPredicted 198097109 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13566789 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 207338959 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136913226 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.378307 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30957399 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 344598 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 66.033526 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37451224 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 402112 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -379,87 +376,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 951838 # Table walker walks requested -system.cpu.dtb.walker.walksLong 951838 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16475 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156308 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 435006 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 516832 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 1986.510123 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-32767 508349 98.36% 98.36% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-65535 5443 1.05% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-98303 1244 0.24% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::98304-131071 1085 0.21% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-163839 165 0.03% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::163840-196607 178 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-229375 121 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::229376-262143 54 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-294911 95 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::294912-327679 7 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-360447 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::360448-393215 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-425983 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::425984-458751 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 516832 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 485267 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 475094 97.90% 97.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 9290 1.91% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 546 0.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 199 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 82 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 20 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 485267 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 776250627376 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.722476 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.519579 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 774163165376 99.73% 99.73% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1120728500 0.14% 99.88% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 435636500 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 187638500 0.02% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 148036000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 113935000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 26323500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 52542500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2621500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 776250627376 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 156309 90.46% 90.46% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16475 9.54% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 172784 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 1430156 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1430156 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30793 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273791 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 677378 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 752778 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2375.228819 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 746726 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4359 0.58% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 685 0.09% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 394 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 311 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 120 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 171 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 752778 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 802636 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 783977 97.68% 97.68% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 16023 2.00% 99.67% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1555 0.19% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 316 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 129 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 37 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 22 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 802636 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1044763922448 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.739319 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.520240 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1040800473448 99.62% 99.62% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2579873000 0.25% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 637994000 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 271834500 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 201274500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 132884500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 46819000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 89469000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3255500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 45000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1044763922448 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 273792 89.89% 89.89% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 30793 10.11% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 304585 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1430156 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951838 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172784 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1430156 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304585 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172784 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1124622 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304585 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1734741 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 170417440 # DTB read hits -system.cpu.dtb.read_misses 677013 # DTB read misses -system.cpu.dtb.write_hits 148384109 # DTB write hits -system.cpu.dtb.write_misses 274825 # DTB write misses -system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 217117628 # DTB read hits +system.cpu.dtb.read_misses 1002788 # DTB read misses +system.cpu.dtb.write_hits 192115888 # DTB write hits +system.cpu.dtb.write_misses 427368 # DTB write misses +system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 39714 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1025 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72556 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 87986 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10696 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 15675 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 70061 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171094453 # DTB read accesses -system.cpu.dtb.write_accesses 148658934 # DTB write accesses +system.cpu.dtb.perms_faults 85972 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 218120416 # DTB read accesses +system.cpu.dtb.write_accesses 192543256 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 318801549 # DTB hits -system.cpu.dtb.misses 951838 # DTB misses -system.cpu.dtb.accesses 319753387 # DTB accesses +system.cpu.dtb.hits 409233516 # DTB hits +system.cpu.dtb.misses 1430156 # DTB misses +system.cpu.dtb.accesses 410663672 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -489,877 +483,877 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 162167 # Table walker walks requested -system.cpu.itb.walker.walksLong 162167 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 122178 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17760 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144407 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1087.128740 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 7079.961036 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143546 99.40% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 491 0.34% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 245 0.17% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 86 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 177415 # Table walker walks requested +system.cpu.itb.walker.walksLong 177415 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1441 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 130680 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 19804 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 157611 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1499.045117 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 10189.386950 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 155888 98.91% 98.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 579 0.37% 99.27% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 739 0.47% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 292 0.19% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 35 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 38 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144407 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 141371 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27408.566821 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 138940 98.28% 98.28% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2106 1.49% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 209 0.15% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 62 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 157611 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 151925 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29463.087050 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 146250 96.26% 96.26% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 4800 3.16% 99.42% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 534 0.35% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 196 0.13% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 80 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 44 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 15 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 141371 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 655988501088 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.936740 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.243710 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 41542191152 6.33% 6.33% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 614402729936 93.66% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 43110500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 467500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 151925 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 920206753364 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.948994 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.220270 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 46987798652 5.11% 5.11% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 873167595712 94.89% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 50573500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 783500 0.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 655988501088 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 122178 98.84% 98.84% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 123611 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 920206753364 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 130680 98.91% 98.91% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1441 1.09% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 132121 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162167 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 162167 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177415 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 177415 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123611 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 123611 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 285778 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 358625455 # ITB inst hits -system.cpu.itb.inst_misses 162167 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 132121 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 132121 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 309536 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 461294711 # ITB inst hits +system.cpu.itb.inst_misses 177415 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 39714 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1025 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53363 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 62159 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372145 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 458083 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 358787622 # ITB inst accesses -system.cpu.itb.hits 358625455 # DTB hits -system.cpu.itb.misses 162167 # DTB misses -system.cpu.itb.accesses 358787622 # DTB accesses -system.cpu.numCycles 1590418745 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 461472126 # ITB inst accesses +system.cpu.itb.hits 461294711 # DTB hits +system.cpu.itb.misses 177415 # DTB misses +system.cpu.itb.accesses 461472126 # DTB accesses +system.cpu.numCycles 2141240199 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 646410999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1006402404 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225557622 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135087620 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 866562323 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26107474 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3678311 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 25439 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9275413 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1023850 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 676 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 358236204 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6112300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 49056 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1540030748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.765724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.157325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 785638694 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1289733601 # Number of instructions fetch has processed +system.cpu.fetch.Branches 288825634 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174364450 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1267374465 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29210356 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4418623 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12152128 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1217886 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 633 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 460817774 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6728045 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 53516 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2085435848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.725171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.139838 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 979927440 63.63% 63.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215057699 13.96% 77.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70955696 4.61% 82.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 274089913 17.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1366680941 65.53% 65.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 278589155 13.36% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 86788366 4.16% 83.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 353377386 16.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1540030748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.141823 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632791 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 525466953 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 519947088 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 434864784 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50506307 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9245616 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33796734 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3867997 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1090931528 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29050280 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9245616 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 570424085 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50840114 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 363017689 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 440398811 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 106104433 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1071115355 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6801917 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5040663 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 343395 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 645255 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 54344412 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20434 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1018974666 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1651092433 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1266893179 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1473696 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 953236782 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65737881 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27206823 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23528426 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 103688094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 174464093 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 151959443 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9931077 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9032567 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1035787653 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27506074 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1051526043 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3293799 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60619533 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33780075 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 314140 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1540030748 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.682795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.925415 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2085435848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.134887 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.602330 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 612239538 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 852574124 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 529946172 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80118083 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10557931 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41219534 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4107385 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1403247413 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32566835 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10557931 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 674962554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 85247440 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 550746700 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 547461697 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 216459526 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1379612307 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 7971383 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7360618 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 963827 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1074082 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 133209723 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22971 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1329803577 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2195861380 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1637517470 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1437183 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1251935276 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 77868298 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43546894 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39087703 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 166786807 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 221659276 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 196613901 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12565776 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11015266 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1326936815 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 43849103 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1356961205 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4098709 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 72699747 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41430931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 372473 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2085435848 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.650685 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.914510 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 888949202 57.72% 57.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 336251490 21.83% 79.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 235798342 15.31% 94.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72468185 4.71% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6544331 0.42% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19198 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1239320860 59.43% 59.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 449936886 21.58% 81.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 291017288 13.95% 94.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 95682212 4.59% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9449903 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28699 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1540030748 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2085435848 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58035888 35.01% 35.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 99674 0.06% 35.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26738 0.02% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 574 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44566242 26.88% 61.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63041416 38.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 73477453 34.17% 34.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90486 0.04% 34.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26768 0.01% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 385 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 57876005 26.91% 61.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83594438 38.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 724142674 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2543730 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122779 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 376 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121012 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 174312709 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150282706 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 937288786 69.07% 69.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2936989 0.22% 69.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 129444 0.01% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 114407 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 221949724 16.36% 85.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194541406 14.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1051526043 # Type of FU issued -system.cpu.iq.rate 0.661163 # Inst issue rate -system.cpu.iq.fu_busy_cnt 165770532 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157648 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3809671307 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1123107931 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1033541701 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2475857 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 947397 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 910004 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1215741366 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1555198 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4333965 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1356961205 # Type of FU issued +system.cpu.iq.rate 0.633727 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215065535 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.158491 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5016097714 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1442740685 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1335189379 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2424787 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 927446 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 888349 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1570502436 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1524273 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5709357 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13839303 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14833 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143349 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6338712 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16902439 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24350 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 184211 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8196884 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2540349 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1552925 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3577769 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1870440 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9245616 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6389360 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5797347 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1063516239 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10557931 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12374030 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7706525 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1371058602 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 174464093 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 151959443 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23100216 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59008 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5663632 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143349 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3667729 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5111764 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8779493 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1040328227 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 170406440 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10257681 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 221659276 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 196613901 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 38550114 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178028 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7343410 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 184211 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4239042 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5703306 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 9942348 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1343677933 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 217120223 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11882036 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222512 # number of nop insts executed -system.cpu.iew.exec_refs 318786335 # number of memory reference insts executed -system.cpu.iew.exec_branches 197400349 # Number of branches executed -system.cpu.iew.exec_stores 148379895 # Number of stores executed -system.cpu.iew.exec_rate 0.654122 # Inst execution rate -system.cpu.iew.wb_sent 1035262700 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1034451705 # cumulative count of insts written-back -system.cpu.iew.wb_producers 440415620 # num instructions producing a value -system.cpu.iew.wb_consumers 712619707 # num instructions consuming a value +system.cpu.iew.exec_nop 272684 # number of nop insts executed +system.cpu.iew.exec_refs 409245203 # number of memory reference insts executed +system.cpu.iew.exec_branches 255119365 # Number of branches executed +system.cpu.iew.exec_stores 192124980 # Number of stores executed +system.cpu.iew.exec_rate 0.627523 # Inst execution rate +system.cpu.iew.wb_sent 1337102879 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1336077728 # cumulative count of insts written-back +system.cpu.iew.wb_producers 573421420 # num instructions producing a value +system.cpu.iew.wb_consumers 940568778 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.650427 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618023 # average fanout of values written-back +system.cpu.iew.wb_rate 0.623974 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.609654 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51498978 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27191934 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8413549 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1528028900 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.656188 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.286676 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 62140410 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 43476630 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9519542 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2071346493 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.626687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.267080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1013092181 66.30% 66.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 289858237 18.97% 85.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121052617 7.92% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36682667 2.40% 95.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28563883 1.87% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14105791 0.92% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8655946 0.57% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4198069 0.27% 99.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11819509 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1395640231 67.38% 67.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 393909449 19.02% 86.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150461425 7.26% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44316735 2.14% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35977476 1.74% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18232281 0.88% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10892931 0.53% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5452952 0.26% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16463013 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1528028900 # Number of insts commited each cycle -system.cpu.commit.committedInsts 853325819 # Number of instructions committed -system.cpu.commit.committedOps 1002674190 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2071346493 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1104366834 # Number of instructions committed +system.cpu.commit.committedOps 1298086167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 306245520 # Number of memory references committed -system.cpu.commit.loads 160624789 # Number of loads committed -system.cpu.commit.membars 6977905 # Number of memory barriers committed -system.cpu.commit.branches 190474151 # Number of branches committed -system.cpu.commit.fp_insts 896785 # Number of committed floating point instructions. -system.cpu.commit.int_insts 921116747 # Number of committed integer instructions. -system.cpu.commit.function_calls 25400785 # Number of function calls committed. +system.cpu.commit.refs 393173853 # Number of memory references committed +system.cpu.commit.loads 204756836 # Number of loads committed +system.cpu.commit.membars 9104821 # Number of memory barriers committed +system.cpu.commit.branches 246834909 # Number of branches committed +system.cpu.commit.fp_insts 874964 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1186447841 # Number of committed integer instructions. +system.cpu.commit.function_calls 30876862 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 694059947 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2158876 0.22% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98131 0.01% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111674 0.01% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 160624789 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 145620731 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 902159630 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2542825 0.20% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 103949 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105868 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 204756836 15.77% 85.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 188417017 14.51% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1002674190 # Class of committed instruction -system.cpu.commit.bw_lim_events 11819509 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2562796067 # The number of ROB reads -system.cpu.rob.rob_writes 2120254358 # The number of ROB writes -system.cpu.timesIdled 8129447 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50387997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101057024238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 853325819 # Number of Instructions Simulated -system.cpu.committedOps 1002674190 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.863788 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.863788 # CPI: Total CPI of All Threads -system.cpu.ipc 0.536542 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.536542 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1231590969 # number of integer regfile reads -system.cpu.int_regfile_writes 735370525 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462122 # number of floating regfile reads -system.cpu.fp_regfile_writes 782688 # number of floating regfile writes -system.cpu.cc_regfile_reads 226859046 # number of cc regfile reads -system.cpu.cc_regfile_writes 227515194 # number of cc regfile writes -system.cpu.misc_regfile_reads 2534481060 # number of misc regfile reads -system.cpu.misc_regfile_writes 27245755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9758519 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983709 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 284707567 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9759031 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.173754 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 1298086167 # Class of committed instruction +system.cpu.commit.bw_lim_events 16463013 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3405665880 # The number of ROB reads +system.cpu.rob.rob_writes 2734432791 # The number of ROB writes +system.cpu.timesIdled 9009507 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 55804351 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100983102115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1104366834 # Number of Instructions Simulated +system.cpu.committedOps 1298086167 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.938885 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.938885 # CPI: Total CPI of All Threads +system.cpu.ipc 0.515760 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.515760 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1596434625 # number of integer regfile reads +system.cpu.int_regfile_writes 940526203 # number of integer regfile writes +system.cpu.fp_regfile_reads 1424965 # number of floating regfile reads +system.cpu.fp_regfile_writes 765828 # number of floating regfile writes +system.cpu.cc_regfile_reads 311708448 # number of cc regfile reads +system.cpu.cc_regfile_writes 312593649 # number of cc regfile writes +system.cpu.misc_regfile_reads 3410532874 # number of misc regfile reads +system.cpu.misc_regfile_writes 44362921 # number of misc regfile writes +system.cpu.dcache.tags.replacements 13614186 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983787 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 360288791 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13614698 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.463223 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983709 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983787 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1243872376 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1243872376 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 147964440 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147964440 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128940955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128940955 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 380183 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 380183 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 324678 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 324678 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3327415 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3327415 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3725844 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3725844 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 276905395 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 276905395 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 277285578 # number of overall hits -system.cpu.dcache.overall_hits::total 277285578 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9612542 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9612542 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11385353 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11385353 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1184834 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1184834 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1232047 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1232047 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 450033 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 450033 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1595334423 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1595334423 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 186468319 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 186468319 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 162903680 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 162903680 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 463393 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 463393 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 334025 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 334025 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4787397 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4787397 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5271269 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5271269 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 349371999 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 349371999 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 349835392 # number of overall hits +system.cpu.dcache.overall_hits::total 349835392 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12723000 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12723000 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18625078 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18625078 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2035956 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2035956 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1270469 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1270469 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 547335 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 547335 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20997895 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20997895 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22182729 # number of overall misses -system.cpu.dcache.overall_misses::total 22182729 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 144669003500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 330867751444 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 63675897168 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 63675897168 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6433485000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6433485000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 31348078 # number of demand (read+write) misses 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number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 251000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 475536754944 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 475536754944 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 475536754944 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 475536754944 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 157576982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 157576982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 140326308 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 140326308 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1565017 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1565017 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1556725 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1556725 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3777448 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3777448 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3725851 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3725851 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 297903290 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 297903290 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 299468307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 299468307 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061002 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061002 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081135 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081135 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.757074 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.757074 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791435 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791435 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119137 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119137 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070486 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070486 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074074 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074074 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_latency::cpu.data 1182718575621 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1182718575621 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1182718575621 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1182718575621 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 199191319 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 199191319 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 181528758 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 181528758 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2499349 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2499349 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5334732 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5334732 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5271276 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5271276 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 380720077 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 380720077 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 383219426 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 383219426 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063873 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.063873 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102601 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.102601 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.814595 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.814595 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791819 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791819 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102598 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102598 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082339 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082339 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087115 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087115 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15982.387487 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15982.387487 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52583.654126 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52583.654126 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 58582.915759 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 58582.915759 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16079.034778 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16079.034778 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22646.877458 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21437.252150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 35158879 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37728.583412 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37728.583412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35427.671072 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35427.671072 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 46020939 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1606955 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2096301 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.879193 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.953402 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7549082 # number of writebacks -system.cpu.dcache.writebacks::total 7549082 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4467834 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4467834 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9360902 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9360902 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7079 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7079 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219205 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 219205 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13828736 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13828736 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13828736 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13828736 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5144708 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5144708 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2024451 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2024451 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1178103 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1178103 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224968 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1224968 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230828 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 230828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 10299062 # number of writebacks +system.cpu.dcache.writebacks::total 10299062 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5706012 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5706012 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15543150 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15543150 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7171 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7171 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 263403 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 263403 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21249162 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21249162 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21249162 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21249162 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7016988 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7016988 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3081928 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3081928 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2029224 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2029224 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263298 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1263298 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283932 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 283932 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7169159 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7169159 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8347262 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8347262 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75818409500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75818409500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57062160713 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57062160713 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20148080000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20148080000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 62191648168 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 62191648168 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3063087000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3063087000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 10098916 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 10098916 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 12128140 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 12128140 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109410315500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109410315500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 144646896672 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 144646896672 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32373018500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32373018500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72874671402 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72874671402 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4076865500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4076865500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 132880570213 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 153028650213 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5828327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5828327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5707957967 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5707957967 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11536285467 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11536285467 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032649 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032649 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752773 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752773 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786888 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786888 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061107 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061107 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024065 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024065 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027874 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027874 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 254057212172 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 286430230672 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829096500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829096500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5708243467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5708243467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11537339967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11537339967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016978 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016978 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.811901 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.811901 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787350 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787350 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053223 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053223 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 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average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15042093 # number of replacements -system.cpu.icache.tags.tagsinuse 511.944879 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 342405629 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15042605 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.762389 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 16756542 # number of replacements +system.cpu.icache.tags.tagsinuse 511.945135 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 443237235 # Total number of references to valid blocks. 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task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 373257734 # Number of tag accesses -system.cpu.icache.tags.data_accesses 373257734 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 342405629 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 342405629 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 342405629 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 342405629 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 342405629 # number of overall hits -system.cpu.icache.overall_hits::total 342405629 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15809279 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15809279 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15809279 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15809279 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15809279 # number of overall misses -system.cpu.icache.overall_misses::total 15809279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 208403044384 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 208403044384 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 208403044384 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208403044384 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208403044384 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 358214908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 358214908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 358214908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 358214908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 358214908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 358214908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044134 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044134 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044134 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044134 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044134 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044134 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13182.324405 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13182.324405 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 15030 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 477553750 # Number of tag accesses +system.cpu.icache.tags.data_accesses 477553750 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 443237235 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 443237235 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 443237235 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 443237235 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 443237235 # number of overall hits +system.cpu.icache.overall_hits::total 443237235 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17559241 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17559241 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17559241 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17559241 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17559241 # number of overall misses +system.cpu.icache.overall_misses::total 17559241 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 232141013891 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 232141013891 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 232141013891 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 232141013891 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 232141013891 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 232141013891 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 460796476 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 460796476 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 460796476 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 460796476 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 460796476 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 460796476 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038106 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.038106 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.038106 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.038106 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.038106 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.038106 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13220.446937 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13220.446937 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13220.446937 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 15959 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1210 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1225 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 12.421488 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.027755 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 766453 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 766453 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 766453 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 766453 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 766453 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 766453 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15042826 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15042826 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15042826 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15042826 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15042826 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15042826 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 801966 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 801966 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 801966 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 801966 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 801966 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 801966 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16757275 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16757275 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16757275 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16757275 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16757275 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16757275 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186915451392 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 186915451392 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186915451392 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 186915451392 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208567956898 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 208567956898 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208567956898 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 208567956898 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208567956898 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 208567956898 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1594412000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1594412000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1594412000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 1594412000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041994 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.041994 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.041994 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12425.554307 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12425.554307 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036366 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.036366 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.036366 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12446.412492 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12446.412492 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1148683 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65278.817014 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46198537 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1210914 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 38.151790 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2345734 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65318.237935 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 55622573 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2409067 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.088844 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 15659706000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 301.460755 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 460.210435 # Average occupied blocks per requestor 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140349228000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 149157162500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1328224500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5407344500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6735569000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5315951000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5315951000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5407939500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6736164000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5316157000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5316157000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1328224500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10723295500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12051520000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10724096500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12052321000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011427 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785148 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785148 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787568 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787568 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005596 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.402131 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.402131 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030479 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030479 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.432327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.432327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045172 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045172 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.467465 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.467465 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060150 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060150 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78619.287068 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1633565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23227278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8622904 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 17438576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 44010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2244083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28317103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 12480720 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 20347986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 60667 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 44017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1983984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1983984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15042826 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6558947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1331632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1224968 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45167572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29499463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 732865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1940611 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77340511 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 963068272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1029563294 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2422088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6336984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2001390638 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1864369 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 52693428 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.056141 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.230194 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 60674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3036433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3036433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16757275 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9323830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1369962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1263298 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50310988 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41099763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 807461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3043712 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 95261924 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1072793136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1449869810 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2707560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10589056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2535959562 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3104722 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 65657900 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.072586 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.259455 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 49735173 94.39% 94.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2958255 5.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 60892075 92.74% 92.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 4765825 7.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 52693428 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 33222815494 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 65657900 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 41856500497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1182000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22592032956 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25164199957 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13487423434 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19241199390 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 430634727 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 469526277 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1148958035 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1720822991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40295 # Transaction distribution -system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.iobus.trans_dist::ReadReq 40298 # Transaction distribution +system.iobus.trans_dist::ReadResp 40298 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1574,11 +1568,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1595,11 +1589,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1628,71 +1622,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568813596 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568892559 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147714000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.423947 # Cycle average of tags in use +system.iocache.tags.replacements 115458 # number of replacements +system.iocache.tags.tagsinuse 10.449705 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13095311635000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544418 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879529 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429971 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651497 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13095311633000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.528028 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.921676 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220502 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432605 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653107 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039623 # Number of tag accesses -system.iocache.tags.data_accesses 1039623 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8810 # number of demand (read+write) misses -system.iocache.demand_misses::total 8850 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8810 # number of overall misses -system.iocache.overall_misses::total 8850 # number of overall misses +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1621911166 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1626980166 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1615020135 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1620089135 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12610487430 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12610487430 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12610143424 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12610143424 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1621911166 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1627331166 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1615020135 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1620440135 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1621911166 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1627331166 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1615020135 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1620440135 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8810 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8850 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8810 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8850 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1707,54 +1701,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183901.906409 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183060.919209 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183879.227797 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183038.533266 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183879.227797 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31681 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183038.533266 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31319 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3345 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.471151 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.276955 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8810 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8850 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8810 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8850 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1181411166 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1184630166 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174370135 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1177589135 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277287430 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7277287430 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7276943424 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7276943424 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1181411166 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1184831166 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1174370135 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1177790135 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1181411166 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1184831166 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1174370135 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1177790135 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1769,72 +1763,72 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54973 # Transaction distribution -system.membus.trans_dist::ReadResp 407867 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::Writeback 1073811 # Transaction distribution -system.membus.trans_dist::CleanEvict 187846 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35358 # Transaction distribution +system.membus.trans_dist::ReadReq 54987 # Transaction distribution +system.membus.trans_dist::ReadResp 601962 # Transaction distribution +system.membus.trans_dist::WriteReq 33703 # Transaction distribution +system.membus.trans_dist::WriteResp 33703 # Transaction distribution +system.membus.trans_dist::Writeback 2181638 # Transaction distribution +system.membus.trans_dist::CleanEvict 277040 # Transaction distribution +system.membus.trans_dist::UpgradeReq 48552 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35361 # Transaction distribution -system.membus.trans_dist::ReadExReq 899707 # Transaction distribution -system.membus.trans_dist::ReadExResp 899707 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 352894 # Transaction distribution +system.membus.trans_dist::UpgradeResp 48555 # Transaction distribution +system.membus.trans_dist::ReadExReq 1902507 # Transaction distribution +system.membus.trans_dist::ReadExResp 1902507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 546975 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3753956 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3883578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4225292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7371150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7500814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341657 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341657 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7842471 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 141818700 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 141988686 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7244096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7244096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 149232782 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2955 # Total snoops (count) -system.membus.snoop_fanout::samples 2747442 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 289319820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 289489890 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7242112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 296732002 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2989 # Total snoops (count) +system.membus.snoop_fanout::samples 5154600 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2747442 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5154600 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2747442 # Request fanout histogram -system.membus.reqLayer0.occupancy 104159500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5154600 # Request fanout histogram +system.membus.reqLayer0.occupancy 104456000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5443500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5495500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7279924206 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14230820482 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6776038462 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13100845399 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228860056 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228852771 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1845,11 +1839,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1878,17 +1872,17 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16150 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 20008 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini index cc1edf626..160a8ac7f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -136,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -212,7 +212,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -322,7 +322,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -410,7 +410,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -761,9 +761,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json index 1d5cc7d19..96cb18ee3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json @@ -6,7 +6,7 @@ "mmap_using_noreserve": false, "kernel_addr_check": true, "highest_el_is_64": false, - "kernel": "/work/gem5/dist/binaries/vmlinux.aarch64.20140821", + "kernel": "/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821", "iobus": { "slave": { "peer": [ @@ -68,7 +68,7 @@ "frontend_latency": 2 }, "symbolfile": "", - "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh", + "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", "have_large_asid_64": false, "phys_addr_range_64": 40, "have_lpae": false, @@ -87,7 +87,7 @@ "multi_proc": true, "early_kernel_symbols": false, "panic_on_oops": true, - "dtb_filename": "/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb", + "dtb_filename": "/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb", "enable_context_switch_stats_dump": false, "work_begin_ckpt_count": 0, "clk_domain": { @@ -108,30 +108,33 @@ ], "realview": { "hdlcd": { - "dma": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, - "pixel_clock": 7299, "vnc": "system.vncserver", + "pxl_clk": "system.realview.realview_io.osc_pxl", "name": "hdlcd", + "workaround_dma_line_count": true, + "amba_id": 1314816, "pio": { "peer": "system.iobus.master[5]", "role": "SLAVE" }, - "amba_id": 1314816, "pio_latency": 10000, "clk_domain": "system.clk_domain", "system": "system", "gic": "system.realview.gic", "int_num": 117, "eventq_index": 0, + "pixel_buffer_size": 2048, "cxx_class": "HDLcd", "enable_capture": true, "path": "system.realview.hdlcd", "pio_addr": 721420288, "workaround_swap_rb": true, - "type": "HDLcd" + "type": "HDLcd", + "pixel_chunk": 32, + "dma": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + } }, "mmc_fake": { "name": "mmc_fake", @@ -893,7 +896,7 @@ "MSIXCAPNextCapability": 0, "PXCAPLinkCtrl": 0, "Revision": 0, - "hardware_address": "<m5.params.EthernetAddr object at 0x7fd02360a190>", + "hardware_address": "<m5.params.EthernetAddr object at 0x511b690>", "LegacyIOBase": 0, "pio_latency": 30000, "platform": "system.realview", @@ -1176,7 +1179,7 @@ "clk_domain": "system.clk_domain", "write_buffers": 8, "response_latency": 50, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 1024, "tags": { "name": "tags", @@ -1210,7 +1213,7 @@ "prefetch_on_access": false, "path": "system.iocache", "name": "iocache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 8 }, @@ -1416,7 +1419,7 @@ "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, "response_latency": 2, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", @@ -1450,7 +1453,7 @@ "prefetch_on_access": false, "path": "system.cpu.icache", "name": "icache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 1 }, @@ -1505,7 +1508,7 @@ "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, "response_latency": 20, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 4194304, "tags": { "name": "tags", @@ -1539,7 +1542,7 @@ "prefetch_on_access": false, "path": "system.cpu.l2cache", "name": "l2cache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 8 }, @@ -1586,7 +1589,7 @@ "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, "response_latency": 2, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", @@ -1620,7 +1623,7 @@ "prefetch_on_access": false, "path": "system.cpu.dcache", "name": "dcache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 4 }, @@ -1701,7 +1704,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.cf0.image.child", - "image_file": "/work/gem5/dist/disks/linaro-minimal-aarch64.img", + "image_file": "/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img", "type": "RawDiskImage" }, "path": "system.cf0.image", @@ -1741,7 +1744,7 @@ "system.realview.vram" ], "work_begin_cpu_id_exit": -1, - "boot_loader": "/work/gem5/dist/binaries/boot_emm.arm64", + "boot_loader": "/scratch/nilay/GEM5/system/binaries/boot_emm.arm64", "num_work_ids": 16 }, "time_sync_period": 100000000000, diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index 35e369985..3b35220e8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1040961 # Simulator instruction rate (inst/s) -host_op_rate 1223300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54038486240 # Simulator tick rate (ticks/s) -host_mem_usage 670940 # Number of bytes of host memory used -host_seconds 945.83 # Real time elapsed on the host +host_inst_rate 926984 # Simulator instruction rate (inst/s) +host_op_rate 1089358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48121696814 # Simulator tick rate (ticks/s) +host_mem_usage 716268 # Number of bytes of host memory used +host_seconds 1062.12 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -210,7 +210,7 @@ system.cpu.itb.inst_accesses 985174158 # IT system.cpu.itb.hits 985047321 # DTB hits system.cpu.itb.misses 126837 # DTB misses system.cpu.itb.accesses 985174158 # DTB accesses -system.cpu.numCycles 102222322140 # number of cpu cycles simulated +system.cpu.numCycles 102222325018 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 984570519 # Number of instructions committed @@ -230,8 +230,8 @@ system.cpu.num_cc_register_writes 263829403 # nu system.cpu.num_mem_refs 352465606 # number of memory refs system.cpu.num_load_insts 184180431 # Number of load instructions system.cpu.num_store_insts 168285175 # Number of store instructions -system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles -system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles +system.cpu.num_idle_cycles 101064646448.926407 # Number of idle cycles +system.cpu.num_busy_cycles 1157678569.073592 # Number of busy cycles system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles system.cpu.idle_fraction 0.988675 # Percentage of idle cycles system.cpu.Branches 220088562 # Number of branches fetched @@ -271,7 +271,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1157666593 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 19653 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 11612141 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks. @@ -787,13 +787,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini index 0ef1481b3..51a633a32 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -212,7 +212,7 @@ sys=system port=system.cpu0.toL2Bus.slave[3] [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -322,7 +322,7 @@ sys=system port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -440,7 +440,7 @@ dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -516,7 +516,7 @@ sys=system port=system.cpu1.toL2Bus.slave[3] [system.cpu1.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -626,7 +626,7 @@ sys=system port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -739,7 +739,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -774,7 +774,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1125,9 +1125,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 34d0b7d0d..f07b9fa73 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.216814 # Nu sim_ticks 47216814145000 # Number of ticks simulated final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 990548 # Simulator instruction rate (inst/s) -host_op_rate 1165292 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47947296122 # Simulator tick rate (ticks/s) -host_mem_usage 681164 # Number of bytes of host memory used -host_seconds 984.77 # Real time elapsed on the host +host_inst_rate 873779 # Simulator instruction rate (inst/s) +host_op_rate 1027923 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42295108650 # Simulator tick rate (ticks/s) +host_mem_usage 724108 # Number of bytes of host memory used +host_seconds 1116.37 # Real time elapsed on the host sim_insts 975457230 # Number of instructions simulated sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -241,7 +241,7 @@ system.cpu0.itb.inst_accesses 497757770 # IT system.cpu0.itb.hits 497696393 # DTB hits system.cpu0.itb.misses 61377 # DTB misses system.cpu0.itb.accesses 497757770 # DTB accesses -system.cpu0.numCycles 94433641544 # number of cpu cycles simulated +system.cpu0.numCycles 94433643486 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 497466384 # Number of instructions committed @@ -261,8 +261,8 @@ system.cpu0.num_cc_register_writes 133531045 # nu system.cpu0.num_mem_refs 178459396 # number of memory refs system.cpu0.num_load_insts 92737001 # Number of load instructions system.cpu0.num_store_insts 85722395 # Number of store instructions -system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles -system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles +system.cpu0.num_idle_cycles 93848339121.288452 # Number of idle cycles +system.cpu0.num_busy_cycles 585304364.711543 # Number of busy cycles system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles system.cpu0.Branches 111287587 # Number of branches fetched @@ -302,7 +302,7 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 585300003 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 15195 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 6272773 # number of replacements system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 172015769 # Total number of references to valid blocks. @@ -767,7 +767,7 @@ system.cpu1.itb.inst_accesses 478309003 # IT system.cpu1.itb.hits 478248118 # DTB hits system.cpu1.itb.misses 60885 # DTB misses system.cpu1.itb.accesses 478309003 # DTB accesses -system.cpu1.numCycles 94433634550 # number of cpu cycles simulated +system.cpu1.numCycles 94433635490 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 477990846 # Number of instructions committed @@ -787,8 +787,8 @@ system.cpu1.num_cc_register_writes 126112608 # nu system.cpu1.num_mem_refs 171406825 # number of memory refs system.cpu1.num_load_insts 90251973 # Number of load instructions system.cpu1.num_store_insts 81154852 # Number of store instructions -system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles -system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles +system.cpu1.num_idle_cycles 93870751219.397461 # Number of idle cycles +system.cpu1.num_busy_cycles 562884270.602548 # Number of busy cycles system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles system.cpu1.Branches 106497601 # Number of branches fetched @@ -828,7 +828,7 @@ system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 562879339 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 7199 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 5945049 # number of replacements system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. @@ -1551,13 +1551,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini index cc1edf626..160a8ac7f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -136,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -212,7 +212,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -322,7 +322,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -410,7 +410,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -761,9 +761,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout index 343cfe408..31e7c1fe5 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 11:06:10 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 03:06:20 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 51111152682000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 5d4303b7e..47d983423 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1034678 # Simulator instruction rate (inst/s) -host_op_rate 1215917 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53712340974 # Simulator tick rate (ticks/s) -host_mem_usage 668604 # Number of bytes of host memory used -host_seconds 951.57 # Real time elapsed on the host +host_inst_rate 921297 # Simulator instruction rate (inst/s) +host_op_rate 1082675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47826467843 # Simulator tick rate (ticks/s) +host_mem_usage 712064 # Number of bytes of host memory used +host_seconds 1068.68 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -210,7 +210,7 @@ system.cpu.itb.inst_accesses 985174158 # IT system.cpu.itb.hits 985047321 # DTB hits system.cpu.itb.misses 126837 # DTB misses system.cpu.itb.accesses 985174158 # DTB accesses -system.cpu.numCycles 102222322140 # number of cpu cycles simulated +system.cpu.numCycles 102222325018 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 984570519 # Number of instructions committed @@ -230,8 +230,8 @@ system.cpu.num_cc_register_writes 263829403 # nu system.cpu.num_mem_refs 352465606 # number of memory refs system.cpu.num_load_insts 184180431 # Number of load instructions system.cpu.num_store_insts 168285175 # Number of store instructions -system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles -system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles +system.cpu.num_idle_cycles 101064646448.926407 # Number of idle cycles +system.cpu.num_busy_cycles 1157678569.073592 # Number of busy cycles system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles system.cpu.idle_fraction 0.988675 # Percentage of idle cycles system.cpu.Branches 220088562 # Number of branches fetched @@ -271,7 +271,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1157666593 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 19653 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 11612141 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks. @@ -787,13 +787,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini index 11e85042f..351e6eb6d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -132,7 +132,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -208,7 +208,7 @@ sys=system port=system.cpu0.toL2Bus.slave[3] [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -318,7 +318,7 @@ sys=system port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -432,7 +432,7 @@ dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -508,7 +508,7 @@ sys=system port=system.cpu1.toL2Bus.slave[3] [system.cpu1.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -618,7 +618,7 @@ sys=system port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -731,7 +731,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -766,7 +766,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1181,9 +1181,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout index 76a99086b..2db4f0fce 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 11:24:22 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 02:37:28 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 47456679626500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 11d99eddf..05fb68c75 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.456680 # Nu sim_ticks 47456679626500 # Number of ticks simulated final_tick 47456679626500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 617984 # Simulator instruction rate (inst/s) -host_op_rate 726985 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33898978760 # Simulator tick rate (ticks/s) -host_mem_usage 711884 # Number of bytes of host memory used -host_seconds 1399.94 # Real time elapsed on the host +host_inst_rate 503190 # Simulator instruction rate (inst/s) +host_op_rate 591944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27602071667 # Simulator tick rate (ticks/s) +host_mem_usage 755208 # Number of bytes of host memory used +host_seconds 1719.32 # Real time elapsed on the host sim_insts 865142471 # Number of instructions simulated sim_ops 1017738631 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -625,7 +625,7 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 502778486 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 14022 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 15090 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 5233253 # number of replacements system.cpu0.dcache.tags.tagsinuse 480.798924 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 147607157 # Total number of references to valid blocks. @@ -1613,7 +1613,7 @@ system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 515545598 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5256 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 7070 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 5176711 # number of replacements system.cpu1.dcache.tags.tagsinuse 457.282743 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 152806636 # Total number of references to valid blocks. @@ -3222,13 +3222,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini index b1ceb0f38..aef164157 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -132,7 +132,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -208,7 +208,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -318,7 +318,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -406,7 +406,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -821,9 +821,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout index 608cdb063..602235712 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 11:22:13 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 00:24:53 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 51832458543500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 829b00030..f9e8bd96f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.832459 # Nu sim_ticks 51832458543500 # Number of ticks simulated final_tick 51832458543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 643815 # Simulator instruction rate (inst/s) -host_op_rate 756535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37796716864 # Simulator tick rate (ticks/s) -host_mem_usage 668604 # Number of bytes of host memory used -host_seconds 1371.35 # Real time elapsed on the host +host_inst_rate 536175 # Simulator instruction rate (inst/s) +host_op_rate 630049 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31477440084 # Simulator tick rate (ticks/s) +host_mem_usage 712068 # Number of bytes of host memory used +host_seconds 1646.65 # Real time elapsed on the host sim_insts 882895003 # Number of instructions simulated sim_ops 1037473525 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -584,7 +584,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1038060895 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16280 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 19158 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 10067650 # number of replacements system.cpu.dcache.tags.tagsinuse 511.966034 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 306351638 # Total number of references to valid blocks. @@ -1588,13 +1588,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini index ab5c7b693..140fedafe 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -212,7 +212,7 @@ sys=system port=system.toL2Bus.slave[3] [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -511,7 +511,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -546,7 +546,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -897,9 +897,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index bd6e6276d..25d466362 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1034928 # Simulator instruction rate (inst/s) -host_op_rate 1216210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53725315382 # Simulator tick rate (ticks/s) -host_mem_usage 668860 # Number of bytes of host memory used -host_seconds 951.34 # Real time elapsed on the host +host_inst_rate 916811 # Simulator instruction rate (inst/s) +host_op_rate 1077403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47593586653 # Simulator tick rate (ticks/s) +host_mem_usage 712068 # Number of bytes of host memory used +host_seconds 1073.91 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -228,7 +228,7 @@ system.cpu0.itb.inst_accesses 493628912 # IT system.cpu0.itb.hits 493558289 # DTB hits system.cpu0.itb.misses 70623 # DTB misses system.cpu0.itb.accesses 493628912 # DTB accesses -system.cpu0.numCycles 98036732821 # number of cpu cycles simulated +system.cpu0.numCycles 98036734134 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 493343054 # Number of instructions committed @@ -248,8 +248,8 @@ system.cpu0.num_cc_register_writes 132723498 # nu system.cpu0.num_mem_refs 176296730 # number of memory refs system.cpu0.num_load_insts 91967123 # Number of load instructions system.cpu0.num_store_insts 84329607 # Number of store instructions -system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles -system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles +system.cpu0.num_idle_cycles 96926192639.173721 # Number of idle cycles +system.cpu0.num_busy_cycles 1110541494.826277 # Number of busy cycles system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles system.cpu0.Branches 110281342 # Number of branches fetched @@ -289,7 +289,7 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 579643698 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 19653 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 11612141 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks. @@ -612,7 +612,7 @@ system.cpu1.itb.inst_accesses 491545246 # IT system.cpu1.itb.hits 491475383 # DTB hits system.cpu1.itb.misses 69863 # DTB misses system.cpu1.itb.accesses 491545246 # DTB accesses -system.cpu1.numCycles 97463064529 # number of cpu cycles simulated +system.cpu1.numCycles 97463066094 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 491227465 # Number of instructions committed @@ -632,8 +632,8 @@ system.cpu1.num_cc_register_writes 131105905 # nu system.cpu1.num_mem_refs 176168876 # number of memory refs system.cpu1.num_load_insts 92213308 # Number of load instructions system.cpu1.num_store_insts 83955568 # Number of store instructions -system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles -system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles +system.cpu1.num_idle_cycles 96357045557.909821 # Number of idle cycles +system.cpu1.num_busy_cycles 1106020536.090176 # Number of busy cycles system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles system.cpu1.Branches 109807220 # Number of branches fetched @@ -1080,13 +1080,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini index 92fcc1d90..fed55ceb4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -212,7 +212,7 @@ sys=system port=system.toL2Bus.slave[3] [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -1610,7 +1610,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1645,7 +1645,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -2060,9 +2060,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr index d502db8d0..4873ce7b9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr @@ -23,8 +23,6 @@ warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11735, Bank: 6 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -41,28 +39,16 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8760, Bank: 1 -WARNING: Bank is not active! -Command: 1, Timestamp: 5113, Bank: 5 -WARNING: Bank is already active! -Command: 0, Timestamp: 8082, Bank: 5 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 10604, Bank: 7 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 9156, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -75,14 +61,12 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -125,6 +109,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -149,14 +135,12 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -165,8 +149,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -175,10 +157,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -199,6 +181,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -209,10 +193,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7012, Bank: 7 -WARNING: Bank is already active! -Command: 0, Timestamp: 10303, Bank: 6 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -229,22 +209,28 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 6518, Bank: 4 +WARNING: Bank is already active! +Command: 0, Timestamp: 12331, Bank: 6 +WARNING: Bank is already active! +Command: 0, Timestamp: 9979, Bank: 4 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8446, Bank: 6 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: Bank is already active! -Command: 0, Timestamp: 10805, Bank: 3 +Command: 0, Timestamp: 6448, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 10161, Bank: 1 +WARNING: Bank is already active! +Command: 0, Timestamp: 11757, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -261,6 +247,16 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 6448, Bank: 5 +WARNING: Bank is already active! +Command: 0, Timestamp: 6479, Bank: 5 +WARNING: Bank is already active! +Command: 0, Timestamp: 6448, Bank: 6 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -273,12 +269,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7980, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -291,32 +289,22 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 11719, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 10011, Bank: 1 +Command: 0, Timestamp: 7906, Bank: 3 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11449, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -335,18 +323,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 6626, Bank: 3 -warn: User mode does not have SPSR -warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -369,28 +349,22 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 9676, Bank: 5 -WARNING: Bank is already active! -Command: 0, Timestamp: 10242, Bank: 1 -WARNING: Bank is already active! -Command: 0, Timestamp: 10403, Bank: 7 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 11427, Bank: 7 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -413,8 +387,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 9256, Bank: 6 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -423,28 +395,18 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 9641, Bank: 4 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -453,10 +415,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -477,10 +435,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -493,24 +449,16 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6826, Bank: 1 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 7179, Bank: 6 -WARNING: Bank is already active! -Command: 0, Timestamp: 8996, Bank: 7 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11485, Bank: 4 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -523,10 +471,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -535,20 +491,22 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 4 -WARNING: Bank is already active! -Command: 0, Timestamp: 10203, Bank: 6 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -573,6 +531,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -593,12 +555,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -611,8 +567,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -633,8 +587,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 8213, Bank: 7 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -643,6 +603,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -651,6 +615,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -667,10 +635,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -681,10 +657,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -705,10 +677,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6550, Bank: 4 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -719,8 +689,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7188, Bank: 5 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -729,12 +699,20 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7000, Bank: 1 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -751,18 +729,20 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -779,8 +759,18 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 6448, Bank: 7 +WARNING: Bank is already active! +Command: 0, Timestamp: 10397, Bank: 4 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -799,16 +789,24 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7532, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7045, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -827,10 +825,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7487, Bank: 6 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -845,10 +839,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -861,10 +851,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -873,8 +859,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -891,14 +875,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 10743, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -907,6 +891,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -923,14 +909,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -939,10 +917,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -961,18 +947,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -995,10 +973,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1007,10 +981,18 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 9050, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 11416, Bank: 6 +WARNING: Bank is already active! +Command: 0, Timestamp: 8249, Bank: 1 WARNING: Bank is already active! -Command: 0, Timestamp: 11000, Bank: 4 +Command: 0, Timestamp: 9760, Bank: 4 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1027,14 +1009,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1043,10 +1017,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1071,20 +1041,22 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1095,6 +1067,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1125,14 +1099,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7339, Bank: 7 +Command: 0, Timestamp: 7036, Bank: 4 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1149,10 +1117,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 12368, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1165,24 +1129,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7706, Bank: 7 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1217,6 +1175,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1232,15 +1198,23 @@ warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7794, Bank: 5 +Command: 0, Timestamp: 8714, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 10622, Bank: 2 +Command: 0, Timestamp: 7453, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: Bank is already active! -Command: 0, Timestamp: 8145, Bank: 1 +Command: 0, Timestamp: 6792, Bank: 5 WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 7 +Command: 0, Timestamp: 10152, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1261,16 +1235,16 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 11476, Bank: 4 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1281,16 +1255,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1305,6 +1277,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9430, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1321,10 +1295,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1345,6 +1315,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1365,8 +1339,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 10803, Bank: 6 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index 5a4eed10a..17066f3b8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,192 +1,192 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.316635 # Number of seconds simulated -sim_ticks 51316634750000 # Number of ticks simulated -final_tick 51316634750000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.276903 # Number of seconds simulated +sim_ticks 51276903265000 # Number of ticks simulated +final_tick 51276903265000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 261197 # Simulator instruction rate (inst/s) -host_op_rate 306920 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15666770859 # Simulator tick rate (ticks/s) -host_mem_usage 680896 # Number of bytes of host memory used -host_seconds 3275.51 # Real time elapsed on the host -sim_insts 855554018 # Number of instructions simulated -sim_ops 1005318688 # Number of ops (including micro ops) simulated +host_inst_rate 195122 # Simulator instruction rate (inst/s) +host_op_rate 229284 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11700811305 # Simulator tick rate (ticks/s) +host_mem_usage 723460 # Number of bytes of host memory used +host_seconds 4382.34 # Real time elapsed on the host +sim_insts 855091424 # Number of instructions simulated +sim_ops 1004800608 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 86272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 87040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2475252 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 44191944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 26688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 26112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 701824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 6588352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 27264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 23232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1769600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 8688000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 64576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 58944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1797376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 16165440 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417344 # Number of bytes read from this memory -system.physmem.bytes_read::total 83195260 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2475252 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 701824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1769600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1797376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6744052 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70299712 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 83904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 91648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2486836 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 43860424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 20800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 20224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 650944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 6302784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 33152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 28032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1597440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 8824832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 59456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1836416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 15839168 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 414400 # Number of bytes read from this memory +system.physmem.bytes_read::total 82215292 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2486836 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 650944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1597440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1836416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6571636 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69835456 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 70320292 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 79083 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 690512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 102943 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 426 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 27650 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 135750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 1009 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 28084 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 252585 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6521 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1340346 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1098433 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69856036 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1311 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 79264 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 685332 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 316 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 98481 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 24960 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 137888 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 28694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 247487 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6475 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1325034 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1091179 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1101006 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 48235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 861162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 13676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 128386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 34484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 169302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 35025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 315014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1621214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 48235 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 13676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 34484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 35025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 131420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1369921 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1093752 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 48498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 855364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 12695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 122917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 31153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 172102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 35814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 308895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1603359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 48498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 12695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 31153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 35814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 128160 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1361928 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1370322 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1369921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 48235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 861563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 13676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 128386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 34484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 169302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1258 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 35025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 315014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2991536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 565119 # Number of read requests accepted -system.physmem.writeReqs 485303 # Number of write requests accepted -system.physmem.readBursts 565119 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 485303 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 36124864 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 42752 # Total number of bytes read from write queue -system.physmem.bytesWritten 31057472 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 36167616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 31059392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 668 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 65964 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 37092 # Per bank write bursts -system.physmem.perBankRdBursts::1 38221 # Per bank write bursts -system.physmem.perBankRdBursts::2 34232 # Per bank write bursts -system.physmem.perBankRdBursts::3 34199 # Per bank write bursts -system.physmem.perBankRdBursts::4 32555 # Per bank write bursts -system.physmem.perBankRdBursts::5 36931 # Per bank write bursts -system.physmem.perBankRdBursts::6 31211 # Per bank write bursts -system.physmem.perBankRdBursts::7 33972 # Per bank write bursts -system.physmem.perBankRdBursts::8 32403 # Per bank write bursts -system.physmem.perBankRdBursts::9 38255 # Per bank write bursts -system.physmem.perBankRdBursts::10 35917 # Per bank write bursts -system.physmem.perBankRdBursts::11 41761 # Per bank write bursts -system.physmem.perBankRdBursts::12 35252 # Per bank write bursts -system.physmem.perBankRdBursts::13 36878 # Per bank write bursts -system.physmem.perBankRdBursts::14 32220 # Per bank write bursts -system.physmem.perBankRdBursts::15 33352 # Per bank write bursts -system.physmem.perBankWrBursts::0 29650 # Per bank write bursts -system.physmem.perBankWrBursts::1 31742 # Per bank write bursts -system.physmem.perBankWrBursts::2 28889 # Per bank write bursts -system.physmem.perBankWrBursts::3 30829 # Per bank write bursts -system.physmem.perBankWrBursts::4 29399 # Per bank write bursts -system.physmem.perBankWrBursts::5 32279 # Per bank write bursts -system.physmem.perBankWrBursts::6 27374 # Per bank write bursts -system.physmem.perBankWrBursts::7 30609 # Per bank write bursts -system.physmem.perBankWrBursts::8 28675 # Per bank write bursts -system.physmem.perBankWrBursts::9 32426 # Per bank write bursts -system.physmem.perBankWrBursts::10 29991 # Per bank write bursts -system.physmem.perBankWrBursts::11 34263 # Per bank write bursts -system.physmem.perBankWrBursts::12 30290 # Per bank write bursts -system.physmem.perBankWrBursts::13 31646 # Per bank write bursts -system.physmem.perBankWrBursts::14 28165 # Per bank write bursts -system.physmem.perBankWrBursts::15 29046 # Per bank write bursts +system.physmem.bw_write::total 1362329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1361928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 48498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 855765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 12695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 122917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 31153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 172102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 35814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 308895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2965689 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 552891 # Number of read requests accepted +system.physmem.writeReqs 477788 # Number of write requests accepted +system.physmem.readBursts 552891 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 477788 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 35353984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31040 # Total number of bytes read from write queue +system.physmem.bytesWritten 30577024 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 35385024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 30578432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 485 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 65706 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 34049 # Per bank write bursts +system.physmem.perBankRdBursts::1 38611 # Per bank write bursts +system.physmem.perBankRdBursts::2 36089 # Per bank write bursts +system.physmem.perBankRdBursts::3 33688 # Per bank write bursts +system.physmem.perBankRdBursts::4 32444 # Per bank write bursts +system.physmem.perBankRdBursts::5 38213 # Per bank write bursts +system.physmem.perBankRdBursts::6 33143 # Per bank write bursts +system.physmem.perBankRdBursts::7 35180 # Per bank write bursts +system.physmem.perBankRdBursts::8 30999 # Per bank write bursts +system.physmem.perBankRdBursts::9 38487 # Per bank write bursts +system.physmem.perBankRdBursts::10 32534 # Per bank write bursts +system.physmem.perBankRdBursts::11 34124 # Per bank write bursts +system.physmem.perBankRdBursts::12 34391 # Per bank write bursts +system.physmem.perBankRdBursts::13 36689 # Per bank write bursts +system.physmem.perBankRdBursts::14 30748 # Per bank write bursts +system.physmem.perBankRdBursts::15 33017 # Per bank write bursts +system.physmem.perBankWrBursts::0 28228 # Per bank write bursts +system.physmem.perBankWrBursts::1 31813 # Per bank write bursts +system.physmem.perBankWrBursts::2 30334 # Per bank write bursts +system.physmem.perBankWrBursts::3 30276 # Per bank write bursts +system.physmem.perBankWrBursts::4 29074 # Per bank write bursts +system.physmem.perBankWrBursts::5 32329 # Per bank write bursts +system.physmem.perBankWrBursts::6 29378 # Per bank write bursts +system.physmem.perBankWrBursts::7 31367 # Per bank write bursts +system.physmem.perBankWrBursts::8 28134 # Per bank write bursts +system.physmem.perBankWrBursts::9 32950 # Per bank write bursts +system.physmem.perBankWrBursts::10 28173 # Per bank write bursts +system.physmem.perBankWrBursts::11 29809 # Per bank write bursts +system.physmem.perBankWrBursts::12 29393 # Per bank write bursts +system.physmem.perBankWrBursts::13 31102 # Per bank write bursts +system.physmem.perBankWrBursts::14 26687 # Per bank write bursts +system.physmem.perBankWrBursts::15 28719 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 51315634470500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 51275902957500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 565119 # Read request sizes (log2) +system.physmem.readPktSize::6 552891 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 485303 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 399408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 101730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 477788 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 390834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 101245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -198,188 +198,189 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 570 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 567 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 8616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 19482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 23454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 26479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 28098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 28044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 29307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 29679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 31078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 30832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 30867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 29853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 28794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 28945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 27599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 278814 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.955476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 145.236301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 282.316846 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 127586 45.76% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 69517 24.93% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25415 9.12% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12865 4.61% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9508 3.41% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5843 2.10% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4935 1.77% 91.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3869 1.39% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19276 6.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 278814 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 27347 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.639193 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 13.469110 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-31 24770 90.58% 90.58% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-63 2374 8.68% 99.26% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-95 169 0.62% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-127 20 0.07% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-159 3 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::160-191 2 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::192-223 2 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::224-255 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::8 560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 554 # What write queue length does an incoming req see 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queue length does an incoming req see +system.physmem.wrQLenPdf::25 30179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 30394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 29233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 29969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 28250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 28349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 27090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see 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an incoming req see +system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 274210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.439605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.938897 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 282.109659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 125716 45.85% 45.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 68438 24.96% 70.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25021 9.12% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12508 4.56% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9258 3.38% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5639 2.06% 89.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4828 1.76% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3908 1.43% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18894 6.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 274210 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 26911 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.526067 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 11.794562 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-31 24375 90.58% 90.58% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-63 2332 8.67% 99.24% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-95 174 0.65% 99.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-127 18 0.07% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-159 4 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::160-191 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::192-223 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::224-255 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::256-287 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::320-351 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::704-735 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::736-767 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::928-959 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 27347 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 27347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.745018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.170209 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.144032 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 15 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 12 0.04% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.03% 0.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 33 0.12% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 25607 93.64% 93.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 450 1.65% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 306 1.12% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 171 0.63% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 124 0.45% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 194 0.71% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 52 0.19% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.04% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 30 0.11% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.08% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 22 0.08% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.04% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 180 0.66% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 15 0.05% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 25 0.09% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 19 0.07% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 27347 # Writes before turning the bus around for reads -system.physmem.totQLat 11691794846 # Total ticks spent queuing -system.physmem.totMemAccLat 22275251096 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2822255000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20713.57 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::544-575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-799 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 26911 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 26911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.753558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.172751 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.257743 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 17 0.06% 0.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.03% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 13 0.05% 0.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 46 0.17% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 25176 93.55% 93.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 431 1.60% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 320 1.19% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 165 0.61% 97.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 117 0.43% 97.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 198 0.74% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 59 0.22% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.07% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 21 0.08% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.06% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 22 0.08% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.04% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 188 0.70% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 14 0.05% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 18 0.07% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.05% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 26911 # Writes before turning the bus around for reads +system.physmem.totQLat 11450608424 # Total ticks spent queuing +system.physmem.totMemAccLat 21808220924 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2762030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20728.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39463.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.61 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.70 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39478.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.69 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.89 # Average write queue length when enqueuing -system.physmem.readRowHits 432443 # Number of row buffer hits during reads -system.physmem.writeRowHits 338466 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.74 # Row buffer hit rate for writes -system.physmem.avgGap 48852398.82 # Average gap between requests -system.physmem.pageHitRate 73.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1049600160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 571056750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2171551200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1560196080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3312990217680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1178995763115 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29844954866250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34342293251235 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.290653 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48908598729306 # Time in different power states -system.physmem_0.memoryStateTime::REF 1693757780000 # Time in different power states +system.physmem.avgWrQLen 9.42 # Average write queue length when enqueuing +system.physmem.readRowHits 422970 # Number of row buffer hits during reads +system.physmem.writeRowHits 332991 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.69 # Row buffer hit rate for writes +system.physmem.avgGap 49749633.94 # Average gap between requests +system.physmem.pageHitRate 73.38 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1067305680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 580820625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2194982400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1573337520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3310526753040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1179597405240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30106177853250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34601718457755 # Total energy per rank (pJ) +system.physmem_0.averagePower 666.680244 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48870107005920 # Time in different power states +system.physmem_0.memoryStateTime::REF 1692498340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 121315217444 # Time in different power states +system.physmem_0.memoryStateTime::ACT 123346652830 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1058233680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 575746875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2231096400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1584372960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3312990217680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1180768405545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 30633804913500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 35133012986640 # Total energy per rank (pJ) -system.physmem_1.averagePower 665.617184 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48905982752444 # Time in different power states -system.physmem_1.memoryStateTime::REF 1693757780000 # Time in different power states +system.physmem_1.actEnergy 1005699240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 547226625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2113714200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1522586160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3310526753040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1176042513600 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29757652392000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34249410884865 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.428862 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48875263841452 # Time in different power states +system.physmem_1.memoryStateTime::REF 1692498340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 123922534306 # Time in different power states +system.physmem_1.memoryStateTime::ACT 118168635298 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -439,47 +440,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 91446 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 91446 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 91446 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 91446 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 91446 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 388607264328 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.523233 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -203332229172 -52.32% -52.32% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 591939493500 152.32% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 388607264328 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 66855 84.61% 84.61% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 12161 15.39% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 79016 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91446 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 90619 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 90619 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 90619 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 90619 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 90619 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 391820506288 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.505623 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -198113446712 -50.56% -50.56% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 589933953000 150.56% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 391820506288 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 66457 84.78% 84.78% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11934 15.22% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 78391 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90619 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91446 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 79016 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90619 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78391 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 79016 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 170462 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78391 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 169010 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 64637193 # DTB read hits -system.cpu0.dtb.read_misses 69043 # DTB read misses -system.cpu0.dtb.write_hits 58569418 # DTB write hits -system.cpu0.dtb.write_misses 22403 # DTB write misses -system.cpu0.dtb.flush_tlb 1193 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 64357240 # DTB read hits +system.cpu0.dtb.read_misses 68494 # DTB read misses +system.cpu0.dtb.write_hits 58282336 # DTB write hits +system.cpu0.dtb.write_misses 22125 # DTB write misses +system.cpu0.dtb.flush_tlb 1188 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16284 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 407 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 42446 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16028 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 418 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 42200 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2875 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2748 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7756 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 64706236 # DTB read accesses -system.cpu0.dtb.write_accesses 58591821 # DTB write accesses +system.cpu0.dtb.perms_faults 7647 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64425734 # DTB read accesses +system.cpu0.dtb.write_accesses 58304461 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 123206611 # DTB hits -system.cpu0.dtb.misses 91446 # DTB misses -system.cpu0.dtb.accesses 123298057 # DTB accesses +system.cpu0.dtb.hits 122639576 # DTB hits +system.cpu0.dtb.misses 90619 # DTB misses +system.cpu0.dtb.accesses 122730195 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -509,695 +510,695 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 53719 # Table walker walks requested -system.cpu0.itb.walker.walksLong 53719 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 53719 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 53719 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 53719 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 388607264328 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.523329 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -203369594172 -52.33% -52.33% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 591976858500 152.33% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 388607264328 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 46750 94.94% 94.94% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2490 5.06% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 49240 # Table walker page sizes translated +system.cpu0.itb.walker.walks 53743 # Table walker walks requested +system.cpu0.itb.walker.walksLong 53743 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 53743 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 53743 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 53743 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 391820506288 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.505732 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -198156351712 -50.57% -50.57% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 589976858000 150.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 391820506288 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 46842 94.98% 94.98% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2476 5.02% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 49318 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53719 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53719 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53743 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53743 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49240 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49240 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 102959 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 343542724 # ITB inst hits -system.cpu0.itb.inst_misses 53719 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49318 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49318 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 103061 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 342266306 # ITB inst hits +system.cpu0.itb.inst_misses 53743 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1193 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1188 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16284 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 407 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 30063 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16028 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 418 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29888 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 343596443 # ITB inst accesses -system.cpu0.itb.hits 343542724 # DTB hits -system.cpu0.itb.misses 53719 # DTB misses -system.cpu0.itb.accesses 343596443 # DTB accesses -system.cpu0.numCycles 414507923 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 342320049 # ITB inst accesses +system.cpu0.itb.hits 342266306 # DTB hits +system.cpu0.itb.misses 53743 # DTB misses +system.cpu0.itb.accesses 342320049 # DTB accesses +system.cpu0.numCycles 413032183 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 343392928 # Number of instructions committed -system.cpu0.committedOps 403926056 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 371010641 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 350352 # Number of float alu accesses -system.cpu0.num_func_calls 20655596 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 52208909 # number of instructions that are conditional controls -system.cpu0.num_int_insts 371010641 # number of integer instructions -system.cpu0.num_fp_insts 350352 # number of float instructions -system.cpu0.num_int_register_reads 542983655 # number of times the integer registers were read -system.cpu0.num_int_register_writes 294627893 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 558017 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 311708 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 89970579 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 89777589 # number of times the CC registers were written -system.cpu0.num_mem_refs 123282310 # number of memory refs -system.cpu0.num_load_insts 64695790 # Number of load instructions -system.cpu0.num_store_insts 58586520 # Number of store instructions -system.cpu0.num_idle_cycles 404635948.136490 # Number of idle cycles -system.cpu0.num_busy_cycles 9871974.863510 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023816 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976184 # Percentage of idle cycles -system.cpu0.Branches 76586966 # Number of branches fetched +system.cpu0.committedInsts 342117440 # Number of instructions committed +system.cpu0.committedOps 402438329 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 369654139 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 360090 # Number of float alu accesses +system.cpu0.num_func_calls 20604842 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 52004192 # number of instructions that are conditional controls +system.cpu0.num_int_insts 369654139 # number of integer instructions +system.cpu0.num_fp_insts 360090 # number of float instructions +system.cpu0.num_int_register_reads 540778381 # number of times the integer registers were read +system.cpu0.num_int_register_writes 293614649 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 575012 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 316800 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 89609832 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89403726 # number of times the CC registers were written +system.cpu0.num_mem_refs 122714331 # number of memory refs +system.cpu0.num_load_insts 64415463 # Number of load instructions +system.cpu0.num_store_insts 58298868 # Number of store instructions +system.cpu0.num_idle_cycles 403076556.915137 # Number of idle cycles +system.cpu0.num_busy_cycles 9955626.084863 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024104 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975896 # Percentage of idle cycles +system.cpu0.Branches 76323262 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 279907726 69.26% 69.26% # Class of executed instruction -system.cpu0.op_class::IntMult 889275 0.22% 69.48% # Class of executed instruction -system.cpu0.op_class::IntDiv 42026 0.01% 69.49% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 46880 0.01% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::MemRead 64695790 16.01% 85.50% # Class of executed instruction -system.cpu0.op_class::MemWrite 58586520 14.50% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 278992555 69.28% 69.28% # Class of executed instruction +system.cpu0.op_class::IntMult 883395 0.22% 69.50% # Class of executed instruction +system.cpu0.op_class::IntDiv 42520 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 46836 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::MemRead 64415463 16.00% 85.52% # Class of executed instruction +system.cpu0.op_class::MemWrite 58298868 14.48% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 404168217 # Class of executed instruction +system.cpu0.op_class::total 402679638 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed 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Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1252278840 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1252278840 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 60369359 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 19140658 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 26830987 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 45818234 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 152159238 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 55384084 # number of WriteReq hits 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SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1189294 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 668357 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 105494 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 155232 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 298331 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1227414 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 93062 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 37431 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 50097 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 180259 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 360849 # number of LoadLockedReq misses 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accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.076550 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.157657 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095470 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000003 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024709 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023300 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030573 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.075566 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041059 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028882 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026924 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034195 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.078839 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.044786 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15615.719024 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15814.139139 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15233.519387 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10859.402128 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27789.017123 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27132.935131 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27709.237743 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23175.499007 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25453.793581 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 27629.721965 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35947.368215 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14419.302539 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14046.365312 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14200.261493 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12434.086509 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9639.810558 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 35625 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 35625 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19110.494479 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20249.153175 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21543.374069 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16072.340996 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16456.235657 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18007.647323 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20548.863572 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14656.871123 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 12269651 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 11721 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 884921 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 303 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.865250 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 38.683168 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024744 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023223 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030446 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076330 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041302 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028890 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026744 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034189 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.079619 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045031 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15313.831711 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15844.924697 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14882.588274 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10692.617325 # average ReadReq miss latency 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16243.765228 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18075.674648 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20253.068763 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14538.885855 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 12171442 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 9970 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 893773 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 243 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.618046 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 41.028807 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed 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ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 821405500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 838200500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2775038000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1040608000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 744829000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 810242500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2595679500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2156040000 # number of overall MSHR uncacheable cycles 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of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 8948924500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12450643000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 23749051500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45148619000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6583355500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9198762000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17328942473 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33111059973 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2410482500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3025654000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 5045013000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10481149500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2532564500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 4225854500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10181517242 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 16939936242 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 374149000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 474867500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 928593000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1777609500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 127000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 127000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 15532280000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 21649405000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 41077993973 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 78259678973 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 17942762500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 24675059000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 46123006973 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 88740828473 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1021104000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 786468000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 830220000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2637792000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943050500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 717793000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 802384000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2463227500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1964154500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1504261000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1632604000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5101019500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031392 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030540 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031917 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019125 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013825 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014605 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014132 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008553 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745136 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.717351 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.738337 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.423697 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.710549 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.741652 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.744275 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.358262 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060128 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.059351 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060890 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035791 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023155 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023277 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023401 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.014088 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026774 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.026936 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.026871 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.016233 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14582.883002 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14716.654617 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15284.079431 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14978.730200 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26725.268093 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25692.604543 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29203.657466 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27652.581812 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17482.763631 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14944.295833 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15257.286093 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15633.827010 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24453.793581 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 26631.516214 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34917.602193 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30625.733688 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12906.166358 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12951.914652 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13262.538301 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13098.909112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 34625 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34625 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18060.068470 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17894.733506 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 19145.127390 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18562.034952 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17979.566040 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17480.358952 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18626.606006 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18161.839600 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176213.586098 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 168701.067981 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 173900.518672 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173234.159436 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180191.861472 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 169394.814646 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180736.671872 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177119.037871 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178111.524164 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 169030.271962 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 177194.775879 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175090.222990 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023071 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023060 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023697 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.014162 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026587 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.026841 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027193 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.016328 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14277.502652 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14787.180118 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15118.454800 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14853.283235 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26498.987675 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25824.855839 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 28987.083773 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27536.284170 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17428.114381 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14825.314694 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15186.170837 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15536.651655 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23386.441288 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 27531.252240 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34394.112801 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30368.649257 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13218.477301 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12805.530836 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13200.929730 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13096.562318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 42333.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 42333.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17746.654281 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18068.469279 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18941.464408 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18448.373449 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17703.185293 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17596.460464 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18442.622462 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18048.863368 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171700.689423 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170194.330232 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 174050.314465 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171977.572043 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 175190.507152 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 171188.409254 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180839.305837 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175781.595661 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173358.737864 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170667.233946 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 177322.037580 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173793.720827 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 15815402 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.974774 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 560516546 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15815914 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.440035 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10320548500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 470.983323 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.370310 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.740928 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 11.880214 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.919889 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006583 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 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-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12486.467351 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12458.323950 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12518.206294 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12470.099645 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12486.467351 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 358138 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 358138 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 358138 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 358138 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 358138 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 358138 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1724189 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3891179 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4655514 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10270882 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 1724189 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 3891179 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 4655514 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 10270882 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 1724189 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 3891179 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 4655514 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10270882 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21410290500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 48525407500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 58117116880 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 128052814880 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21410290500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 48525407500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 58117116880 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 128052814880 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21410290500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48525407500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 58117116880 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 128052814880 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015794 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.055547 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.086582 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017853 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015794 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055547 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.086582 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017853 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015794 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055547 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.086582 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017853 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12417.600681 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12470.618160 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12483.501689 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12467.557789 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12417.600681 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12470.618160 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12483.501689 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12467.557789 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12417.600681 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12470.618160 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12483.501689 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12467.557789 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1228,67 +1229,68 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 31331 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 31331 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4585 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 22783 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walks 32157 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 32157 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4670 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23647 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 31326 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 31326 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 31326 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 27373 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24398.385270 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21301.040403 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13057.600682 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 17904 65.41% 65.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9272 33.87% 99.28% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 108 0.39% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 61 0.22% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 4 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 12 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 5 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 27373 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2726095120 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.627697 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.483419 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1014934000 37.23% 37.23% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1711161120 62.77% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2726095120 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 22783 83.25% 83.25% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4585 16.75% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 27368 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31331 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 32152 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 32152 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 32152 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 28322 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24465.680390 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21462.893478 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 12624.124225 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 18193 64.24% 64.24% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9967 35.19% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 97 0.34% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 42 0.15% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 3 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 9 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 28322 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -3003382012 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.339073 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1018364500 -33.91% -33.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -4021746512 133.91% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -3003382012 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 23647 83.51% 83.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4670 16.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 28317 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32157 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31331 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27368 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 32157 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 28317 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27368 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 58699 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28317 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 60474 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 20435080 # DTB read hits -system.cpu1.dtb.read_misses 24017 # DTB read misses -system.cpu1.dtb.write_hits 18473169 # DTB write hits -system.cpu1.dtb.write_misses 7314 # DTB write misses -system.cpu1.dtb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 20628760 # DTB read hits +system.cpu1.dtb.read_misses 24754 # DTB read misses +system.cpu1.dtb.write_hits 18600606 # DTB write hits +system.cpu1.dtb.write_misses 7403 # DTB write misses +system.cpu1.dtb.flush_tlb 1180 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5397 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 130 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 17737 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5222 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 123 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 17774 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 965 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 948 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2574 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 20459097 # DTB read accesses -system.cpu1.dtb.write_accesses 18480483 # DTB write accesses +system.cpu1.dtb.perms_faults 2501 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20653514 # DTB read accesses +system.cpu1.dtb.write_accesses 18608009 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 38908249 # DTB hits -system.cpu1.dtb.misses 31331 # DTB misses -system.cpu1.dtb.accesses 38939580 # DTB accesses +system.cpu1.dtb.hits 39229366 # DTB hits +system.cpu1.dtb.misses 32157 # DTB misses +system.cpu1.dtb.accesses 39261523 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1318,135 +1320,134 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 20082 # Table walker walks requested -system.cpu1.itb.walker.walksLong 20082 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 956 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17736 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 20082 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 20082 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 20082 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 18692 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27635.592767 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24782.304535 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14713.760053 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 9635 51.55% 51.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 8833 47.26% 98.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 80 0.43% 99.23% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 115 0.62% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 1 0.01% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 12 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 3 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 3 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 18692 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 20715 # Table walker walks requested +system.cpu1.itb.walker.walksLong 20715 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 930 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18416 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 20715 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 20715 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 20715 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 19346 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27414.659361 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24764.281979 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13419.535342 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 9905 51.20% 51.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 9256 47.84% 99.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 65 0.34% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 99 0.51% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 1 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 7 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 19346 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 17736 94.89% 94.89% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 956 5.11% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 18692 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 18416 95.19% 95.19% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 930 4.81% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 19346 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20082 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20082 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20715 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20715 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18692 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18692 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 38774 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 109086545 # ITB inst hits -system.cpu1.itb.inst_misses 20082 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 19346 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 19346 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 40061 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 109170509 # ITB inst hits +system.cpu1.itb.inst_misses 20715 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1180 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5397 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 130 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13123 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5222 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 123 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13293 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 109106627 # ITB inst accesses -system.cpu1.itb.hits 109086545 # DTB hits -system.cpu1.itb.misses 20082 # DTB misses -system.cpu1.itb.accesses 109106627 # DTB accesses -system.cpu1.numCycles 1184099170 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 109191224 # ITB inst accesses +system.cpu1.itb.hits 109170509 # DTB hits +system.cpu1.itb.misses 20715 # DTB misses +system.cpu1.itb.accesses 109191224 # DTB accesses +system.cpu1.numCycles 1180099422 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 109009230 # Number of instructions committed -system.cpu1.committedOps 127862448 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 117464588 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 115738 # Number of float alu accesses -system.cpu1.num_func_calls 6440342 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 16554986 # number of instructions that are conditional controls -system.cpu1.num_int_insts 117464588 # number of integer instructions -system.cpu1.num_fp_insts 115738 # number of float instructions -system.cpu1.num_int_register_reads 169322185 # number of times the integer registers were read -system.cpu1.num_int_register_writes 93148708 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 190671 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 89412 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 28259298 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 28158154 # number of times the CC registers were written -system.cpu1.num_mem_refs 38905190 # number of memory refs -system.cpu1.num_load_insts 20434165 # Number of load instructions -system.cpu1.num_store_insts 18471025 # Number of store instructions -system.cpu1.num_idle_cycles 1158563290.473996 # Number of idle cycles -system.cpu1.num_busy_cycles 25535879.526004 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021566 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978434 # Percentage of idle cycles -system.cpu1.Branches 24332682 # Number of branches fetched +system.cpu1.committedInsts 109095321 # Number of instructions committed +system.cpu1.committedOps 128047126 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 117680197 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 117915 # Number of float alu accesses +system.cpu1.num_func_calls 6450893 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16554916 # number of instructions that are conditional controls +system.cpu1.num_int_insts 117680197 # number of integer instructions +system.cpu1.num_fp_insts 117915 # number of float instructions +system.cpu1.num_int_register_reads 169047923 # number of times the integer registers were read +system.cpu1.num_int_register_writes 93200008 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 191658 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 96888 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 28194465 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 28098874 # number of times the CC registers were written +system.cpu1.num_mem_refs 39226015 # number of memory refs +system.cpu1.num_load_insts 20627300 # Number of load instructions +system.cpu1.num_store_insts 18598715 # Number of store instructions +system.cpu1.num_idle_cycles 1154150302.947621 # Number of idle cycles +system.cpu1.num_busy_cycles 25949119.052379 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021989 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978011 # Percentage of idle cycles +system.cpu1.Branches 24363890 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 88740475 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 271069 0.21% 69.57% # Class of executed instruction -system.cpu1.op_class::IntDiv 11362 0.01% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 11625 0.01% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::MemRead 20434165 15.97% 85.56% # Class of executed instruction -system.cpu1.op_class::MemWrite 18471025 14.44% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 88601672 69.15% 69.15% # Class of executed instruction +system.cpu1.op_class::IntMult 269277 0.21% 69.36% # Class of executed instruction +system.cpu1.op_class::IntDiv 11730 0.01% 69.37% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 13579 0.01% 69.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.38% # Class of executed instruction +system.cpu1.op_class::MemRead 20627300 16.10% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 18598715 14.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 127939763 # Class of executed instruction +system.cpu1.op_class::total 128122314 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 40521416 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28118087 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2031475 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 29676837 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 20868777 # Number of BTB hits +system.cpu2.branchPred.lookups 40464780 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28154198 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1978898 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 29418306 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 20974527 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 70.320085 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4994532 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 335745 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.297535 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4946229 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 331686 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1476,62 +1477,64 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 95252 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 95252 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7000 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29929 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 95252 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 95252 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 95252 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 36929 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 24871.388340 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 22228.503196 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 11289.834647 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-32767 23698 64.17% 64.17% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-65535 13086 35.44% 99.61% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-98303 84 0.23% 99.83% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::98304-131071 38 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-163839 4 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::163840-196607 9 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 36929 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 93767 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 93767 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6983 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29518 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 93767 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 93767 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 93767 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 36501 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 24922.262404 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 22135.996220 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 12304.178118 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-32767 23409 64.13% 64.13% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12906 35.36% 99.49% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-98303 87 0.24% 99.73% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::98304-131071 74 0.20% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::163840-196607 7 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-294911 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 36501 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000228500 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000228500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000228500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 29929 81.04% 81.04% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 7000 18.96% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 36929 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 95252 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 29518 80.87% 80.87% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 6983 19.13% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 36501 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93767 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 95252 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36929 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93767 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36501 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36929 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 132181 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36501 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 130268 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 29009718 # DTB read hits -system.cpu2.dtb.read_misses 79511 # DTB read misses -system.cpu2.dtb.write_hits 25340544 # DTB write hits -system.cpu2.dtb.write_misses 15741 # DTB write misses -system.cpu2.dtb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 28765084 # DTB read hits +system.cpu2.dtb.read_misses 78268 # DTB read misses +system.cpu2.dtb.write_hits 25322239 # DTB write hits +system.cpu2.dtb.write_misses 15499 # DTB write misses +system.cpu2.dtb.flush_tlb 1180 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 6565 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 192 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22319 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 74 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2265 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 6709 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 189 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 22277 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 76 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 2199 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3693 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 29089229 # DTB read accesses -system.cpu2.dtb.write_accesses 25356285 # DTB write accesses +system.cpu2.dtb.perms_faults 3811 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28843352 # DTB read accesses +system.cpu2.dtb.write_accesses 25337738 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 54350262 # DTB hits -system.cpu2.dtb.misses 95252 # DTB misses -system.cpu2.dtb.accesses 54445514 # DTB accesses +system.cpu2.dtb.hits 54087323 # DTB hits +system.cpu2.dtb.misses 93767 # DTB misses +system.cpu2.dtb.accesses 54181090 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1561,87 +1564,85 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 27224 # Table walker walks requested -system.cpu2.itb.walker.walksLong 27224 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1814 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22841 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 27224 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 27224 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 27224 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 24655 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 27863.922125 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25521.619222 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 11746.072802 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 11779 47.78% 47.78% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 12711 51.56% 99.33% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 67 0.27% 99.60% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 84 0.34% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 1 0.00% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 5 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 27119 # Table walker walks requested +system.cpu2.itb.walker.walksLong 27119 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1817 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22640 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 27119 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 27119 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 27119 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 24457 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 28043.607147 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 25574.105463 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 12475.611214 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 11681 47.76% 47.76% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 12550 51.31% 99.08% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 85 0.35% 99.42% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 123 0.50% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 7 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 6 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::262144-294911 1 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 24655 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 24457 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000202500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000202500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000202500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 22841 92.64% 92.64% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1814 7.36% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 24655 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 22640 92.57% 92.57% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1817 7.43% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 24457 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27224 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27224 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27119 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27119 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24655 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24655 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 51879 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 69987684 # ITB inst hits -system.cpu2.itb.inst_misses 27224 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24457 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24457 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 51576 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70111472 # ITB inst hits +system.cpu2.itb.inst_misses 27119 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1180 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 6565 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 192 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 17001 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 6709 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 189 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 16886 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 55845 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 56888 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70014908 # ITB inst accesses -system.cpu2.itb.hits 69987684 # DTB hits -system.cpu2.itb.misses 27224 # DTB misses -system.cpu2.itb.accesses 70014908 # DTB accesses -system.cpu2.numCycles 6727315780 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70138591 # ITB inst accesses +system.cpu2.itb.hits 70111472 # DTB hits +system.cpu2.itb.misses 27119 # DTB misses +system.cpu2.itb.accesses 70138591 # DTB accesses +system.cpu2.numCycles 6662793368 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 148611673 # Number of instructions committed -system.cpu2.committedOps 174373358 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 14098587 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1631 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 95904949193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 45.267748 # CPI: cycles per instruction -system.cpu2.ipc 0.022091 # IPC: instructions per cycle +system.cpu2.committedInsts 148437005 # Number of instructions committed +system.cpu2.committedOps 174093973 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 14341019 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1575 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 95890004718 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 44.886337 # CPI: cycles per instruction +system.cpu2.ipc 0.022278 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 276122031 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 6451193749 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 75051711 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50745018 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3426540 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 51416576 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 36523401 # Number of BTB hits +system.cpu2.tickCycles 276177864 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 6386615504 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 74718826 # Number of BP lookups +system.cpu3.branchPred.condPredicted 50589890 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3325419 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 50396966 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 36328478 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 71.034293 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9845099 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 104872 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 72.084653 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9777895 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 104949 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1671,91 +1672,91 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 518940 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 518940 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8603 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 51054 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 322381 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 196559 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2153.353446 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 12453.010606 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-65535 195431 99.43% 99.43% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-131071 797 0.41% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-196607 204 0.10% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-262143 65 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-327679 34 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-393215 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-458751 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 196559 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 238895 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 21937.397183 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 18018.053356 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 15122.644026 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-32767 188060 78.72% 78.72% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-65535 46353 19.40% 98.12% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-98303 3667 1.53% 99.66% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::98304-131071 466 0.20% 99.85% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.88% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::163840-196607 89 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-229375 102 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::229376-262143 32 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-294911 22 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::294912-327679 17 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-360447 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 238895 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -25404728884 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 1.186676 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -25965813384 102.21% 102.21% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 315763500 -1.24% 100.97% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 105079500 -0.41% 100.55% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 65519000 -0.26% 100.29% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 25638000 -0.10% 100.19% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 14396000 -0.06% 100.14% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 12378500 -0.05% 100.09% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 18510000 -0.07% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 3399500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 261000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 34500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 99500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::48-51 5500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -25404728884 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 51054 85.58% 85.58% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8603 14.42% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 59657 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 518940 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walks 514773 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 514773 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8632 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50765 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 320483 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 194290 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2154.802100 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 11919.135471 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-32767 190271 97.93% 97.93% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-65535 2868 1.48% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-98303 495 0.25% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::98304-131071 352 0.18% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-163839 145 0.07% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::163840-196607 61 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-229375 39 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::229376-262143 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-294911 21 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::360448-393215 8 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-425983 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 194290 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 239173 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 21856.421921 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 17938.758794 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 15122.793116 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-65535 234615 98.09% 98.09% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-131071 4213 1.76% 99.86% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-196607 180 0.08% 99.93% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-262143 137 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-327679 10 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 239173 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -26483974220 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.370007 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -27038933220 102.10% 102.10% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 309842500 -1.17% 100.93% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 102710000 -0.39% 100.54% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 66075500 -0.25% 100.29% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 25941500 -0.10% 100.19% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 14268000 -0.05% 100.14% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 12970500 -0.05% 100.09% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 19273500 -0.07% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 3639000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 190500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 29000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::44-47 8000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::48-51 11000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -26483974220 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 50765 85.47% 85.47% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8632 14.53% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 59397 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 514773 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 518940 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59657 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 514773 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59397 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59657 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 578597 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59397 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 574170 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 58887686 # DTB read hits -system.cpu3.dtb.read_misses 354452 # DTB read misses -system.cpu3.dtb.write_hits 46401949 # DTB write hits -system.cpu3.dtb.write_misses 164488 # DTB write misses -system.cpu3.dtb.flush_tlb 1183 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 58948022 # DTB read hits +system.cpu3.dtb.read_misses 349619 # DTB read misses +system.cpu3.dtb.write_hits 46411302 # DTB write hits +system.cpu3.dtb.write_misses 165154 # DTB write misses +system.cpu3.dtb.flush_tlb 1180 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 11695 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 298 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 29305 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 75 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 5086 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 11984 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 297 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 29239 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 79 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 5206 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 31208 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 59242138 # DTB read accesses -system.cpu3.dtb.write_accesses 46566437 # DTB write accesses +system.cpu3.dtb.perms_faults 31663 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 59297641 # DTB read accesses +system.cpu3.dtb.write_accesses 46576456 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 105289635 # DTB hits -system.cpu3.dtb.misses 518940 # DTB misses -system.cpu3.dtb.accesses 105808575 # DTB accesses +system.cpu3.dtb.hits 105359324 # DTB hits +system.cpu3.dtb.misses 514773 # DTB misses +system.cpu3.dtb.accesses 105874097 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1785,380 +1786,384 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 61371 # Table walker walks requested -system.cpu3.itb.walker.walksLong 61371 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1880 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41824 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8320 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 53051 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1484.693974 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 7949.697617 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 52591 99.13% 99.13% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 303 0.57% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 95 0.18% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 39 0.07% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 10 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 53051 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 52024 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 27951.877979 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 24094.893737 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 16939.258391 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-65535 51107 98.24% 98.24% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-131071 782 1.50% 99.74% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walks 60795 # Table walker walks requested +system.cpu3.itb.walker.walksLong 60795 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1936 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41390 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8352 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 52443 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1489.417081 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 8610.325599 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 51982 99.12% 99.12% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 282 0.54% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 109 0.21% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 37 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 7 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 52443 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 51678 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 27642.962189 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 23739.857132 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 16715.530485 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-65535 50770 98.24% 98.24% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-131071 774 1.50% 99.74% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::131072-196607 83 0.16% 99.90% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-262143 28 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-393215 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 52024 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -25407358384 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 1.082792 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 2146509568 -8.45% -8.45% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -27591517452 108.60% 100.15% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 32946500 -0.13% 100.02% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 4144000 -0.02% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 483500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 75500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -25407358384 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 41824 95.70% 95.70% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 1880 4.30% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 43704 # Table walker page sizes translated +system.cpu3.itb.walker.walkCompletionTime::196608-262143 35 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-393215 9 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 51678 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -30778988516 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.762645 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.421863 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -7265808116 23.61% 23.61% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -23547141900 76.50% 100.11% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 29216500 -0.09% 100.02% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 4017500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 490000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 170000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::6 67500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -30778988516 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 41390 95.53% 95.53% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 1936 4.47% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 43326 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 61371 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 61371 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60795 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60795 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43704 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43704 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 105075 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 54222751 # ITB inst hits -system.cpu3.itb.inst_misses 61371 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43326 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43326 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 104121 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 53907663 # ITB inst hits +system.cpu3.itb.inst_misses 60795 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1183 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1180 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 11695 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 298 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 22112 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 11984 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 297 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 22179 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 119556 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 120136 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 54284122 # ITB inst accesses -system.cpu3.itb.hits 54222751 # DTB hits -system.cpu3.itb.misses 61371 # DTB misses -system.cpu3.itb.accesses 54284122 # DTB accesses -system.cpu3.numCycles 362116242 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 53968458 # ITB inst accesses +system.cpu3.itb.hits 53907663 # DTB hits +system.cpu3.itb.misses 60795 # DTB misses +system.cpu3.itb.accesses 53968458 # DTB accesses +system.cpu3.numCycles 361864421 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 140692068 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 333606704 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 75051711 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 46368500 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 200357205 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7729147 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1466432 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 5775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 2417 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 3039056 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 93220 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 3908 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 54085330 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2111003 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 24755 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 349524457 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.117326 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.359483 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 140139481 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 332397649 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 74718826 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 46106373 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 200741121 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7544543 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1439697 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 5770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 2171 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 3065576 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 88539 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 4142 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 53769751 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2045312 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 24414 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 349258578 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.114486 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.357052 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 267214314 76.45% 76.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 10401691 2.98% 79.43% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10376538 2.97% 82.40% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7732436 2.21% 84.61% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 15785532 4.52% 89.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5057577 1.45% 90.57% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5498876 1.57% 92.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4902371 1.40% 93.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 22555122 6.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 267245928 76.52% 76.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 10321823 2.96% 79.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10331128 2.96% 82.43% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7716473 2.21% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15764851 4.51% 89.15% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5041778 1.44% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5511234 1.58% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4828224 1.38% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 22497139 6.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 349524457 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.207259 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.921270 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 115102148 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 163151118 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 60941298 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7267408 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 3060603 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 11237446 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 815602 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 364546839 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2510722 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 3060603 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 119327697 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 12479500 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 131448496 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 63890938 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 19315280 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 355739076 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 49184 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1032074 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 774475 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 9071524 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2005 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 339501197 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 543916726 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 420235861 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 502563 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 283815673 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 55685519 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 8092119 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 6958081 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 40275448 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 57221877 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 48841814 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7500676 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 8056084 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 337690712 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8109511 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 336678168 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 492039 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 46643392 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 29867606 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 195066 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 349524457 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.963246 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.677033 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 349258578 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.206483 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.918570 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 114369930 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 164038042 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 60584469 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7298385 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2965812 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 11163267 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 817702 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 363461294 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2524053 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 2965812 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 118569176 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 12281642 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 132557510 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 63592874 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 19289346 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 354946625 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 42029 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1018488 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 787978 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 8985547 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 1997 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 338843996 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 543179256 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 419420785 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 479701 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 284856001 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 53987990 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 8148289 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 7010381 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 40518568 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 57083242 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 48761213 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7628593 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 8153720 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 337135094 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8186679 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 336664947 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 479828 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 45100588 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 28943367 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 197497 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 349258578 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.963942 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.678060 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 218668838 62.56% 62.56% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 53919118 15.43% 77.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24783168 7.09% 85.08% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 17648409 5.05% 90.13% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 13036700 3.73% 93.86% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9178789 2.63% 96.48% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6241479 1.79% 98.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3625780 1.04% 99.31% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2422176 0.69% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 218381855 62.53% 62.53% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 54040442 15.47% 78.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24694063 7.07% 85.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17645756 5.05% 90.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 13020798 3.73% 93.85% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9160873 2.62% 96.47% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6234653 1.79% 98.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3637468 1.04% 99.30% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2442670 0.70% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 349524457 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 349258578 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1699142 25.95% 25.95% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 17812 0.27% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1053 0.02% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.24% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2601719 39.74% 65.97% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2227949 34.03% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1713190 25.96% 25.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 16354 0.25% 26.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1162 0.02% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2637813 39.97% 66.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2231741 33.81% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 228602725 67.90% 67.90% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 820222 0.24% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 38384 0.01% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 5 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 43257 0.01% 68.17% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 228589817 67.90% 67.90% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 839294 0.25% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 38427 0.01% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 187 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 41560 0.01% 68.17% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.17% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.17% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 60130906 17.86% 86.03% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 47042657 13.97% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 60136646 17.86% 86.03% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 47019015 13.97% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 336678168 # Type of FU issued -system.cpu3.iq.rate 0.929752 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6547675 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.019448 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1029252740 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 392488113 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 324616709 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 667767 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 333618 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 297362 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 342868261 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 357570 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2662931 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 336664947 # Type of FU issued +system.cpu3.iq.rate 0.930362 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6600260 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019605 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1029031717 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 390494788 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 324869188 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 636843 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 315952 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 284328 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 342924564 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 340642 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2686629 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 9411324 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 12714 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 384094 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 5127738 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 9062852 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 11957 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 394369 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4946237 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2090075 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 3953629 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2102231 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 3983237 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 3060603 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8381523 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 3212246 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 345878827 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 1059491 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 57221877 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 48841814 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6807675 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 123383 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 3041851 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 384094 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1583894 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1359451 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2943345 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 332673161 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 58878878 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3493066 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 2965812 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8240311 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 3183987 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 345400316 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 1015101 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 57083242 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 48761213 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6857312 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 127001 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 3008020 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 394369 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1508943 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1318655 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2827598 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 332842425 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 58939894 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3314806 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 78604 # number of nop insts executed -system.cpu3.iew.exec_refs 105279838 # number of memory reference insts executed -system.cpu3.iew.exec_branches 61795726 # Number of branches executed -system.cpu3.iew.exec_stores 46400960 # Number of stores executed -system.cpu3.iew.exec_rate 0.918692 # Inst execution rate -system.cpu3.iew.wb_sent 325632326 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 324914071 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 160314385 # num instructions producing a value -system.cpu3.iew.wb_consumers 278113551 # num instructions consuming a value +system.cpu3.iew.exec_nop 78543 # number of nop insts executed +system.cpu3.iew.exec_refs 105350305 # number of memory reference insts executed +system.cpu3.iew.exec_branches 61793426 # Number of branches executed +system.cpu3.iew.exec_stores 46410411 # Number of stores executed +system.cpu3.iew.exec_rate 0.919799 # Inst execution rate +system.cpu3.iew.wb_sent 325835982 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 325153516 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 160610684 # num instructions producing a value +system.cpu3.iew.wb_consumers 278606679 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.897265 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.576435 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.898551 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.576478 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 46667653 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7914445 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2622372 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 341617018 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.875708 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.868271 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 45121096 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7989182 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2518769 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 341571330 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.878941 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.873545 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 232826047 68.15% 68.15% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 52669534 15.42% 83.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 19043564 5.57% 89.15% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8581535 2.51% 91.66% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6262304 1.83% 93.49% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3681580 1.08% 94.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3506851 1.03% 95.60% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2207487 0.65% 96.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 12838116 3.76% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 232593389 68.10% 68.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 52799684 15.46% 83.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 18973015 5.55% 89.11% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8542771 2.50% 91.61% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6283805 1.84% 93.45% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3713979 1.09% 94.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3487678 1.02% 95.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2200102 0.64% 96.20% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 12976907 3.80% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 341617018 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 254540187 # Number of instructions committed -system.cpu3.commit.committedOps 299156826 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 341571330 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 255441658 # Number of instructions committed +system.cpu3.commit.committedOps 300221180 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 91524628 # Number of memory references committed -system.cpu3.commit.loads 47810552 # Number of loads committed -system.cpu3.commit.membars 2044329 # Number of memory barriers committed -system.cpu3.commit.branches 56838517 # Number of branches committed -system.cpu3.commit.fp_insts 284474 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 274963169 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7559690 # Number of function calls committed. +system.cpu3.commit.refs 91835365 # Number of memory references committed +system.cpu3.commit.loads 48020389 # Number of loads committed +system.cpu3.commit.membars 2080926 # Number of memory barriers committed +system.cpu3.commit.branches 57030615 # Number of branches committed +system.cpu3.commit.fp_insts 272912 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 275960484 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7595427 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 206931641 69.17% 69.17% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 635252 0.21% 69.38% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 28375 0.01% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 36930 0.01% 69.41% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 207669074 69.17% 69.17% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 652533 0.22% 69.39% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 28496 0.01% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.40% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 35712 0.01% 69.41% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.41% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.41% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.41% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 47810552 15.98% 85.39% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 43714076 14.61% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 48020389 16.00% 85.41% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 43814976 14.59% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 299156826 # Class of committed instruction -system.cpu3.commit.bw_lim_events 12838116 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 672513030 # The number of ROB reads -system.cpu3.rob.rob_writes 699568614 # The number of ROB writes -system.cpu3.timesIdled 2366771 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 12591785 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98718850803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 254540187 # Number of Instructions Simulated -system.cpu3.committedOps 299156826 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.422629 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.422629 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.702924 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.702924 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 392099204 # number of integer regfile reads -system.cpu3.int_regfile_writes 232294349 # number of integer regfile writes -system.cpu3.fp_regfile_reads 578128 # number of floating regfile reads -system.cpu3.fp_regfile_writes 349384 # number of floating regfile writes -system.cpu3.cc_regfile_reads 70503993 # number of cc regfile reads -system.cpu3.cc_regfile_writes 71192448 # number of cc regfile writes -system.cpu3.misc_regfile_reads 655577760 # number of misc regfile reads -system.cpu3.misc_regfile_writes 7960975 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40269 # Transaction distribution -system.iobus.trans_dist::ReadResp 40269 # Transaction distribution +system.cpu3.commit.op_class_0::total 300221180 # Class of committed instruction +system.cpu3.commit.bw_lim_events 12976907 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 671801943 # The number of ROB reads +system.cpu3.rob.rob_writes 698382232 # The number of ROB writes +system.cpu3.timesIdled 2359266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 12605843 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98651627369 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 255441658 # Number of Instructions Simulated +system.cpu3.committedOps 300221180 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.416623 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.416623 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.705904 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.705904 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 392429814 # number of integer regfile reads +system.cpu3.int_regfile_writes 232475172 # number of integer regfile writes +system.cpu3.fp_regfile_reads 557185 # number of floating regfile reads +system.cpu3.fp_regfile_writes 341168 # number of floating regfile writes +system.cpu3.cc_regfile_reads 70618800 # number of cc regfile reads +system.cpu3.cc_regfile_writes 71286741 # number of cc regfile writes +system.cpu3.misc_regfile_reads 655702130 # number of misc regfile reads +system.cpu3.misc_regfile_writes 8023774 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40266 # Transaction distribution +system.iobus.trans_dist::ReadResp 40266 # Transaction distribution system.iobus.trans_dist::WriteReq 136539 # Transaction distribution system.iobus.trans_dist::WriteResp 136539 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) @@ -2177,11 +2182,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353610 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2198,12 +2203,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 14862000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13439000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2223,70 +2228,70 @@ system.iobus.reqLayer16.occupancy 4000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 10142000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 9713000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 45000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 18725000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 18683000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 244315631 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 237657786 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 45003000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 43053000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 69196000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 55076000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115462 # number of replacements -system.iocache.tags.tagsinuse 10.425339 # Cycle average of tags in use +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.421040 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115478 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13087689855509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544644 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.880695 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430043 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651584 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13087689445509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547391 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.873649 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221712 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429603 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651315 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039677 # Number of tag accesses -system.iocache.tags.data_accesses 1039677 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses -system.iocache.demand_misses::total 8856 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8816 # number of overall misses -system.iocache.overall_misses::total 8856 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 902834218 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 902834218 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 5365256413 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5365256413 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 902834218 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 902834218 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 902834218 # number of overall miss cycles -system.iocache.overall_miss_latency::total 902834218 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 399236664 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 399236664 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 5327578122 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5327578122 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 399236664 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 399236664 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 399236664 # number of overall miss cycles +system.iocache.overall_miss_latency::total 399236664 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2300,505 +2305,504 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 102408.600045 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 101980.596182 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 50300.536385 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 50300.536385 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 102408.600045 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 101946.049910 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 102408.600045 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 101946.049910 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 17834 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 45300.880971 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 45111.487458 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 49947.293576 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 49947.293576 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 45300.880971 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 45096.200610 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 45300.880971 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 45096.200610 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7536 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1976 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 866 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.025304 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.702079 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 4982 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 4982 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 45408 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 45408 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 4982 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 4982 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 4982 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 4982 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 653734218 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 653734218 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3094856413 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3094856413 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 653734218 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 653734218 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 653734218 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 653734218 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.565109 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.562747 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.425711 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.425711 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.565109 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.562556 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.565109 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.562556 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131219.232838 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 131219.232838 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68156.633479 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68156.633479 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 131219.232838 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131219.232838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 131219.232838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131219.232838 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::realview.ide 2210 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 2210 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 45088 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 45088 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 2210 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 2210 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 2210 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 2210 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 288736664 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 288736664 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3073178122 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3073178122 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 288736664 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 288736664 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 288736664 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 288736664 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.250766 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.249718 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.422711 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.422711 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.250766 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.249633 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.250766 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.249633 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130650.074208 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130650.074208 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68159.557355 # average WriteLineReq mshr miss latency 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occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 62.862423 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 734.403230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2295.121948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 38.166542 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 55.564036 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2274.574548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3138.217003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 98.389522 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 140.202266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1940.354614 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 3994.639050 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.558867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002939 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.050319 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.156730 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000677 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000959 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011206 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.035021 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 36497.090356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 128.195847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 207.365343 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3477.103411 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 10892.259737 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.622029 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 64.439339 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 663.388118 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2525.804190 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 38.130985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 52.876796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2102.725425 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2793.262675 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 102.733184 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 141.240216 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2056.053767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 3525.266147 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.556901 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001956 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003164 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.053056 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.166203 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000635 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000983 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.010122 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.038541 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000848 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.047885 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001501 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.002139 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.029607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.060953 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996920 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 305 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62557 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 569 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2827 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53917 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004654 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.954544 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 421629401 # Number of tag accesses -system.l2c.tags.data_accesses 421629401 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 162534 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 110569 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 55382 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 41930 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 157494 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 59360 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 299154 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 112124 # number of ReadReq hits -system.l2c.ReadReq_hits::total 998547 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7530303 # number of Writeback hits -system.l2c.Writeback_hits::total 7530303 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3865 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1247 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 1535 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 2775 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9422 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 634082 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 192446 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 277703 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 471607 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1575838 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 5493197 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 1685224 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 3887506 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 4647283 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15713210 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 2580953 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 758591 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 1060227 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 1868057 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6267828 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 284671 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 86494 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu2.data 126322 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu3.data 229482 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 726969 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 162534 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 110569 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 5493197 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3215035 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 55382 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 41930 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1685224 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 951037 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 157494 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 59360 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 3887506 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 1337930 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 299154 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 112124 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 4647283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 2339664 # number of demand (read+write) hits -system.l2c.demand_hits::total 24555423 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 162534 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 110569 # number of overall hits -system.l2c.overall_hits::cpu0.inst 5493197 # number of overall hits -system.l2c.overall_hits::cpu0.data 3215035 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 55382 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 41930 # number of overall hits -system.l2c.overall_hits::cpu1.inst 1685224 # number of overall hits -system.l2c.overall_hits::cpu1.data 951037 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 157494 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 59360 # number of overall hits -system.l2c.overall_hits::cpu2.inst 3887506 # number of overall hits -system.l2c.overall_hits::cpu2.data 1337930 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 299154 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 112124 # number of overall hits -system.l2c.overall_hits::cpu3.inst 4647283 # number of overall hits -system.l2c.overall_hits::cpu3.data 2339664 # number of overall hits -system.l2c.overall_hits::total 24555423 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1348 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1360 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 417 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 408 # number of ReadReq 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70907.030823 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71641.218289 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74916.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73233.029547 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71717.289305 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 78048.067393 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78945.168295 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75043.138442 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84436.554292 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 77318.672367 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163713.586098 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 156199.733005 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 161400.414938 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160733.722455 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168691.861472 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 157871.958153 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 169235.221950 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 165611.736609 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166088.599752 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 156993.254910 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 165175.910996 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 163064.272674 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.791095 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.783113 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.781538 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.466676 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.666667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.206348 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.194439 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.189681 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.114899 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005899 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006415 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.006164 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.004043 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.038630 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.036754 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.036299 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021713 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.165266 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.197599 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.218556 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.092213 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005601 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007238 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.077932 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003329 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.007353 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006415 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.075182 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008398 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.071533 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.017326 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005601 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007238 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.077932 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003329 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.007353 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006415 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.075182 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008398 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.071533 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.017326 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77417.632099 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20654.547501 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20753.964059 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20748.769685 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20729.583785 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 46000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 46000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70601.953858 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71311.158103 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88007.118763 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 79267.714322 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70749.631305 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73179.079364 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75314.839339 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73752.099458 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72693.790988 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73643.538987 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78775.181390 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76023.759050 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69397.608538 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78042.152984 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97872.175338 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 88033.309719 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70749.631305 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71395.870225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73179.079364 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 72173.499336 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75314.839339 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84398.481942 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 77400.768256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70749.631305 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71395.870225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73179.079364 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 72173.499336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75314.839339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84398.481942 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 77400.768256 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159200.689423 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157693.140013 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 161550.314465 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159477.213457 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163690.507152 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 159670.164560 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 169338.517016 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 164275.886677 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161333.848191 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158633.651010 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 165303.573368 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 161768.236176 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76739 # Transaction distribution -system.membus.trans_dist::ReadResp 460749 # Transaction distribution -system.membus.trans_dist::WriteReq 33648 # Transaction distribution -system.membus.trans_dist::WriteResp 33648 # Transaction distribution -system.membus.trans_dist::Writeback 1098433 # Transaction distribution -system.membus.trans_dist::CleanEvict 213962 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34949 # Transaction distribution +system.membus.trans_dist::ReadReq 76737 # Transaction distribution +system.membus.trans_dist::ReadResp 455193 # Transaction distribution +system.membus.trans_dist::WriteReq 33647 # Transaction distribution +system.membus.trans_dist::WriteResp 33647 # Transaction distribution +system.membus.trans_dist::Writeback 1091179 # Transaction distribution +system.membus.trans_dist::CleanEvict 208864 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34786 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 34951 # Transaction distribution -system.membus.trans_dist::ReadExReq 916210 # Transaction distribution -system.membus.trans_dist::ReadExResp 916210 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 384010 # Transaction distribution +system.membus.trans_dist::UpgradeResp 34788 # Transaction distribution +system.membus.trans_dist::ReadExReq 906494 # Transaction distribution +system.membus.trans_dist::ReadExResp 906494 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 378456 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 62 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3942227 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4071627 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 343658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4415285 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6756 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3898162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4027556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 345368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4372924 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13524 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146305120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 146474546 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7302336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 153776882 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1554 # Total snoops (count) -system.membus.snoop_fanout::samples 2866082 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144864864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 145034278 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7356288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7356288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 152390566 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 691 # Total snoops (count) +system.membus.snoop_fanout::samples 2837421 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2866082 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2837421 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2866082 # Request fanout histogram -system.membus.reqLayer0.occupancy 51617000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2837421 # Request fanout histogram +system.membus.reqLayer0.occupancy 49386500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1694500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1639500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3281296074 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3223716711 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3058096264 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3001422636 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 103726218 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 89214499 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3186,64 +3190,64 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 1507075 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23857599 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8015609 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 18152591 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43716 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43720 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1994458 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1994458 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15815989 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6539025 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1270619 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1225211 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47531663 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29482635 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 826355 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1753245 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 79593898 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1012390548 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1027984926 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2989368 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6204744 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2049569586 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 999459 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 53440188 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.040190 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.196406 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1500754 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23827950 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33647 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33647 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8025102 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 18108882 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43452 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43455 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1996830 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1996830 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15787707 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6541408 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1269700 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1224612 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47446864 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29502710 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 824705 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1741139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 79515418 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1010580372 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1029542098 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2979800 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6154816 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2049257086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 987636 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 53377948 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039876 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.195669 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 51292404 95.98% 95.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 2147784 4.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 51249425 96.01% 96.01% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 2128523 3.99% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 53440188 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 20656393480 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 53377948 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 20681814986 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 436500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15434172491 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15410337923 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7824329236 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7854888294 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 294252739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 293722728 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 716654510 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 713107905 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini index 5de46231b..11d96493e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -204,7 +204,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -587,7 +587,7 @@ opLat=3 pipelined=false [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -1261,7 +1261,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1296,7 +1296,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1711,9 +1711,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index b9292423f..b59b70a33 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.321386 # Number of seconds simulated -sim_ticks 51321386217000 # Number of ticks simulated -final_tick 51321386217000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.241896 # Number of seconds simulated +sim_ticks 51241895910000 # Number of ticks simulated +final_tick 51241895910000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134164 # Simulator instruction rate (inst/s) -host_op_rate 157647 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7630777532 # Simulator tick rate (ticks/s) -host_mem_usage 687808 # Number of bytes of host memory used -host_seconds 6725.58 # Real time elapsed on the host -sim_insts 902332774 # Number of instructions simulated -sim_ops 1060266688 # Number of ops (including micro ops) simulated +host_inst_rate 95627 # Simulator instruction rate (inst/s) +host_op_rate 112378 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5423934154 # Simulator tick rate (ticks/s) +host_mem_usage 730628 # Number of bytes of host memory used +host_seconds 9447.37 # Real time elapsed on the host +sim_insts 903425057 # Number of instructions simulated +sim_ops 1061671663 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 154240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 142464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4107136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 45245848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 165376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 158016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3334400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 43223216 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 435264 # Number of bytes read from this memory -system.physmem.bytes_read::total 96965960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4107136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3334400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7441536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 82289920 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 165376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 148160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3796224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 45159832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 160832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 148224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3625536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 44632368 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 406656 # Number of bytes read from this memory +system.physmem.bytes_read::total 98243208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3796224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3625536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7421760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83214784 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 82310500 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2226 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 64174 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 706974 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2584 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 52100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 675368 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6801 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1515106 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1285780 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 83235364 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2584 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2315 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 59316 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 705630 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2513 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2316 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 697386 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6354 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1535063 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1300231 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1288353 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 80028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 881618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 842207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1889387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 80028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 144999 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1603424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1603825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1603424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 80028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 882019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 842207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3493212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1515106 # Number of read requests accepted -system.physmem.writeReqs 1288353 # Number of write requests accepted -system.physmem.readBursts 1515106 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1288353 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 96901440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 65344 # Total number of bytes read from write queue -system.physmem.bytesWritten 82309952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 96965960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 82310500 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1021 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 144011 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 91435 # Per bank write bursts -system.physmem.perBankRdBursts::1 93225 # Per bank write bursts -system.physmem.perBankRdBursts::2 89718 # Per bank write bursts -system.physmem.perBankRdBursts::3 87919 # Per bank write bursts -system.physmem.perBankRdBursts::4 92611 # Per bank write bursts -system.physmem.perBankRdBursts::5 102433 # Per bank write bursts -system.physmem.perBankRdBursts::6 93232 # Per bank write bursts -system.physmem.perBankRdBursts::7 90056 # Per bank write bursts -system.physmem.perBankRdBursts::8 87362 # Per bank write bursts -system.physmem.perBankRdBursts::9 117909 # Per bank write bursts -system.physmem.perBankRdBursts::10 95229 # Per bank write bursts -system.physmem.perBankRdBursts::11 97284 # Per bank write bursts -system.physmem.perBankRdBursts::12 90073 # Per bank write bursts -system.physmem.perBankRdBursts::13 103730 # Per bank write bursts -system.physmem.perBankRdBursts::14 91691 # Per bank write bursts -system.physmem.perBankRdBursts::15 90178 # Per bank write bursts -system.physmem.perBankWrBursts::0 77827 # Per bank write bursts -system.physmem.perBankWrBursts::1 79309 # Per bank write bursts -system.physmem.perBankWrBursts::2 76608 # Per bank write bursts -system.physmem.perBankWrBursts::3 77829 # Per bank write bursts -system.physmem.perBankWrBursts::4 80050 # Per bank write bursts -system.physmem.perBankWrBursts::5 85847 # Per bank write bursts -system.physmem.perBankWrBursts::6 79718 # Per bank write bursts -system.physmem.perBankWrBursts::7 79449 # Per bank write bursts -system.physmem.perBankWrBursts::8 76360 # Per bank write bursts -system.physmem.perBankWrBursts::9 83802 # Per bank write bursts -system.physmem.perBankWrBursts::10 81643 # Per bank write bursts -system.physmem.perBankWrBursts::11 83145 # Per bank write bursts -system.physmem.perBankWrBursts::12 78123 # Per bank write bursts -system.physmem.perBankWrBursts::13 87627 # Per bank write bursts -system.physmem.perBankWrBursts::14 79500 # Per bank write bursts -system.physmem.perBankWrBursts::15 79256 # Per bank write bursts +system.physmem.num_writes::total 1302804 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 881307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 871013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1917244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 144838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1623960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1624362 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1623960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 74084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 881708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 871013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3541605 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1535063 # Number of read requests accepted +system.physmem.writeReqs 1302804 # Number of write requests accepted +system.physmem.readBursts 1535063 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1302804 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 98199040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 44992 # Total number of bytes read from write queue +system.physmem.bytesWritten 83234496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 98243208 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 83235364 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 703 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 144188 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 94050 # Per bank write bursts +system.physmem.perBankRdBursts::1 94624 # Per bank write bursts +system.physmem.perBankRdBursts::2 91446 # Per bank write bursts +system.physmem.perBankRdBursts::3 92243 # Per bank write bursts +system.physmem.perBankRdBursts::4 98717 # Per bank write bursts +system.physmem.perBankRdBursts::5 106707 # Per bank write bursts +system.physmem.perBankRdBursts::6 93934 # Per bank write bursts +system.physmem.perBankRdBursts::7 93123 # Per bank write bursts +system.physmem.perBankRdBursts::8 90055 # Per bank write bursts +system.physmem.perBankRdBursts::9 118648 # Per bank write bursts +system.physmem.perBankRdBursts::10 94680 # Per bank write bursts +system.physmem.perBankRdBursts::11 96202 # Per bank write bursts +system.physmem.perBankRdBursts::12 91550 # Per bank write bursts +system.physmem.perBankRdBursts::13 95334 # Per bank write bursts +system.physmem.perBankRdBursts::14 93205 # Per bank write bursts +system.physmem.perBankRdBursts::15 89842 # Per bank write bursts +system.physmem.perBankWrBursts::0 79067 # Per bank write bursts +system.physmem.perBankWrBursts::1 80858 # Per bank write bursts +system.physmem.perBankWrBursts::2 78439 # Per bank write bursts +system.physmem.perBankWrBursts::3 80901 # Per bank write bursts +system.physmem.perBankWrBursts::4 84568 # Per bank write bursts +system.physmem.perBankWrBursts::5 88799 # Per bank write bursts +system.physmem.perBankWrBursts::6 79324 # Per bank write bursts +system.physmem.perBankWrBursts::7 81423 # Per bank write bursts +system.physmem.perBankWrBursts::8 78366 # Per bank write bursts +system.physmem.perBankWrBursts::9 84879 # Per bank write bursts +system.physmem.perBankWrBursts::10 80434 # Per bank write bursts +system.physmem.perBankWrBursts::11 83122 # Per bank write bursts +system.physmem.perBankWrBursts::12 79318 # Per bank write bursts +system.physmem.perBankWrBursts::13 82355 # Per bank write bursts +system.physmem.perBankWrBursts::14 80105 # Per bank write bursts +system.physmem.perBankWrBursts::15 78581 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 14 # Number of times write queue was full causing retry -system.physmem.totGap 51321385112000 # Total gap between requests +system.physmem.numWrRetry 26 # Number of times write queue was full causing retry +system.physmem.totGap 51241894805000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1515091 # Read request sizes (log2) +system.physmem.readPktSize::6 1535048 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1285780 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 688629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 426852 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 228074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 164413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1300231 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 696212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 434080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 231480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 166858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 804 # What read queue length does an incoming req see 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read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 738 # What 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write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 590002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.746442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.840046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.017877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 235290 39.88% 39.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 136180 23.08% 62.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56828 9.63% 72.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27605 4.68% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24232 4.11% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13797 2.34% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13359 2.26% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9785 1.66% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72926 12.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 590002 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 74241 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.393489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 234.888851 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 74237 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 14109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 29697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 65149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 77035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 77508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 81035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 83877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 86632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 85119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 84437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 96180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 104378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 81922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 85007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 77822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 599076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.854983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.463010 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.270126 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 239456 39.97% 39.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 137779 23.00% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 58288 9.73% 72.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28412 4.74% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23965 4.00% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14114 2.36% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13744 2.29% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10019 1.67% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 73299 12.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 599076 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 75110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.428012 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 233.528819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 75106 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::61440-63487 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 74241 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 74241 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.323218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.863934 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.335765 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 39 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 11 0.01% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 20 0.03% 0.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 65 0.09% 0.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 70112 94.44% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1316 1.77% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 568 0.77% 97.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 346 0.47% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 342 0.46% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 528 0.71% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 134 0.18% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.05% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 41 0.06% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 27 0.04% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 42 0.06% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 26 0.04% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 396 0.53% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 32 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 46 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 38 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 9 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 75110 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 75110 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.315124 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.869848 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.130210 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 32 0.04% 0.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 20 0.03% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 14 0.02% 0.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 62 0.08% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 70906 94.40% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1379 1.84% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 596 0.79% 97.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 313 0.42% 97.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 370 0.49% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 506 0.67% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 145 0.19% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 36 0.05% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 45 0.06% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 34 0.05% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 32 0.04% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 33 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 412 0.55% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 33 0.04% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 44 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 8 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 24 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 74241 # Writes before turning the bus around for reads -system.physmem.totQLat 44116098728 # Total ticks spent queuing -system.physmem.totMemAccLat 72505192478 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7570425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29137.13 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 27 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 75110 # Writes before turning the bus around for reads +system.physmem.totQLat 44722536913 # Total ticks spent queuing +system.physmem.totMemAccLat 73491786913 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7671800000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29147.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47887.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47897.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.13 # Average write queue length when enqueuing -system.physmem.readRowHits 1245847 # Number of row buffer hits during reads -system.physmem.writeRowHits 964327 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.66 # Average write queue length when enqueuing +system.physmem.readRowHits 1262545 # Number of row buffer hits during reads +system.physmem.writeRowHits 973277 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.98 # Row buffer hit rate for writes -system.physmem.avgGap 18306451.11 # Average gap between requests -system.physmem.pageHitRate 78.93 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2222337600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1212585000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5776859400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4125407760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352063391040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1232605432755 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29711598339000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34309604352555 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.524518 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49427675587817 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713733840000 # Time in different power states +system.physmem.writeRowHitRate 74.84 # Row buffer hit rate for writes +system.physmem.avgGap 18056482.14 # Average gap between requests +system.physmem.pageHitRate 78.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2313095400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1262105625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5965736400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4233895920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3346871502000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1235329874865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29661514581750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34257490791960 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.544567 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49344314821819 # Time in different power states +system.physmem_0.memoryStateTime::REF 1711079500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 179976420183 # Time in different power states +system.physmem_0.memoryStateTime::ACT 186501218681 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2238077520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1221173250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6032956800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4208474880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352063391040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1237235987925 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29707536448500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34310536509915 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.542681 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49420862619804 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713733840000 # Time in different power states +system.physmem_1.actEnergy 2215919160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1209082875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6002224800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4193596800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3346871502000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1231628029245 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29664761814750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34256882169630 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.532689 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49349717648088 # Time in different power states +system.physmem_1.memoryStateTime::REF 1711079500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 186788845196 # Time in different power states +system.physmem_1.memoryStateTime::ACT 181098330662 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -374,15 +368,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 132571032 # Number of BP lookups -system.cpu0.branchPred.condPredicted 90050105 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5878539 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 90490581 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 64975080 # Number of BTB hits +system.cpu0.branchPred.lookups 131237057 # Number of BP lookups +system.cpu0.branchPred.condPredicted 89167205 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5638568 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 88557097 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 64192129 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.803142 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17318147 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 190057 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.486713 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17175820 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 188370 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -413,94 +407,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 913008 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 913008 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16692 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 92976 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 560771 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 352237 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2376.777567 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 13703.858808 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-32767 344408 97.78% 97.78% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-65535 5384 1.53% 99.31% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-98303 983 0.28% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-131071 725 0.21% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-163839 276 0.08% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-196607 169 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-229375 94 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::229376-262143 47 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-294911 59 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::294912-327679 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-360447 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::360448-393215 25 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-425983 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::425984-458751 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-491519 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::491520-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 352237 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 421207 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22517.986406 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18384.767938 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16267.103719 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 412281 97.88% 97.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8071 1.92% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 392 0.09% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 363 0.09% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 22 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 421207 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 353008884868 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.117411 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.682149 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 352021835868 99.72% 99.72% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 541843500 0.15% 99.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 193463500 0.05% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 118741500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 46634500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 24285000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 23543000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 31748500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 6046000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 436000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 56500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 38500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 27500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::52-55 185000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 353008884868 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 92977 84.78% 84.78% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 16692 15.22% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 109669 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 913008 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 905525 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 905525 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16897 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 92924 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 558822 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 346703 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2425.430412 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 13757.880539 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 344211 99.28% 99.28% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1816 0.52% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 412 0.12% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 106 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 81 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 346703 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 421563 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22489.281555 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18275.838186 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16656.658640 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 412599 97.87% 97.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 7935 1.88% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 523 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 370 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 86 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 13 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 421563 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 359417936788 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.126321 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.679023 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 358421610788 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 547811500 0.15% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 199809500 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 118742000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 45429500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 23353000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 23408000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 31953500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 5493500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 315500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 10000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 359417936788 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 92925 84.61% 84.61% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 16897 15.39% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 109822 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 905525 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 913008 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 109669 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 905525 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 109822 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 109669 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1022677 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 109822 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1015347 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 104802286 # DTB read hits -system.cpu0.dtb.read_misses 628192 # DTB read misses -system.cpu0.dtb.write_hits 81730320 # DTB write hits -system.cpu0.dtb.write_misses 284816 # DTB write misses -system.cpu0.dtb.flush_tlb 1079 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 104324024 # DTB read hits +system.cpu0.dtb.read_misses 622142 # DTB read misses +system.cpu0.dtb.write_hits 81549080 # DTB write hits +system.cpu0.dtb.write_misses 283383 # DTB write misses +system.cpu0.dtb.flush_tlb 1078 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 22185 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 501 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 54383 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 188 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9307 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 22319 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 542 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56138 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 214 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9448 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56122 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 105430478 # DTB read accesses -system.cpu0.dtb.write_accesses 82015136 # DTB write accesses +system.cpu0.dtb.perms_faults 55690 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 104946166 # DTB read accesses +system.cpu0.dtb.write_accesses 81832463 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 186532606 # DTB hits -system.cpu0.dtb.misses 913008 # DTB misses -system.cpu0.dtb.accesses 187445614 # DTB accesses +system.cpu0.dtb.hits 185873104 # DTB hits +system.cpu0.dtb.misses 905525 # DTB misses +system.cpu0.dtb.accesses 186778629 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -530,831 +514,828 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 102934 # Table walker walks requested -system.cpu0.itb.walker.walksLong 102934 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2830 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69670 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14211 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 88723 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1670.198257 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 9993.098637 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 87793 98.95% 98.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 509 0.57% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 243 0.27% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 94 0.11% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 34 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 21 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 88723 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 86711 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 27827.271050 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23655.790569 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18399.370737 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 84751 97.74% 97.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1686 1.94% 99.68% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 179 0.21% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 53 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 86711 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 499035191932 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.085193 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -42443239012 -8.51% -8.51% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 541415505444 108.49% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 55393500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 6761000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 722500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 48000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 499035191932 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 69670 96.10% 96.10% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2830 3.90% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72500 # Table walker page sizes translated +system.cpu0.itb.walker.walks 104491 # Table walker walks requested +system.cpu0.itb.walker.walksLong 104491 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2977 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 70833 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14071 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 90420 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1597.942933 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9019.721733 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 89473 98.95% 98.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 526 0.58% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 276 0.31% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 90 0.10% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 22 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 16 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 90420 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 87881 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27928.608004 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23671.030961 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18442.594011 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 85773 97.60% 97.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1788 2.03% 99.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 210 0.24% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 67 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 26 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 87881 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 587048610976 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.928143 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.258729 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 42249088256 7.20% 7.20% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 544740674220 92.79% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 52941500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 5346000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 541000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 5000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 15000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 587048610976 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 70833 95.97% 95.97% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2977 4.03% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 73810 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102934 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102934 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 104491 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 104491 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72500 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72500 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 175434 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 95094277 # ITB inst hits -system.cpu0.itb.inst_misses 102934 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73810 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73810 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 178301 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 93910274 # ITB inst hits +system.cpu0.itb.inst_misses 104491 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1079 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1078 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 22185 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 501 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40091 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22319 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 542 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41605 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 207907 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 209342 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 95197211 # ITB inst accesses -system.cpu0.itb.hits 95094277 # DTB hits -system.cpu0.itb.misses 102934 # DTB misses -system.cpu0.itb.accesses 95197211 # DTB accesses -system.cpu0.numCycles 675702202 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94014765 # ITB inst accesses +system.cpu0.itb.hits 93910274 # DTB hits +system.cpu0.itb.misses 104491 # DTB misses +system.cpu0.itb.accesses 94014765 # DTB accesses +system.cpu0.numCycles 672837873 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 244757501 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 589419880 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 132571032 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 82293227 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 391738714 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13356245 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2509355 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 22606 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 4900 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5469917 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 167540 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 2725 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 94868898 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3621980 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 41300 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 651351111 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.059349 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.306953 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 242596168 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 583871358 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 131237057 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81367949 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 391672300 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 12912795 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2559887 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 21371 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 5907 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5496890 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 161597 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2291 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 93683695 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3482115 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 41656 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 648972539 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.054070 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.303352 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 505677761 77.64% 77.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18279909 2.81% 80.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18243298 2.80% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13516535 2.08% 85.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28852465 4.43% 89.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8999693 1.38% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9719421 1.49% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8528805 1.31% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39533224 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 504751488 77.78% 77.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18012631 2.78% 80.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 17993966 2.77% 83.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13374247 2.06% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28570124 4.40% 89.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8915108 1.37% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9700378 1.49% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8355653 1.29% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39298944 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 651351111 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.196197 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.872307 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 198764731 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 327769223 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105831567 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13682981 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5300378 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19660361 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1397395 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 643175990 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4312729 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5300378 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 206434504 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 26397501 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 257870314 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 111703786 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 43642083 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 627780362 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 81911 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1880696 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1582827 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 24120192 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3699 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 601307944 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 969598831 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 742471294 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 750947 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 504947564 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 96360375 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15500464 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13524428 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 76866665 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 101145902 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86060501 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13628383 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14576675 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 595266457 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15567772 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 595602490 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 860155 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 81220997 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 52302062 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 356361 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 651351111 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.914411 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.641831 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 648972539 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.195050 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.867774 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 196814484 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 328839067 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 104545498 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13685712 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5085585 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19454701 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1390261 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 638009836 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4286683 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5085585 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 204391005 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 27392255 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 259209600 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 110517948 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 42373779 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 623249202 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 71579 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1876177 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1615058 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 22749976 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3905 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 596805281 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 963507479 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 737465972 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 746816 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 504819765 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 91985511 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15562034 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13603964 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 76990444 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 100130044 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85693466 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13752433 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14485683 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 591325254 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15668453 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 593122197 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 836144 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 77301127 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 49722084 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 361977 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 648972539 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.913940 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.642087 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 416907124 64.01% 64.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 99553383 15.28% 79.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43434757 6.67% 85.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30928180 4.75% 90.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22872426 3.51% 94.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16003542 2.46% 96.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10950121 1.68% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6425711 0.99% 99.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4275867 0.66% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 415433099 64.01% 64.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 99398694 15.32% 79.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43154141 6.65% 85.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 30671240 4.73% 90.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22754813 3.51% 94.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 15949435 2.46% 96.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10913282 1.68% 98.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6427298 0.99% 99.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4270537 0.66% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 651351111 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 648972539 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2977313 25.58% 25.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 21726 0.19% 25.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2146 0.02% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4737742 40.71% 66.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3899084 33.50% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2981405 25.56% 25.56% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 22602 0.19% 25.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2507 0.02% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4779561 40.98% 66.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3875984 33.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 69 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 404218599 67.87% 67.87% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1425375 0.24% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 67506 0.01% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 50 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 58410 0.01% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 106977397 17.96% 86.09% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82855084 13.91% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 47 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 402622584 67.88% 67.88% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1399505 0.24% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 65721 0.01% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 48 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 5 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 57538 0.01% 68.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.14% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 106372763 17.93% 86.07% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82603986 13.93% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 595602490 # Type of FU issued -system.cpu0.iq.rate 0.881457 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11638012 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019540 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1854047614 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 692214073 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 573874162 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1006644 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 498985 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 447097 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 606702343 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 538090 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4757420 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 593122197 # Type of FU issued +system.cpu0.iq.rate 0.881523 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11662060 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019662 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1846708499 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 684493895 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 571889273 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1006638 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 498386 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 446935 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 604246281 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 537929 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4762645 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16585910 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 22662 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 668240 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 9092320 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 15679208 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 19927 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 708487 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8639603 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3863731 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7820378 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3917286 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7883426 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5300378 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15293530 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 9669423 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 610970772 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1799898 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 101145902 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86060501 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13228626 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 242900 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 9335617 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 668240 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2719159 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2323934 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5043093 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 588743474 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 104791307 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5960112 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5085585 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15009758 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 10941422 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 607129936 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1704783 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 100130044 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85693466 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13307217 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 240581 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10607814 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 708487 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2549086 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2233115 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4782201 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 586634430 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 104313037 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5594967 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 136543 # number of nop insts executed -system.cpu0.iew.exec_refs 186525171 # number of memory reference insts executed -system.cpu0.iew.exec_branches 109265890 # Number of branches executed -system.cpu0.iew.exec_stores 81733864 # Number of stores executed -system.cpu0.iew.exec_rate 0.871306 # Inst execution rate -system.cpu0.iew.wb_sent 575597633 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 574321259 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 283300170 # num instructions producing a value -system.cpu0.iew.wb_consumers 492230600 # num instructions consuming a value +system.cpu0.iew.exec_nop 136229 # number of nop insts executed +system.cpu0.iew.exec_refs 185865379 # number of memory reference insts executed +system.cpu0.iew.exec_branches 108795926 # Number of branches executed +system.cpu0.iew.exec_stores 81552342 # Number of stores executed +system.cpu0.iew.exec_rate 0.871881 # Inst execution rate +system.cpu0.iew.wb_sent 573547999 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 572336208 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 282398495 # num instructions producing a value +system.cpu0.iew.wb_consumers 490722197 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.849962 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575544 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.850630 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575475 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 81268346 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15211411 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4500525 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 637573218 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.830670 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.824266 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 77341674 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15306476 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4267486 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 635759269 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.833165 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.828636 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 442173264 69.35% 69.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 97173464 15.24% 84.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33154077 5.20% 89.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15182673 2.38% 92.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10793922 1.69% 93.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6469162 1.01% 94.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6019139 0.94% 95.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3912878 0.61% 96.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22694639 3.56% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 440698390 69.32% 69.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 96997007 15.26% 84.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 32966862 5.19% 89.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15106149 2.38% 92.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10791866 1.70% 93.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6453132 1.02% 94.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6019295 0.95% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3918041 0.62% 96.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22808527 3.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 637573218 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 450633299 # Number of instructions committed -system.cpu0.commit.committedOps 529613227 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 635759269 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 450546917 # Number of instructions committed +system.cpu0.commit.committedOps 529692575 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 161528172 # Number of memory references committed -system.cpu0.commit.loads 84559991 # Number of loads committed -system.cpu0.commit.membars 3687184 # Number of memory barriers committed -system.cpu0.commit.branches 100678778 # Number of branches committed -system.cpu0.commit.fp_insts 428537 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 486019598 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13276351 # Number of function calls committed. +system.cpu0.commit.refs 161504698 # Number of memory references committed +system.cpu0.commit.loads 84450835 # Number of loads committed +system.cpu0.commit.membars 3736231 # Number of memory barriers committed +system.cpu0.commit.branches 100681556 # Number of branches committed +system.cpu0.commit.fp_insts 429176 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 486199452 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13322938 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 366882155 69.27% 69.27% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1103700 0.21% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 50072 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 49128 0.01% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84559991 15.97% 85.47% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 76968181 14.53% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 366991615 69.28% 69.28% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1098704 0.21% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 48820 0.01% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 48738 0.01% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84450835 15.94% 85.45% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77053863 14.55% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 529613227 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22694639 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1221719500 # The number of ROB reads -system.cpu0.rob.rob_writes 1235563732 # The number of ROB writes -system.cpu0.timesIdled 4062222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24351091 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 46889510422 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 450633299 # Number of Instructions Simulated -system.cpu0.committedOps 529613227 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.499450 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.499450 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.666911 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.666911 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 694532138 # number of integer regfile reads -system.cpu0.int_regfile_writes 409756453 # number of integer regfile writes -system.cpu0.fp_regfile_reads 813886 # number of floating regfile reads -system.cpu0.fp_regfile_writes 470480 # number of floating regfile writes -system.cpu0.cc_regfile_reads 126655644 # number of cc regfile reads -system.cpu0.cc_regfile_writes 127915254 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1202729248 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15348526 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10661519 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.983500 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 305118964 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10662031 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.617340 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 529692575 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22808527 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1215947592 # The number of ROB reads +system.cpu0.rob.rob_writes 1227300023 # The number of ROB writes +system.cpu0.timesIdled 4042817 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 23865334 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 48376378387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 450546917 # Number of Instructions Simulated +system.cpu0.committedOps 529692575 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.493380 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.493380 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.669622 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.669622 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 692384326 # number of integer regfile reads +system.cpu0.int_regfile_writes 408324633 # number of integer regfile writes +system.cpu0.fp_regfile_reads 809160 # number of floating regfile reads +system.cpu0.fp_regfile_writes 477572 # number of floating regfile writes +system.cpu0.cc_regfile_reads 126161613 # number of cc regfile reads +system.cpu0.cc_regfile_writes 127342866 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1198291262 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15447790 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10676503 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.983474 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 304546323 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10677015 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.523545 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1659069500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 285.071495 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 226.912005 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.556780 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.443188 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 293.453166 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 218.530308 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.573151 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.426817 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1346452186 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1346452186 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80589927 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 80681589 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 161271516 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67520868 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67884168 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135405036 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204627 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 201539 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 406166 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 174874 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 149966 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 324840 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1793684 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1773233 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3566917 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2041252 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2056052 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4097304 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148110795 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 148565757 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 296676552 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148315422 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 148767296 # number of overall hits -system.cpu0.dcache.overall_hits::total 297082718 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6173656 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6486433 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12660089 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6585609 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6413253 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 12998862 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 647829 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 671589 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1319418 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 637368 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 603972 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1241340 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 307807 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 348230 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 656037 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1344556090 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1344556090 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79999086 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 80528903 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 160527989 # number of ReadReq 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overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43970285000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 44965591500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 88935876500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39469232389 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 38108394120 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 77577626509 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10196891500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11887921500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22084813000 # number of SoftPFReq MSHR miss cycles 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cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 188598316009 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3034885000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2806255000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5841140000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3049818991 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2643724500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5693543491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6084703991 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5449979500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11534683491 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032584 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033422 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033004 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014874 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014574 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749269 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.751518 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.750407 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.780312 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.796677 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.788190 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056876 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063358 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 259500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83577052752 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83973988225 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 167551040977 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 93806071252 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 96080752225 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 189886823477 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2986588500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2854625000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5841213500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2919463491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2774139500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5693602991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5906051991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5628764500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11534816491 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032825 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033450 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033139 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014914 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014630 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014772 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750542 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.752100 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751333 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.781736 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.793751 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787555 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059340 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060247 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059791 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024426 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024749 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024588 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028246 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028658 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028453 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15553.080512 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15434.659029 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15492.980887 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35808.721629 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35192.810538 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35503.497146 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15964.597108 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18117.108955 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17055.358370 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 52377.984613 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 52327.162289 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 52353.255990 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13724.036812 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13509.110117 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13610.273849 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 29437.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024539 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024774 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024657 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028382 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028713 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028548 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15516.323636 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15543.345785 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15530.033638 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35891.446660 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35534.057006 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35714.120698 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15972.608954 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18301.045751 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17155.716759 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 52537.056848 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 53450.703585 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 52983.009421 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13465.443706 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13699.155352 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13582.548196 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22071.428571 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 35000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30954.545455 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21235.022565 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20788.593778 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21009.926860 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20498.095883 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20411.801791 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20454.554586 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174458.783628 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172332.043724 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173430.522565 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161272.222040 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178799.168132 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168962.919281 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167590.381772 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175409.703894 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 171196.157309 # average overall mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25950 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21245.925751 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20985.732335 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21114.719316 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20507.636360 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20604.860338 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20556.715733 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174858.811475 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172006.808870 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173453.305024 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161180.560426 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178034.879990 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168974.714082 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167818.941011 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174925.865498 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 171213.378026 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 16142168 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.947517 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 172883065 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16142680 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.709688 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 16340342500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 273.082606 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 238.864911 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.533364 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.466533 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 16087139 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.947221 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 170921783 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16087651 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.624409 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 16333976500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 275.838488 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 236.108732 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.538747 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.461150 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999897 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 206401666 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 206401666 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 86191123 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 86691942 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 172883065 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 86191123 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 86691942 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 172883065 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 86191123 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 86691942 # number of overall hits -system.cpu0.icache.overall_hits::total 172883065 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8665288 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 8710490 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 17375778 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8665288 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 8710490 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 17375778 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8665288 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 8710490 # number of overall misses -system.cpu0.icache.overall_misses::total 17375778 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 113689396380 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 113502001896 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 227191398276 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 113689396380 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 113502001896 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 227191398276 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 113689396380 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 113502001896 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 227191398276 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 94856411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 95402432 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 190258843 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 94856411 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 95402432 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 190258843 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 94856411 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 95402432 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 190258843 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.091352 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091303 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.091327 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.091352 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.091303 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.091327 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.091352 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.091303 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.091327 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13120.094379 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13030.495632 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13075.178463 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13120.094379 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13030.495632 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13075.178463 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13120.094379 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13030.495632 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13075.178463 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 86637 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 204325556 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 204325556 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 85081339 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 85840444 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 170921783 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 85081339 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 85840444 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 170921783 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 85081339 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 85840444 # number of overall hits +system.cpu0.icache.overall_hits::total 170921783 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8589868 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 8726123 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 17315991 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8589868 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 8726123 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 17315991 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8589868 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 8726123 # number of overall misses +system.cpu0.icache.overall_misses::total 17315991 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 112329905402 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 114108527365 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 226438432767 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 112329905402 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 114108527365 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 226438432767 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 112329905402 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 114108527365 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 226438432767 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 93671207 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 94566567 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 188237774 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 93671207 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 94566567 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 188237774 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 93671207 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 94566567 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 188237774 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.091702 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.092275 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.091990 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.091702 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.092275 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.091990 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.091702 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.092275 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.091990 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13077.023466 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13076.658141 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13076.839366 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13077.023466 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13076.658141 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13076.839366 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13077.023466 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13076.658141 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13076.839366 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 85300 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 7314 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 7438 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.845365 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.468137 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 615328 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 617627 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 1232955 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 615328 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 617627 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 1232955 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 615328 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 617627 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 1232955 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8049960 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8092863 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 16142823 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8049960 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 8092863 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 16142823 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8049960 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 8092863 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 16142823 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 606680 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 621529 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1228209 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 606680 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 621529 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1228209 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 606680 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 621529 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1228209 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 7983188 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8104594 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16087782 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 7983188 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 8104594 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16087782 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 7983188 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 8104594 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16087782 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12465 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8175 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 20640 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12465 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8175 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 20640 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 100646775925 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 100551252932 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 201198028857 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 100646775925 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 100551252932 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 201198028857 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 100646775925 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 100551252932 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 201198028857 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99492670437 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 101031835906 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 200524506343 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99492670437 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 101031835906 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 200524506343 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99492670437 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 101031835906 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 200524506343 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 965827500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 632670500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1598498000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 965827500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 632670500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1598498000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084865 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084829 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084847 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084865 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084829 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084847 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084865 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084829 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084847 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12502.767209 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12424.682456 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12463.621069 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12502.767209 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12424.682456 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12463.621069 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12502.767209 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12424.682456 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12463.621069 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085226 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085703 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085465 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085226 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085703 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085465 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085226 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085703 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085465 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12462.774325 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12465.995941 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12464.397289 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12462.774325 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12465.995941 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12464.397289 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12462.774325 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12465.995941 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12464.397289 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 77446.608527 # average ReadReq mshr uncacheable latency @@ -1362,15 +1343,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 77446.608527 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 132830364 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90187101 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5886537 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91288458 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 64898028 # Number of BTB hits +system.cpu1.branchPred.lookups 132090219 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89757318 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5756723 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 89315962 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 64542834 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.091165 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17334778 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 185732 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.263493 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17132912 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 188342 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1400,96 +1381,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 905180 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 905180 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17142 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92306 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 553484 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 351696 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2321.493563 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13592.585679 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 349244 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1804 0.51% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 390 0.11% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 114 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 67 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 351696 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 414217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22492.792425 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18361.243775 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16253.124731 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 322417 77.84% 77.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 82857 20.00% 97.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 6808 1.64% 99.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1275 0.31% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 173 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 198 0.05% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 298 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 83 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 62 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 13 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 414217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 326963093592 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.083701 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.672512 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 325992368092 99.70% 99.70% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 539476500 0.16% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 187726500 0.06% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 115407500 0.04% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 46500000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 23809500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 21473500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 29946500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 5666000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 571000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 55000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 32500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 25000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::56-59 32000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 326963093592 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 92306 84.34% 84.34% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17142 15.66% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 109448 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 905180 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 899065 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 899065 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16912 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92517 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 553507 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 345558 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2400.667905 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13912.564680 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 343096 99.29% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1764 0.51% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 399 0.12% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 131 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 83 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 41 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 39 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 345558 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 421889 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22499.157361 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18375.438889 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16484.116423 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 412836 97.85% 97.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 8131 1.93% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 432 0.10% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 347 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 85 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 30 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 25 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 421889 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 324784285420 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.056472 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.661085 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 323808973920 99.70% 99.70% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 531761500 0.16% 99.86% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 194206000 0.06% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 116904000 0.04% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 46719500 0.01% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 26039000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 24606500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 29193500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 5603500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 253000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 17000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 324784285420 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 92517 84.55% 84.55% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 16912 15.45% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 109429 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 899065 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 905180 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 109448 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 899065 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 109429 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 109448 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1014628 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 109429 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1008494 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 105776812 # DTB read hits -system.cpu1.dtb.read_misses 627964 # DTB read misses -system.cpu1.dtb.write_hits 81868125 # DTB write hits -system.cpu1.dtb.write_misses 277216 # DTB write misses -system.cpu1.dtb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 105725858 # DTB read hits +system.cpu1.dtb.read_misses 617527 # DTB read misses +system.cpu1.dtb.write_hits 81869169 # DTB write hits +system.cpu1.dtb.write_misses 281538 # DTB write misses +system.cpu1.dtb.flush_tlb 1084 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21316 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 568 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55232 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 212 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8920 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 55091 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 175 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8923 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 54701 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 106404776 # DTB read accesses -system.cpu1.dtb.write_accesses 82145341 # DTB write accesses +system.cpu1.dtb.perms_faults 57008 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 106343385 # DTB read accesses +system.cpu1.dtb.write_accesses 82150707 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 187644937 # DTB hits -system.cpu1.dtb.misses 905180 # DTB misses -system.cpu1.dtb.accesses 188550117 # DTB accesses +system.cpu1.dtb.hits 187595027 # DTB hits +system.cpu1.dtb.misses 899065 # DTB misses +system.cpu1.dtb.accesses 188494092 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1519,217 +1491,223 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 106266 # Table walker walks requested -system.cpu1.itb.walker.walksLong 106266 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3111 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 73302 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14293 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 91973 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1630.543747 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 9941.577304 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 90961 98.90% 98.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 588 0.64% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 258 0.28% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 90 0.10% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 38 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::458752-491519 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 91973 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 90706 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28271.216899 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24128.368541 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18525.575548 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 88461 97.52% 97.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1926 2.12% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 212 0.23% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 62 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 21 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 90706 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 610372252128 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.878972 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.326581 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 73947141376 12.12% 12.12% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 536358552252 87.87% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 59179000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 6640000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 645500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 94000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 610372252128 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 73302 95.93% 95.93% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3111 4.07% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 76413 # Table walker page sizes translated +system.cpu1.itb.walker.walks 107064 # Table walker walks requested +system.cpu1.itb.walker.walksLong 107064 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3059 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 73056 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14602 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 92462 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1594.287383 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 9428.868117 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 91539 99.00% 99.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 493 0.53% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 272 0.29% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 87 0.09% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 28 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 16 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 92462 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 90717 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28181.123714 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24098.190167 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18325.203286 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 49691 54.78% 54.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 38968 42.96% 97.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 889 0.98% 98.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 845 0.93% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 113 0.12% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 103 0.11% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 30 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 24 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 11 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 18 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 90717 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 612488746252 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.881369 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.323767 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 72732513396 11.87% 11.87% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 539691898856 88.11% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 57837000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 5354000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 885500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 253500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 612488746252 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 73056 95.98% 95.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3059 4.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 76115 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 106266 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 106266 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 107064 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 107064 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 76413 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 76413 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 182679 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 95636263 # ITB inst hits -system.cpu1.itb.inst_misses 106266 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 76115 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 76115 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 183179 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 94801988 # ITB inst hits +system.cpu1.itb.inst_misses 107064 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1084 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21316 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 568 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 41371 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40979 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202868 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 204318 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 95742529 # ITB inst accesses -system.cpu1.itb.hits 95636263 # DTB hits -system.cpu1.itb.misses 106266 # DTB misses -system.cpu1.itb.accesses 95742529 # DTB accesses -system.cpu1.numCycles 670348620 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 94909052 # ITB inst accesses +system.cpu1.itb.hits 94801988 # DTB hits +system.cpu1.itb.misses 107064 # DTB misses +system.cpu1.itb.accesses 94909052 # DTB accesses +system.cpu1.numCycles 671476106 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 245802953 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 590871754 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 132830364 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 82232806 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 386445016 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13431293 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2639306 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 21635 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 4572 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5276880 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 167481 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 2239 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95410634 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3652057 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 41964 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 647075459 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.068807 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.316374 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 245366519 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 588017734 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 132090219 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 81675746 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 387641424 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13138102 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2647355 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 22361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 4505 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5327205 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 166052 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2673 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 94574767 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3547562 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 42774 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 647746875 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.062629 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.311059 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 501080801 77.44% 77.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18371493 2.84% 80.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18561867 2.87% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13401625 2.07% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28513625 4.41% 89.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 9105805 1.41% 91.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9777924 1.51% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8450851 1.31% 93.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39811468 6.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 502555880 77.59% 77.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18134910 2.80% 80.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18417584 2.84% 83.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13370411 2.06% 85.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28474947 4.40% 89.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9035668 1.39% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9746929 1.50% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8410613 1.30% 93.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 39599933 6.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 647075459 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.198151 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.881440 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 199983147 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 321798427 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 106352633 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13609650 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5329449 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19773591 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1406143 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 644884461 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4323616 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5329449 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 207655640 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 26665473 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 252746187 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 112130376 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 42545968 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 629384575 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 84102 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2156884 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1598140 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 23186474 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3948 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 602389573 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 968798649 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 744085505 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 803060 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 505488932 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 96900641 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15182115 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13209558 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 75938042 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 101507501 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 86179777 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13679637 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14662477 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 596915130 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15279603 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 597602438 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 863336 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 81541272 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52071117 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 356106 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 647075459 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.923544 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.649381 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 647746875 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.196716 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.875709 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 199564404 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 323792643 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 105578746 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13636228 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5172543 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19679879 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1416500 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 642218643 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4358994 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5172543 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 207175837 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 26230498 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 253904637 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 111453983 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 43806880 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 627356682 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 88872 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2222363 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1667701 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 24272659 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3825 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 600705753 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 967034808 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 741797210 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 803110 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 507019119 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 93686634 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15251472 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13261267 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 76352353 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 101066741 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 86034098 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13578571 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14575923 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 595450227 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15308226 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 597111513 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 840860 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 78779365 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 50277835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 362203 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 647746875 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.921828 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.648992 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 412751344 63.79% 63.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 98711881 15.26% 79.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43578879 6.73% 85.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31028755 4.80% 90.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23162473 3.58% 94.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16109238 2.49% 96.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10961200 1.69% 98.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6490260 1.00% 99.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4281429 0.66% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 413645402 63.86% 63.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 98786426 15.25% 79.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43350634 6.69% 85.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 30948406 4.78% 90.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23128317 3.57% 94.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16110243 2.49% 96.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11031117 1.70% 98.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6443224 0.99% 99.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4303106 0.66% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 647075459 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 647746875 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3038725 25.54% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 25345 0.21% 25.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 3128 0.03% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 3 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4885830 41.07% 66.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3943683 33.15% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3034292 25.34% 25.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 25435 0.21% 25.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2765 0.02% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 1 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4931574 41.19% 66.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3978849 33.23% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 46 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 405061818 67.78% 67.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1472658 0.25% 68.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 66179 0.01% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 56 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 52 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 404756244 67.79% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1480116 0.25% 68.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 67236 0.01% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 53 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued @@ -1742,111 +1720,111 @@ system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Ty system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 2 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 16 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 23 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 71237 0.01% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 107954973 18.06% 86.12% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82975408 13.88% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 71191 0.01% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 107813613 18.06% 86.11% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82922942 13.89% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 597602438 # Type of FU issued -system.cpu1.iq.rate 0.891480 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11896714 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019907 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1853948472 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 693931681 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 575193406 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1091913 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 542260 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 485773 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 608916098 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 583008 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4685337 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 597111513 # Type of FU issued +system.cpu1.iq.rate 0.889252 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11972916 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020051 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1853695544 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 689699314 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 575118751 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1088133 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 538121 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 485191 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 608503665 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 580712 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4698016 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16615869 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 21909 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 749717 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 9068365 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 15955461 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 21531 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 710912 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8765717 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3952894 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8300380 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3921205 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8400525 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5329449 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14829127 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 10212979 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 612328593 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1790117 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 101507501 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 86179777 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12919930 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 237071 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 9891044 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 749717 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2710919 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2329182 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5040101 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 590723670 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 105766513 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5987554 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5172543 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14653668 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 9919586 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 610892135 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1742457 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 101066741 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 86034098 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12972500 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 236911 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 9594506 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 710912 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2600980 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2287673 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4888653 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 590524927 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 105716307 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5700612 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 133860 # number of nop insts executed -system.cpu1.iew.exec_refs 187634979 # number of memory reference insts executed -system.cpu1.iew.exec_branches 109483047 # Number of branches executed -system.cpu1.iew.exec_stores 81868466 # Number of stores executed -system.cpu1.iew.exec_rate 0.881219 # Inst execution rate -system.cpu1.iew.wb_sent 576950915 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 575679179 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 284156915 # num instructions producing a value -system.cpu1.iew.wb_consumers 493402851 # num instructions consuming a value +system.cpu1.iew.exec_nop 133682 # number of nop insts executed +system.cpu1.iew.exec_refs 187585376 # number of memory reference insts executed +system.cpu1.iew.exec_branches 109412564 # Number of branches executed +system.cpu1.iew.exec_stores 81869069 # Number of stores executed +system.cpu1.iew.exec_rate 0.879443 # Inst execution rate +system.cpu1.iew.wb_sent 576824246 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 575603942 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 284399442 # num instructions producing a value +system.cpu1.iew.wb_consumers 494076723 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.858776 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575913 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.857222 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575618 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 81583045 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14923497 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4500070 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 633204147 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.838045 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.832186 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 78818099 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14946023 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4359945 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 634288153 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.838703 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.835068 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 438438352 69.24% 69.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 96042056 15.17% 84.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33088291 5.23% 89.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15382536 2.43% 92.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10958189 1.73% 93.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6612249 1.04% 94.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6082014 0.96% 95.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3902550 0.62% 96.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22697910 3.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 439406713 69.28% 69.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 96089140 15.15% 84.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33004326 5.20% 89.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15342101 2.42% 92.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10933751 1.72% 93.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6607641 1.04% 94.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6115019 0.96% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3924026 0.62% 96.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22865436 3.60% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 633204147 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 451699475 # Number of instructions committed -system.cpu1.commit.committedOps 530653461 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 634288153 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 452878140 # Number of instructions committed +system.cpu1.commit.committedOps 531979088 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 162003044 # Number of memory references committed -system.cpu1.commit.loads 84891632 # Number of loads committed -system.cpu1.commit.membars 3738235 # Number of memory barriers committed -system.cpu1.commit.branches 100868221 # Number of branches committed -system.cpu1.commit.fp_insts 465542 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 487126697 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13297594 # Number of function calls committed. +system.cpu1.commit.refs 162379661 # Number of memory references committed +system.cpu1.commit.loads 85111280 # Number of loads committed +system.cpu1.commit.membars 3699604 # Number of memory barriers committed +system.cpu1.commit.branches 101084293 # Number of branches committed +system.cpu1.commit.fp_insts 466365 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 488261253 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13274874 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 367411373 69.24% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1128741 0.21% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 49317 0.01% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 368350296 69.24% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1137362 0.21% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 50458 0.01% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.46% # Class of committed instruction @@ -1869,35 +1847,35 @@ system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.46% # system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 60944 0.01% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84891632 16.00% 85.47% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 77111412 14.53% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 61269 0.01% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 85111280 16.00% 85.48% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 77268381 14.52% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 530653461 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22697910 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1218827033 # The number of ROB reads -system.cpu1.rob.rob_writes 1238367651 # The number of ROB writes -system.cpu1.timesIdled 4095381 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 23273161 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 54406850213 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 451699475 # Number of Instructions Simulated -system.cpu1.committedOps 530653461 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.484059 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.484059 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.673828 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.673828 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 696515100 # number of integer regfile reads -system.cpu1.int_regfile_writes 411090108 # number of integer regfile writes -system.cpu1.fp_regfile_reads 864151 # number of floating regfile reads -system.cpu1.fp_regfile_writes 531144 # number of floating regfile writes -system.cpu1.cc_regfile_reads 126615327 # number of cc regfile reads -system.cpu1.cc_regfile_writes 127765048 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1196239956 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15044847 # number of misc regfile writes +system.cpu1.commit.op_class_0::total 531979088 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22865436 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1218285123 # The number of ROB reads +system.cpu1.rob.rob_writes 1235075441 # The number of ROB writes +system.cpu1.timesIdled 4119845 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 23729231 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 52762738169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 452878140 # Number of Instructions Simulated +system.cpu1.committedOps 531979088 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.482686 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.482686 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.674452 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.674452 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 696400049 # number of integer regfile reads +system.cpu1.int_regfile_writes 410875535 # number of integer regfile writes +system.cpu1.fp_regfile_reads 865968 # number of floating regfile reads +system.cpu1.fp_regfile_writes 525416 # number of floating regfile writes +system.cpu1.cc_regfile_reads 127021368 # number of cc regfile reads +system.cpu1.cc_regfile_writes 128126601 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1197743929 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15078416 # number of misc regfile writes system.iobus.trans_dist::ReadReq 40301 # Transaction distribution system.iobus.trans_dist::ReadResp 40301 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution @@ -1972,7 +1950,7 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569059287 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568866585 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) @@ -1982,17 +1960,17 @@ system.iobus.respLayer3.occupancy 147720000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115460 # number of replacements -system.iocache.tags.tagsinuse 10.424672 # Cycle average of tags in use +system.iocache.tags.replacements 115461 # number of replacements +system.iocache.tags.tagsinuse 10.416117 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13093329887000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544075 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.880598 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221505 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430037 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651542 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13093305735000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.549567 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.866551 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221848 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429159 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651007 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2012,18 +1990,18 @@ system.iocache.overall_misses::realview.ethernet 40 system.iocache.overall_misses::realview.ide 8816 # number of overall misses system.iocache.overall_misses::total 8856 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1614263059 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1619332059 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1629394165 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1634463165 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12613364228 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12613364228 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12612717420 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12612717420 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1614263059 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1619683059 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1629394165 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1634814165 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1614263059 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1619683059 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1629394165 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1634814165 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses) @@ -2051,28 +2029,28 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183106.063861 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182913.369366 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184822.387137 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184622.519485 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118253.245969 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118253.245969 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118247.181992 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118247.181992 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183106.063861 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182891.040989 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 184822.387137 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 184599.612127 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183106.063861 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182891.040989 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31017 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 184822.387137 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 184599.612127 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31652 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3459 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.967042 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.451179 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106629 # number of writebacks -system.iocache.writebacks::total 106629 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8816 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8853 # number of ReadReq MSHR misses @@ -2087,18 +2065,18 @@ system.iocache.overall_mshr_misses::realview.ethernet 40 system.iocache.overall_mshr_misses::realview.ide 8816 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8856 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1173463059 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1176682059 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188594165 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1191813165 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7280164228 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7280164228 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279517420 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7279517420 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1173463059 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1176883059 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1188594165 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1192014165 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1173463059 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1176883059 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1188594165 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1192014165 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2113,307 +2091,308 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133106.063861 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132913.369366 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134822.387137 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134622.519485 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68253.245969 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68253.245969 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68247.181992 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.181992 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 133106.063861 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 132891.040989 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 134822.387137 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 134599.612127 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133106.063861 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 132891.040989 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 134822.387137 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 134599.612127 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1395026 # number of replacements -system.l2c.tags.tagsinuse 65295.492166 # Cycle average of tags in use -system.l2c.tags.total_refs 50144400 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1458293 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 34.385682 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 15281090500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35597.818988 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 166.792374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 227.419292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3927.975659 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9604.860217 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 170.331373 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 255.084245 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3398.092398 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11947.117619 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.543180 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002545 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003470 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059936 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146559 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002599 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003892 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.051851 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.182299 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996330 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 361 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62906 # Occupied blocks per task id +system.l2c.tags.replacements 1414414 # number of replacements +system.l2c.tags.tagsinuse 65287.875921 # Cycle average of tags in use +system.l2c.tags.total_refs 50028752 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1477251 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 33.866115 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 15277469000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35504.413846 # Average occupied blocks per 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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78816.641204 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81822.005240 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80377.637051 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 91957.388739 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 97836.450379 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 94724.817679 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75283.656542 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86373.257469 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78375 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74567.025318 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87413.322610 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 85635.919878 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75283.656542 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86373.257469 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74567.025318 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87413.322610 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 85635.919878 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 90230.134002 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90394.673812 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 90311.050476 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75487.484775 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74598.515770 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75035.324452 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79308.892100 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81323.971199 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80383.585016 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 92550.482818 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 97569.105528 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 94962.533294 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75487.484775 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86489.395439 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74598.515770 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86939.539820 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 85513.057654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75487.484775 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86489.395439 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74598.515770 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86939.539820 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 85513.057654 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161958.783628 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162358.723653 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159832.013019 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 123319.072147 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149688.778806 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167298.356553 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157415.734220 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159506.658231 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 123330.363042 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149593.744824 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166534.109870 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157427.689568 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155567.782962 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155788.892678 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 163385.194722 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 136372.859732 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 162909.658773 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 136384.520105 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54320 # Transaction distribution -system.membus.trans_dist::ReadResp 484522 # Transaction distribution -system.membus.trans_dist::WriteReq 33697 # Transaction distribution -system.membus.trans_dist::WriteResp 33697 # Transaction distribution -system.membus.trans_dist::Writeback 1285780 # Transaction distribution -system.membus.trans_dist::CleanEvict 222453 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37353 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 37356 # Transaction distribution -system.membus.trans_dist::ReadExReq 1066998 # Transaction distribution -system.membus.trans_dist::ReadExResp 1066998 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 430202 # Transaction distribution +system.membus.trans_dist::ReadReq 54316 # Transaction distribution +system.membus.trans_dist::ReadResp 488581 # Transaction distribution +system.membus.trans_dist::WriteReq 33695 # Transaction distribution +system.membus.trans_dist::WriteResp 33695 # Transaction distribution +system.membus.trans_dist::Writeback 1300231 # Transaction distribution +system.membus.trans_dist::CleanEvict 226932 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37530 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 37532 # Transaction distribution +system.membus.trans_dist::ReadExReq 1083335 # Transaction distribution +system.membus.trans_dist::ReadExResp 1083335 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 434265 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4492142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4621788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4963983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6852 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4552687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4682321 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5023611 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172016940 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 172188714 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7259520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7259520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 179448234 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2724 # Total snoops (count) -system.membus.snoop_fanout::samples 3239737 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174247596 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 174419346 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7230976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7230976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 181650322 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3166 # Total snoops (count) +system.membus.snoop_fanout::samples 3279708 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3239737 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3279708 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3239737 # Request fanout histogram -system.membus.reqLayer0.occupancy 113920999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3279708 # Request fanout histogram +system.membus.reqLayer0.occupancy 114259000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5444004 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5427500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8690318133 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8793071023 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8114396828 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8222412889 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228917368 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228888550 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2754,67 +2733,67 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 2074158 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25494018 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 9446739 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 18863436 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46705 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46716 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2151304 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2151304 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16142823 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7285144 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1341111 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1234447 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48465856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32213596 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 910891 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2571300 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 84161643 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1034451264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1125904618 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3051976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8646848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2172054706 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2184416 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 57389162 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.063529 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.243911 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2064834 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25434780 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33695 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33695 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 9463502 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 18825810 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46769 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46779 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2161853 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2161853 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16087782 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7290273 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1340417 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1233753 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48300519 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32258677 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 920526 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2543246 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 84022968 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1030929280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1127055058 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3086240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8539792 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2169610370 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2203584 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 57319196 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.063782 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.244364 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 53743303 93.65% 93.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 3645859 6.35% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 53663256 93.62% 93.62% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 3655940 6.38% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 57389162 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 36059386455 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 57319196 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 36016999461 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1120500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1117500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24257498228 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24175146802 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14835156686 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14858261870 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 529789657 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 535144651 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1493165292 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1478603615 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16399 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 19287 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini index edfc7ccb5..10ca60c72 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -132,7 +132,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -208,7 +208,7 @@ sys=system port=system.toL2Bus.slave[3] [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -503,7 +503,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -538,7 +538,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -953,9 +953,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 8ea842e52..0c2ce6f33 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.832615 # Nu sim_ticks 51832614542500 # Number of ticks simulated final_tick 51832614542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 636228 # Simulator instruction rate (inst/s) -host_op_rate 747615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37416431352 # Simulator tick rate (ticks/s) -host_mem_usage 669888 # Number of bytes of host memory used -host_seconds 1385.29 # Real time elapsed on the host +host_inst_rate 536275 # Simulator instruction rate (inst/s) +host_op_rate 630162 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31538205227 # Simulator tick rate (ticks/s) +host_mem_usage 713092 # Number of bytes of host memory used +host_seconds 1643.49 # Real time elapsed on the host sim_insts 881360160 # Number of instructions simulated sim_ops 1035663034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -599,7 +599,7 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 518072849 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16267 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 19145 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 10037940 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.966034 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 305864730 # Total number of references to valid blocks. @@ -2119,13 +2119,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 4b49caa69..15805fa4d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -29,7 +29,7 @@ mem_ranges=0:134217727 memories=system.physmem mmap_using_noreserve=false num_work_ids=16 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -202,7 +202,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -252,7 +252,7 @@ system=system port=system.cpu.dtb_walker_cache.cpu_side [system.cpu.dtb_walker_cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -594,7 +594,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -660,7 +660,7 @@ system=system port=system.cpu.itb_walker_cache.cpu_side [system.cpu.itb_walker_cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -695,7 +695,7 @@ sequential_access=false size=1024 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1202,7 +1202,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 @@ -1586,7 +1586,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1609,7 +1609,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index ce7843f5c..264f4c629 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.154115 # Number of seconds simulated -sim_ticks 5154115247000 # Number of ticks simulated -final_tick 5154115247000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.126140 # Number of seconds simulated +sim_ticks 5126139641000 # Number of ticks simulated +final_tick 5126139641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128017 # Simulator instruction rate (inst/s) -host_op_rate 253040 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1617614851 # Simulator tick rate (ticks/s) -host_mem_usage 806232 # Number of bytes of host memory used -host_seconds 3186.24 # Real time elapsed on the host -sim_insts 407894468 # Number of instructions simulated -sim_ops 806246903 # Number of ops (including micro ops) simulated +host_inst_rate 128755 # Simulator instruction rate (inst/s) +host_op_rate 254500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618610313 # Simulator tick rate (ticks/s) +host_mem_usage 809248 # Number of bytes of host memory used +host_seconds 3167.00 # Real time elapsed on the host +sim_insts 407767906 # Number of instructions simulated +sim_ops 806002026 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 4480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10813376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1038720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10766272 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11893632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1047104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1047104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9584064 # Number of bytes written to this memory -system.physmem.bytes_written::total 9584064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 70 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168959 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11837632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1038720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1038720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9565696 # Number of bytes written to this memory +system.physmem.bytes_written::total 9565696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168223 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185838 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149751 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149751 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 203159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2098008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2307599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 203159 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 203159 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1859497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1859497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1859497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 203159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2098008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4167097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185838 # Number of read requests accepted -system.physmem.writeReqs 149751 # Number of write requests accepted -system.physmem.readBursts 185838 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149751 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11883456 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 9582144 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11893632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9584064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 184963 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149464 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149464 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 202632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2100269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2309268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 202632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 202632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1866062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1866062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1866062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 202632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2100269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4175331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 184963 # Number of read requests accepted +system.physmem.writeReqs 149464 # Number of write requests accepted +system.physmem.readBursts 184963 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149464 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11826048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue +system.physmem.bytesWritten 9564672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11837632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9565696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11738 # Per bank write bursts -system.physmem.perBankRdBursts::1 11323 # Per bank write bursts -system.physmem.perBankRdBursts::2 11916 # Per bank write bursts -system.physmem.perBankRdBursts::3 11912 # Per bank write bursts -system.physmem.perBankRdBursts::4 12271 # Per bank write bursts -system.physmem.perBankRdBursts::5 11705 # Per bank write bursts -system.physmem.perBankRdBursts::6 10605 # Per bank write bursts -system.physmem.perBankRdBursts::7 10992 # Per bank write bursts -system.physmem.perBankRdBursts::8 11596 # Per bank write bursts -system.physmem.perBankRdBursts::9 11415 # Per bank write bursts -system.physmem.perBankRdBursts::10 11752 # Per bank write bursts -system.physmem.perBankRdBursts::11 11610 # Per bank write bursts -system.physmem.perBankRdBursts::12 11474 # Per bank write bursts -system.physmem.perBankRdBursts::13 12022 # Per bank write bursts -system.physmem.perBankRdBursts::14 11655 # Per bank write bursts -system.physmem.perBankRdBursts::15 11693 # Per bank write bursts -system.physmem.perBankWrBursts::0 10141 # Per bank write bursts -system.physmem.perBankWrBursts::1 9357 # Per bank write bursts -system.physmem.perBankWrBursts::2 8826 # Per bank write bursts -system.physmem.perBankWrBursts::3 8882 # Per bank write bursts -system.physmem.perBankWrBursts::4 9347 # Per bank write bursts -system.physmem.perBankWrBursts::5 9205 # Per bank write bursts -system.physmem.perBankWrBursts::6 8767 # Per bank write bursts -system.physmem.perBankWrBursts::7 8936 # Per bank write bursts -system.physmem.perBankWrBursts::8 9149 # Per bank write bursts -system.physmem.perBankWrBursts::9 9192 # Per bank write bursts -system.physmem.perBankWrBursts::10 10057 # Per bank write bursts -system.physmem.perBankWrBursts::11 9346 # Per bank write bursts -system.physmem.perBankWrBursts::12 9689 # Per bank write bursts -system.physmem.perBankWrBursts::13 9578 # Per bank write bursts -system.physmem.perBankWrBursts::14 9663 # Per bank write bursts -system.physmem.perBankWrBursts::15 9586 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48781 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12059 # Per bank write bursts +system.physmem.perBankRdBursts::1 11374 # Per bank write bursts +system.physmem.perBankRdBursts::2 11651 # Per bank write bursts +system.physmem.perBankRdBursts::3 11200 # Per bank write bursts +system.physmem.perBankRdBursts::4 11713 # Per bank write bursts +system.physmem.perBankRdBursts::5 11071 # Per bank write bursts +system.physmem.perBankRdBursts::6 11625 # Per bank write bursts +system.physmem.perBankRdBursts::7 11816 # Per bank write bursts +system.physmem.perBankRdBursts::8 11540 # Per bank write bursts +system.physmem.perBankRdBursts::9 11598 # Per bank write bursts +system.physmem.perBankRdBursts::10 11427 # Per bank write bursts +system.physmem.perBankRdBursts::11 11449 # Per bank write bursts +system.physmem.perBankRdBursts::12 11382 # Per bank write bursts +system.physmem.perBankRdBursts::13 12463 # Per bank write bursts +system.physmem.perBankRdBursts::14 11321 # Per bank write bursts +system.physmem.perBankRdBursts::15 11093 # Per bank write bursts +system.physmem.perBankWrBursts::0 10213 # Per bank write bursts +system.physmem.perBankWrBursts::1 9339 # Per bank write bursts +system.physmem.perBankWrBursts::2 9470 # Per bank write bursts +system.physmem.perBankWrBursts::3 9072 # Per bank write bursts +system.physmem.perBankWrBursts::4 9457 # Per bank write bursts +system.physmem.perBankWrBursts::5 9178 # Per bank write bursts +system.physmem.perBankWrBursts::6 9173 # Per bank write bursts +system.physmem.perBankWrBursts::7 8997 # Per bank write bursts +system.physmem.perBankWrBursts::8 8928 # Per bank write bursts +system.physmem.perBankWrBursts::9 9204 # Per bank write bursts +system.physmem.perBankWrBursts::10 9473 # Per bank write bursts +system.physmem.perBankWrBursts::11 8827 # Per bank write bursts +system.physmem.perBankWrBursts::12 9527 # Per bank write bursts +system.physmem.perBankWrBursts::13 9857 # Per bank write bursts +system.physmem.perBankWrBursts::14 9294 # Per bank write bursts +system.physmem.perBankWrBursts::15 9439 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 5154115197500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 5126139591500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185838 # Read request sizes (log2) +system.physmem.readPktSize::6 184963 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149751 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 171307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149464 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,418 +156,418 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7827 # What write queue length does an incoming req see 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queue length does an incoming req see +system.physmem.wrQLenPdf::33 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 72428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.370685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.530831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.820481 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27904 38.53% 38.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17658 24.38% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7456 10.29% 73.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4108 5.67% 78.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2731 3.77% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1986 2.74% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1581 2.18% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1174 1.62% 89.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7830 10.81% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 72428 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7352 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.252992 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 561.335686 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7351 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 71880 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.588425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.048684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 320.988013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27629 38.44% 38.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17400 24.21% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7428 10.33% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4118 5.73% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2845 3.96% 82.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1999 2.78% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1307 1.82% 87.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1141 1.59% 88.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8013 11.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71880 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7347 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.150402 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 560.379075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7346 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7352 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7352 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.364663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.601623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.168660 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6294 85.61% 85.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 82 1.12% 86.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 194 2.64% 89.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 86 1.17% 90.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 99 1.35% 91.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 218 2.97% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 33 0.45% 95.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.15% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.20% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.08% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.04% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.04% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 253 3.44% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 7 0.10% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.20% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7347 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.341364 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.592949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.054942 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6299 85.74% 85.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 77 1.05% 86.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 192 2.61% 89.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 82 1.12% 90.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 130 1.77% 92.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 203 2.76% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 23 0.31% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.10% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 7 0.10% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.11% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.05% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.08% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 243 3.31% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.10% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.12% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 11 0.15% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 7 0.10% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.22% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7352 # Writes before turning the bus around for reads -system.physmem.totQLat 2003475850 # Total ticks spent queuing -system.physmem.totMemAccLat 5484957100 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 928395000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10790.00 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7347 # Writes before turning the bus around for reads +system.physmem.totQLat 1972823732 # Total ticks spent queuing +system.physmem.totMemAccLat 5437486232 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 923910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10676.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29540.00 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29426.49 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.16 # Average write queue length when enqueuing -system.physmem.readRowHits 152313 # Number of row buffer hits during reads -system.physmem.writeRowHits 110658 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.89 # Row buffer hit rate for writes -system.physmem.avgGap 15358415.20 # Average gap between requests -system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 270738720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 147724500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 721203600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 476027280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 336641292000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 130240416060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2978219081250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3446716483410 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.731853 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4954469478230 # Time in different power states -system.physmem_0.memoryStateTime::REF 172107000000 # Time in different power states +system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.70 # Average write queue length when enqueuing +system.physmem.readRowHits 152120 # Number of row buffer hits during reads +system.physmem.writeRowHits 110229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.75 # Row buffer hit rate for writes +system.physmem.avgGap 15328127.19 # Average gap between requests +system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 270149040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 147402750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 721570200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 485345520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129415070025 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2962157471250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3428011044705 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.732438 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4927750166228 # Time in different power states +system.physmem_0.memoryStateTime::REF 171172820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27531969270 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27209465022 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 276816960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 151041000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 727084800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 494164800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 336641292000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 130162900905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2978287085250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3446740385715 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.736489 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4954592740478 # Time in different power states -system.physmem_1.memoryStateTime::REF 172107000000 # Time in different power states +system.physmem_1.actEnergy 273263760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 149102250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 719721600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 483077520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129328302060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2962233583500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3428001086610 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.730496 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4927884080230 # Time in different power states +system.physmem_1.memoryStateTime::REF 171172820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27415396022 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27082630770 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86789700 # Number of BP lookups -system.cpu.branchPred.condPredicted 86789700 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 894071 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80040540 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78122239 # Number of BTB hits +system.cpu.branchPred.lookups 86515320 # Number of BP lookups +system.cpu.branchPred.condPredicted 86515320 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 846562 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79887008 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77941063 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.603338 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1558682 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180590 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.564128 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1538368 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179519 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449504376 # number of cpu cycles simulated +system.cpu.numCycles 448780162 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27485279 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 428718572 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86789700 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79680921 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 418030666 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1875632 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 150798 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 59488 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 208856 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 90 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 672 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9123295 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 449746 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4755 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 446873665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.892893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.051645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27109366 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427484272 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86515320 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79479431 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417767954 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1778202 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 144572 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 59542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 198505 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8932158 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 424030 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4890 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 446169387 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.890848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.050446 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281625965 63.02% 63.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2138685 0.48% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72155487 16.15% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1568927 0.35% 80.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2122343 0.47% 80.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2325830 0.52% 80.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1507660 0.34% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1867139 0.42% 81.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81561629 18.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281281763 63.04% 63.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2130107 0.48% 63.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72126905 16.17% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1545484 0.35% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2095217 0.47% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2290541 0.51% 81.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1479828 0.33% 81.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1850907 0.41% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81368635 18.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 446873665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193079 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.953758 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 22890187 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264923803 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150702566 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7419293 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 937816 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837865741 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 937816 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25728184 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 222903682 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12889746 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154594835 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29819402 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834359795 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 448369 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12212745 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 141423 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14773604 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 996662587 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1812180036 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114009606 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 309 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964181963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32480622 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 461875 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 465908 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 38538990 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17255328 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10136845 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1286418 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1053742 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828858399 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1188333 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823669123 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 243637 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23799824 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 35821203 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 147900 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 446873665 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.843181 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418517 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 446169387 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192779 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.952547 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23013230 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 265986736 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 147854773 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8425547 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 889101 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 835878661 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 889101 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 26336765 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 222825660 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12982234 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 152266315 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 30869312 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 832551989 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 449261 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12787861 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 146326 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14734321 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 994655089 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1807638707 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1111268111 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963888503 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30766581 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 460676 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 463553 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43190500 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17070475 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10019861 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1311535 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1113253 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827301854 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1181846 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 822527972 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 224018 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22481665 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33938360 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 142118 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 446169387 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843533 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.419200 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262902763 58.83% 58.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13828746 3.09% 61.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9781500 2.19% 64.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7055144 1.58% 65.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74339132 16.64% 82.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4387820 0.98% 83.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72808347 16.29% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1195469 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 574744 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262457891 58.82% 58.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13818111 3.10% 61.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9771246 2.19% 64.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7528828 1.69% 65.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 73243364 16.42% 82.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4832116 1.08% 83.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72756563 16.31% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1182673 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 578595 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 446873665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 446169387 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1974081 71.95% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 609151 22.20% 94.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160307 5.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2475977 76.35% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 605774 18.68% 95.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 161247 4.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 285084 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795424559 96.57% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 127671 0.02% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 84 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18333357 2.23% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9347919 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 283294 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 794512938 96.59% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150315 0.02% 96.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 126079 0.02% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 84 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18183253 2.21% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9272009 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823669123 # Type of FU issued -system.cpu.iq.rate 1.832394 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2743541 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2097198642 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 853858757 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819128971 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 446 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 432 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 155 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826127364 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 216 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1863869 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 822527972 # Type of FU issued +system.cpu.iq.rate 1.832808 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3242998 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003943 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2094691886 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 850977244 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818130626 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 165 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825487451 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1857982 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3260732 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15309 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14369 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1707925 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3083761 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14419 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13953 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1600409 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2207612 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 70919 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2207227 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 67958 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 937816 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 204799790 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10007204 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 830046732 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 155850 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17255344 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10136845 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 698572 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 395239 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8760495 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14369 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 514805 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 529588 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1044393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822053660 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17935902 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1483234 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 889101 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 204671978 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10002497 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 828483700 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 158761 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17070475 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10019861 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 692471 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 393140 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8758574 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13953 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 479614 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 507057 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 986671 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821011839 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17813350 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1389357 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27057833 # number of memory reference insts executed -system.cpu.iew.exec_branches 83242296 # Number of branches executed -system.cpu.iew.exec_stores 9121931 # Number of stores executed -system.cpu.iew.exec_rate 1.828800 # Inst execution rate -system.cpu.iew.wb_sent 821550761 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819129126 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640649566 # num instructions producing a value -system.cpu.iew.wb_consumers 1049893259 # num instructions consuming a value +system.cpu.iew.exec_refs 26873346 # number of memory reference insts executed +system.cpu.iew.exec_branches 83150160 # Number of branches executed +system.cpu.iew.exec_stores 9059996 # Number of stores executed +system.cpu.iew.exec_rate 1.829430 # Inst execution rate +system.cpu.iew.wb_sent 820539763 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818130791 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639922411 # num instructions producing a value +system.cpu.iew.wb_consumers 1048802840 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.822294 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610204 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823010 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610146 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23669936 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1040433 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 905908 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443311497 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818692 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.674309 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22357422 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1039727 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 857347 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 442798070 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.820247 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.674846 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272449194 61.46% 61.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11181690 2.52% 63.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3605884 0.81% 64.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74618286 16.83% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2464935 0.56% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1628465 0.37% 82.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 954634 0.22% 82.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70998554 16.02% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5409855 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272013186 61.43% 61.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11121974 2.51% 63.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3639430 0.82% 64.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74586618 16.84% 81.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2447768 0.55% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1626880 0.37% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1002961 0.23% 82.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70975924 16.03% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5383329 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443311497 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407894468 # Number of instructions committed -system.cpu.commit.committedOps 806246903 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 442798070 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407767906 # Number of instructions committed +system.cpu.commit.committedOps 806002026 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22423531 # Number of memory references committed -system.cpu.commit.loads 13994611 # Number of loads committed -system.cpu.commit.membars 468283 # Number of memory barriers committed -system.cpu.commit.branches 82184111 # Number of branches committed +system.cpu.commit.refs 22406164 # Number of memory references committed +system.cpu.commit.loads 13986712 # Number of loads committed +system.cpu.commit.membars 468149 # Number of memory barriers committed +system.cpu.commit.branches 82157432 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735078702 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156217 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171842 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783387641 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 145035 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121422 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 734850257 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155439 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171613 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783160302 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144896 0.02% 97.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121618 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -594,230 +594,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13992027 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8428920 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13984129 1.73% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8419452 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806246903 # Class of committed instruction -system.cpu.commit.bw_lim_events 5409855 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1267740043 # The number of ROB reads -system.cpu.rob.rob_writes 1663415417 # The number of ROB writes -system.cpu.timesIdled 288487 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2630711 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9858723524 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407894468 # Number of Instructions Simulated -system.cpu.committedOps 806246903 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.102011 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.102011 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907432 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907432 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091775121 # number of integer regfile reads -system.cpu.int_regfile_writes 655663425 # number of integer regfile writes -system.cpu.fp_regfile_reads 155 # number of floating regfile reads -system.cpu.cc_regfile_reads 416039105 # number of cc regfile reads -system.cpu.cc_regfile_writes 321913343 # number of cc regfile writes -system.cpu.misc_regfile_reads 265322894 # number of misc regfile reads -system.cpu.misc_regfile_writes 400562 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1662098 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.990156 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19068760 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1662610 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.469172 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 806002026 # Class of committed instruction +system.cpu.commit.bw_lim_events 5383329 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1265696040 # The number of ROB reads +system.cpu.rob.rob_writes 1660107630 # The number of ROB writes +system.cpu.timesIdled 283975 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2610775 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9803496536 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407767906 # Number of Instructions Simulated +system.cpu.committedOps 806002026 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.100577 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.100577 # CPI: Total CPI of All Threads +system.cpu.ipc 0.908614 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.908614 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1090426394 # number of integer regfile reads +system.cpu.int_regfile_writes 654841654 # number of integer regfile writes +system.cpu.fp_regfile_reads 165 # number of floating regfile reads +system.cpu.cc_regfile_reads 415713185 # number of cc regfile reads +system.cpu.cc_regfile_writes 321659378 # number of cc regfile writes +system.cpu.misc_regfile_reads 264880270 # number of misc regfile reads +system.cpu.misc_regfile_writes 399890 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1655948 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995019 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18959511 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1656460 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.445801 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.990156 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999981 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999981 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995019 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 204 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88153475 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88153475 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10917190 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10917190 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8084600 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8084600 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 64210 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 64210 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19001790 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19001790 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19066000 # number of overall hits -system.cpu.dcache.overall_hits::total 19066000 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1815691 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1815691 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334621 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334621 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406397 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406397 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2150312 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2150312 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2556709 # number of overall misses -system.cpu.dcache.overall_misses::total 2556709 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27046737500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27046737500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13846171242 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13846171242 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40892908742 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40892908742 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40892908742 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40892908742 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12732881 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12732881 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8419221 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8419221 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 470607 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 470607 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21152102 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21152102 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21622709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21622709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142599 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.142599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039745 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039745 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863559 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.863559 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.101659 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.101659 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118242 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118242 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14896.112554 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14896.112554 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41378.667932 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41378.667932 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19017.197849 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19017.197849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15994.353969 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15994.353969 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 467851 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 84 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 51332 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87653092 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87653092 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10818266 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10818266 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8075018 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8075018 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63136 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63136 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 18893284 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18893284 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18956420 # number of overall hits +system.cpu.dcache.overall_hits::total 18956420 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1801440 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1801440 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334795 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334795 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406500 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406500 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2136235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2136235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2542735 # number of overall misses +system.cpu.dcache.overall_misses::total 2542735 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26875877500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26875877500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13801276738 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13801276738 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40677154238 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40677154238 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40677154238 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40677154238 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12619706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12619706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8409813 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8409813 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 469636 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 469636 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21029519 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21029519 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21499155 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21499155 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142748 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.142748 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039810 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039810 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865564 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.865564 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101583 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101583 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118271 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118271 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14919.107769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14919.107769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.067065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.067065 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19041.516611 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19041.516611 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15997.402104 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15997.402104 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 467524 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 52009 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.114217 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 84 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.989290 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1563047 # number of writebacks -system.cpu.dcache.writebacks::total 1563047 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 843909 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 843909 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44439 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44439 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 888348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 888348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 888348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 888348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971782 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 971782 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290182 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290182 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402906 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402906 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1261964 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1261964 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1664870 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1664870 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602920 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 602920 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13934 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 13934 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616854 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 616854 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13356525500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13356525500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12439701244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12439701244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6060856500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6060856500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25796226744 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25796226744 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31857083244 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31857083244 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97797423500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97797423500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2624129500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2624129500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100421553000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 100421553000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076321 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076321 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.856141 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.856141 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059661 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059661 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076996 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076996 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.363962 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.363962 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42868.617778 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42868.617778 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15042.854909 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15042.854909 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20441.333306 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20441.333306 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19134.877344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19134.877344 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.301831 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.301831 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188325.642314 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188325.642314 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162796.306744 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162796.306744 # average overall mshr uncacheable latency +system.cpu.dcache.writebacks::writebacks 1557810 # number of writebacks +system.cpu.dcache.writebacks::total 1557810 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 835579 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 835579 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44644 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 880223 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 880223 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 880223 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 880223 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 965861 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 965861 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290151 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290151 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403017 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403017 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1256012 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1256012 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1659029 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1659029 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13873 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13873 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616769 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 616769 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13275179500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13275179500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12396951239 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12396951239 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6045548500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6045548500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25672130739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25672130739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31717679239 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31717679239 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2614977500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2614977500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100408631000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100408631000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076536 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076536 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034501 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034501 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858148 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858148 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077167 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077167 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.399556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.399556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42725.860807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42725.860807 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15000.728257 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15000.728257 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20439.399257 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20439.399257 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19118.218692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19118.218692 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.505766 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.505766 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188494.017156 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188494.017156 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.791394 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.791394 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 73546 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.805379 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 113695 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 73561 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.545588 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5097093086500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.805379 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.925336 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.925336 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 71018 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.855051 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 110090 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 71033 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.549843 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 197734009500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.855051 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.990941 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.990941 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 451096 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 451096 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113711 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 113711 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113711 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 113711 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113711 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 113711 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74558 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 74558 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74558 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 74558 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74558 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 74558 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 932190000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 932190000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 932190000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 932190000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 932190000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 932190000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 188269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 188269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 188269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 188269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 188269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 188269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.396018 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.396018 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.396018 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.396018 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.396018 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.396018 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12502.883661 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12502.883661 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12502.883661 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12502.883661 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12502.883661 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12502.883661 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 436469 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 436469 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 110104 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 110104 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 110104 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 110104 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 110104 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 110104 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 72087 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 72087 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 72087 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 72087 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 72087 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 72087 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 888705500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 888705500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 888705500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 888705500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 888705500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 888705500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 182191 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 182191 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 182191 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 182191 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 182191 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 182191 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395667 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395667 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395667 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395667 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395667 # miss 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system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -826,180 +827,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 13222 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 13222 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74558 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74558 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74558 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 74558 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74558 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 74558 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 857632000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 857632000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 857632000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 857632000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 857632000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 857632000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.396018 # mshr miss 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11502.883661 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11502.883661 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 17880 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 17880 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 72087 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 72087 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 72087 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 72087 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 72087 # number of overall MSHR misses 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14809433489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14809433489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14809433489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9123291 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9123291 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9123291 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9123291 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9123291 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9123291 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116671 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.116671 # miss rate for ReadReq accesses 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14506630997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14506630997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8932155 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8932155 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8932155 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8932155 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8932155 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8932155 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116381 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116381 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116381 # miss rate for demand accesses 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-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13139309991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13139309991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13139309991 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13139309991 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108941 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108941 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108941 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108941 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108941 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108941 # mshr miss rate for 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(read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12880264497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12880264497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12880264497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108973 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108973 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108973 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13232.690750 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13232.690750 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 13951 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.067078 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 26495 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13966 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.897107 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104644726500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.067078 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.379192 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.379192 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 97508 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 97508 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26495 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26495 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 13962 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.017494 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 24005 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 13975 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.717710 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5100174829000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.017494 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376093 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376093 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 92555 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 92555 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24014 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 24014 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26497 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26497 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26497 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26497 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14838 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14838 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14838 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14838 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14838 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14838 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176788000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176788000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176788000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 176788000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176788000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 176788000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41333 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41333 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24016 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 24016 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24016 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 24016 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14841 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 14841 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14841 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 14841 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14841 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 14841 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 170100000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 170100000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 170100000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 170100000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 170100000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 170100000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38855 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38855 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41335 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41335 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41335 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41335 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358987 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358987 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358969 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.358969 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358969 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.358969 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11914.543739 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11914.543739 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11914.543739 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11914.543739 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11914.543739 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11914.543739 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38857 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38857 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38857 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38857 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381959 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381959 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381939 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.381939 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381939 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.381939 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11461.491813 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11461.491813 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11461.491813 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11461.491813 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1008,183 +1009,183 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1499 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1499 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14838 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14838 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14838 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14838 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14838 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 14838 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 161950000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 161950000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 161950000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 161950000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 161950000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 161950000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358987 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358987 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358969 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358969 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358969 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358969 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10914.543739 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10914.543739 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10914.543739 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10914.543739 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10914.543739 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10914.543739 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2319 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2319 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14841 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14841 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14841 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 14841 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14841 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 14841 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155259000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155259000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155259000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155259000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155259000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155259000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381959 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381959 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381939 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381939 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10461.491813 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112938 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64810.238427 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4946164 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176935 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.954695 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112328 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64826.279220 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4884469 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176125 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.732968 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50458.579366 # Average occupied blocks per requestor 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average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66992.784412 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66992.784412 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73054.275411 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73054.275411 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 75900 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76270.829257 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76284.779941 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73054.275411 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68946.255289 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69312.522469 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73054.275411 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68946.255289 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69312.522469 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.288562 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.288562 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176824.996412 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176824.996412 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150318.867998 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150318.867998 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.847651 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.847651 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463964 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463964 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026098 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024742 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068536 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068536 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21184.770437 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21184.770437 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66967.446512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66967.446512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73063.894023 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73063.894023 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 75500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75722.357587 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75739.090935 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73063.894023 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68815.046633 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73063.894023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68815.046633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.497472 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.497472 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176993.260290 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176993.260290 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.259287 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.259287 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 602920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3061153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1727529 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1124352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 288090 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288090 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 993903 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1464872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 602896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3032324 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13873 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13873 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1727482 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1093519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 973367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1456602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2979851 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6223737 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 32716 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 177236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9413540 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63603072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208211079 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 921280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5280832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278016263 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 218468 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6317764 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.033210 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179185 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917513 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6205490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31703 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168231 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9322937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62267648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207474745 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 922624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5343616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 276008633 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 220316 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6258702 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.033424 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179742 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6107951 96.68% 96.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 209813 3.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6049509 96.66% 96.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 209193 3.34% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6317764 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4638715490 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6258702 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4609709481 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 577500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1492354491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1461362367 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3105124685 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3096027096 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22263487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 22269484 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 111892387 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 108175907 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 222126 # Transaction distribution -system.iobus.trans_dist::ReadResp 222126 # Transaction distribution -system.iobus.trans_dist::WriteReq 57753 # Transaction distribution -system.iobus.trans_dist::WriteResp 57753 # Transaction distribution -system.iobus.trans_dist::MessageReq 1650 # Transaction distribution -system.iobus.trans_dist::MessageResp 1650 # Transaction distribution +system.iobus.trans_dist::ReadReq 222102 # Transaction distribution +system.iobus.trans_dist::ReadResp 222102 # Transaction distribution +system.iobus.trans_dist::WriteReq 57708 # Transaction distribution +system.iobus.trans_dist::WriteResp 57708 # Transaction distribution +system.iobus.trans_dist::MessageReq 1641 # Transaction distribution +system.iobus.trans_dist::MessageResp 1641 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -1383,15 +1384,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 464488 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 464350 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 563058 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3282 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3282 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 562902 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -1407,19 +1408,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 238530 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 238452 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3272994 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3272880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3911656 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1449,25 +1450,25 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 242643106 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 242679087 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 453455000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 453362000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 50182000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1641000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47580 # number of replacements -system.iocache.tags.tagsinuse 0.177808 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.091366 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4993210705000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177808 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.011113 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.011113 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4993241946000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091366 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005710 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005710 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1481,14 +1482,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 915 system.iocache.demand_misses::total 915 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 915 # number of overall misses system.iocache.overall_misses::total 915 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142818702 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 142818702 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5513453404 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5513453404 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 142818702 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 142818702 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 142818702 # number of overall miss cycles -system.iocache.overall_miss_latency::total 142818702 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143595677 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 143595677 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5513463410 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5513463410 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 143595677 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 143595677 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 143595677 # number of overall miss cycles +system.iocache.overall_miss_latency::total 143595677 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) @@ -1505,19 +1506,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156086.013115 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 156086.013115 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.560873 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118010.560873 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156086.013115 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 156086.013115 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156086.013115 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 156086.013115 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 218 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 156935.166120 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.775043 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118010.775043 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 156935.166120 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 156935.166120 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 18 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.111111 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1531,14 +1532,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 915 system.iocache.demand_mshr_misses::total 915 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 915 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 915 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97068702 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97068702 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3177453404 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3177453404 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97068702 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 97068702 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97068702 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 97068702 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 97845677 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3177463410 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3177463410 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 97845677 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 97845677 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1547,81 +1548,81 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106086.013115 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.560873 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.560873 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 106086.013115 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 106086.013115 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 106935.166120 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.775043 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.775043 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 602920 # Transaction distribution -system.membus.trans_dist::ReadResp 656038 # Transaction distribution -system.membus.trans_dist::WriteReq 13934 # Transaction distribution -system.membus.trans_dist::WriteResp 13934 # Transaction distribution -system.membus.trans_dist::Writeback 149751 # Transaction distribution -system.membus.trans_dist::CleanEvict 10203 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2209 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1791 # Transaction distribution -system.membus.trans_dist::ReadExReq 133869 # Transaction distribution -system.membus.trans_dist::ReadExResp 133868 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 53130 # Transaction distribution -system.membus.trans_dist::MessageReq 1650 # Transaction distribution -system.membus.trans_dist::MessageResp 1650 # Transaction distribution -system.membus.trans_dist::BadAddressError 12 # Transaction distribution +system.membus.trans_dist::ReadReq 602896 # Transaction distribution +system.membus.trans_dist::ReadResp 655806 # Transaction distribution +system.membus.trans_dist::WriteReq 13873 # Transaction distribution +system.membus.trans_dist::WriteResp 13873 # Transaction distribution +system.membus.trans_dist::Writeback 149464 # Transaction distribution +system.membus.trans_dist::CleanEvict 9883 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2535 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2080 # Transaction distribution +system.membus.trans_dist::ReadExReq 133195 # Transaction distribution +system.membus.trans_dist::ReadExResp 133194 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52918 # Transaction distribution +system.membus.trans_dist::MessageReq 1641 # Transaction distribution +system.membus.trans_dist::MessageResp 1641 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464488 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 488383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 24 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1722115 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1867232 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238530 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18462656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20239623 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3282 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3282 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464350 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 486631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720185 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1865287 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6564 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6564 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538373 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18388288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20165113 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23261263 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1586 # Total snoops (count) -system.membus.snoop_fanout::samples 1014957 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001626 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040287 # Request fanout histogram +system.membus.pkt_size::total 23186717 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1616 # Total snoops (count) +system.membus.snoop_fanout::samples 1013692 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001619 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040202 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1013307 99.84% 99.84% # Request fanout histogram -system.membus.snoop_fanout::2 1650 0.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 1012051 99.84% 99.84% # Request fanout histogram +system.membus.snoop_fanout::2 1641 0.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 1014957 # Request fanout histogram -system.membus.reqLayer0.occupancy 355040500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1013692 # Request fanout histogram +system.membus.reqLayer0.occupancy 354973500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 388549500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 388325000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3282000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1018755770 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1016908044 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1641000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2209187226 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2204699193 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 86115345 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 86072153 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index bea975397..d7ee3e6f6 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -29,7 +29,7 @@ mem_ranges=0:134217727 memories=system.physmem mmap_using_noreserve=false num_work_ids=16 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -134,7 +134,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -184,7 +184,7 @@ system=system port=system.toL2Bus.slave[3] [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -1220,7 +1220,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 @@ -1255,7 +1255,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1639,7 +1639,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1662,7 +1662,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json index 6fe40cc4f..6cc193075 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json @@ -2,7 +2,7 @@ "name": null, "sim_quantum": 0, "system": { - "kernel": "/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9", + "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9", "mmap_using_noreserve": false, "kernel_addr_check": true, "bridge": { @@ -111,7 +111,7 @@ "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, "response_latency": 20, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 4194304, "tags": { "name": "tags", @@ -145,11 +145,11 @@ "prefetch_on_access": false, "path": "system.l2c", "name": "l2c", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 8 }, - "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh", + "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", "intel_mp_table": { "oem_table_addr": 0, "name": "intel_mp_table", @@ -638,7 +638,7 @@ "clk_domain": "system.clk_domain", "write_buffers": 8, "response_latency": 50, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 1024, "tags": { "name": "tags", @@ -672,7 +672,7 @@ "prefetch_on_access": false, "path": "system.iocache", "name": "iocache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 8 }, @@ -1183,7 +1183,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks0.image.child", - "image_file": "/work/gem5/dist/disks/linux-x86.img", + "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks0.image", @@ -1211,7 +1211,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks1.image.child", - "image_file": "/work/gem5/dist/disks/linux-bigswap2.img", + "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks1.image", @@ -1797,7 +1797,7 @@ "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, "response_latency": 2, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", @@ -1831,7 +1831,7 @@ "prefetch_on_access": false, "path": "system.cpu0.icache", "name": "icache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 1 }, @@ -1906,7 +1906,7 @@ "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, "response_latency": 2, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", @@ -1940,7 +1940,7 @@ "prefetch_on_access": false, "path": "system.cpu0.dcache", "name": "dcache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 4 }, diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 69801740a..fb8fdc7fa 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -4,6 +4,7 @@ warn: Sockets disabled, not accepting gdb connections warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -21,24 +22,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 6 -WARNING: Bank is already active! -Command: 0, Timestamp: 7107, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 12359, Bank: 3 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 10565, Bank: 5 -WARNING: Bank is already active! -Command: 0, Timestamp: 7170, Bank: 1 +Command: 0, Timestamp: 7191, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -52,7 +43,7 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7090, Bank: 1 +Command: 0, Timestamp: 6675, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -61,6 +52,20 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6767, Bank: 1 +WARNING: Bank is already active! +Command: 0, Timestamp: 6921, Bank: 6 +WARNING: Bank is already active! +Command: 0, Timestamp: 11289, Bank: 4 +WARNING: Bank is already active! +Command: 0, Timestamp: 7232, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 11338, Bank: 4 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -77,26 +82,24 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: Tried to clear PCI interrupt 14 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: Unknown mouse command 0xe1. WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: instruction 'wbinvd' unimplemented +warn: Tried to clear PCI interrupt 14 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: Unknown mouse command 0xe1. +warn: instruction 'wbinvd' unimplemented WARNING: Bank is already active! -Command: 0, Timestamp: 10421, Bank: 2 -WARNING: Bank is already active! -Command: 0, Timestamp: 9326, Bank: 7 +Command: 0, Timestamp: 7075, Bank: 7 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 0 +Command: 0, Timestamp: 6474, Bank: 4 WARNING: Bank is already active! -Command: 0, Timestamp: 6590, Bank: 6 +Command: 0, Timestamp: 6837, Bank: 6 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index ba1f8e728..494bbffd2 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,156 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.141168 # Number of seconds simulated -sim_ticks 5141168437500 # Number of ticks simulated -final_tick 5141168437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137726 # Number of seconds simulated +sim_ticks 5137726358500 # Number of ticks simulated +final_tick 5137726358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195369 # Simulator instruction rate (inst/s) -host_op_rate 388397 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4114294038 # Simulator tick rate (ticks/s) -host_mem_usage 1021404 # Number of bytes of host memory used -host_seconds 1249.59 # Real time elapsed on the host -sim_insts 244131065 # Number of instructions simulated -sim_ops 485336254 # Number of ops (including micro ops) simulated +host_inst_rate 193743 # Simulator instruction rate (inst/s) +host_op_rate 385165 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4079424438 # Simulator tick rate (ticks/s) +host_mem_usage 1056160 # Number of bytes of host memory used +host_seconds 1259.42 # Real time elapsed on the host +sim_insts 244004222 # Number of instructions simulated +sim_ops 485086710 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 377472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4958144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 201472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2034880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 383296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3456256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 380096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4972288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 215232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2058496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 369024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3382272 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11442624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 377472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 201472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 383296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9198208 # Number of bytes written to this memory -system.physmem.bytes_written::total 9198208 # Number of bytes written to this memory +system.physmem.bytes_read::total 11408192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 380096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 215232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 369024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9193728 # Number of bytes written to this memory +system.physmem.bytes_written::total 9193728 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 5898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 77471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3148 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 31795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 37 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 54004 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 5939 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 77692 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 32164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5766 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 52848 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143722 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143722 # Number of write requests responded to by this memory +system.physmem.num_reads::total 178253 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143652 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143652 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 73421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 964400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 39188 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 395801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 74554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 672271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2225685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 73421 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 39188 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 74554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1789128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1789128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1789128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 73981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 967799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 400663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 71826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 658321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2220475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 73981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 71826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 187700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1789455 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1789455 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1789455 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 73421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 964400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 39188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 395801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 74554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 672271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4014813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 95417 # Number of read requests accepted -system.physmem.writeReqs 81462 # Number of write requests accepted -system.physmem.readBursts 95417 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 81462 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6099840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 5213440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6106688 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5213568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 73981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 967799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 400663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 71826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 658321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4009929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 94617 # Number of read requests accepted +system.physmem.writeReqs 88760 # Number of write requests accepted +system.physmem.readBursts 94617 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 88760 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6047936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 5680640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6055488 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5680640 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 21330 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6364 # Per bank write bursts -system.physmem.perBankRdBursts::1 5596 # Per bank write bursts -system.physmem.perBankRdBursts::2 5691 # Per bank write bursts -system.physmem.perBankRdBursts::3 5690 # Per bank write bursts -system.physmem.perBankRdBursts::4 6222 # Per bank write bursts -system.physmem.perBankRdBursts::5 5617 # Per bank write bursts -system.physmem.perBankRdBursts::6 5512 # Per bank write bursts -system.physmem.perBankRdBursts::7 5018 # Per bank write bursts -system.physmem.perBankRdBursts::8 6455 # Per bank write bursts -system.physmem.perBankRdBursts::9 6386 # Per bank write bursts -system.physmem.perBankRdBursts::10 5929 # Per bank write bursts -system.physmem.perBankRdBursts::11 5798 # Per bank write bursts -system.physmem.perBankRdBursts::12 5744 # Per bank write bursts -system.physmem.perBankRdBursts::13 6558 # Per bank write bursts -system.physmem.perBankRdBursts::14 6049 # Per bank write bursts -system.physmem.perBankRdBursts::15 6681 # Per bank write bursts -system.physmem.perBankWrBursts::0 5937 # Per bank write bursts -system.physmem.perBankWrBursts::1 5551 # Per bank write bursts -system.physmem.perBankWrBursts::2 4927 # Per bank write bursts -system.physmem.perBankWrBursts::3 4762 # Per bank write bursts -system.physmem.perBankWrBursts::4 5737 # Per bank write bursts -system.physmem.perBankWrBursts::5 5264 # Per bank write bursts -system.physmem.perBankWrBursts::6 5028 # Per bank write bursts -system.physmem.perBankWrBursts::7 4496 # Per bank write bursts -system.physmem.perBankWrBursts::8 4483 # Per bank write bursts -system.physmem.perBankWrBursts::9 4823 # Per bank write bursts -system.physmem.perBankWrBursts::10 4660 # Per bank write bursts -system.physmem.perBankWrBursts::11 4592 # Per bank write bursts -system.physmem.perBankWrBursts::12 4759 # Per bank write bursts -system.physmem.perBankWrBursts::13 5475 # Per bank write bursts -system.physmem.perBankWrBursts::14 5045 # Per bank write bursts -system.physmem.perBankWrBursts::15 5921 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 28899 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6147 # Per bank write bursts +system.physmem.perBankRdBursts::1 5269 # Per bank write bursts +system.physmem.perBankRdBursts::2 5685 # Per bank write bursts +system.physmem.perBankRdBursts::3 5978 # Per bank write bursts +system.physmem.perBankRdBursts::4 5788 # Per bank write bursts +system.physmem.perBankRdBursts::5 5231 # Per bank write bursts +system.physmem.perBankRdBursts::6 5218 # Per bank write bursts +system.physmem.perBankRdBursts::7 5097 # Per bank write bursts +system.physmem.perBankRdBursts::8 6282 # Per bank write bursts +system.physmem.perBankRdBursts::9 6366 # Per bank write bursts +system.physmem.perBankRdBursts::10 6408 # Per bank write bursts +system.physmem.perBankRdBursts::11 6175 # Per bank write bursts +system.physmem.perBankRdBursts::12 5716 # Per bank write bursts +system.physmem.perBankRdBursts::13 6642 # Per bank write bursts +system.physmem.perBankRdBursts::14 6153 # Per bank write bursts +system.physmem.perBankRdBursts::15 6344 # Per bank write bursts +system.physmem.perBankWrBursts::0 6191 # Per bank write bursts +system.physmem.perBankWrBursts::1 5213 # Per bank write bursts +system.physmem.perBankWrBursts::2 6082 # Per bank write bursts +system.physmem.perBankWrBursts::3 5966 # Per bank write bursts +system.physmem.perBankWrBursts::4 5232 # Per bank write bursts +system.physmem.perBankWrBursts::5 5147 # Per bank write bursts +system.physmem.perBankWrBursts::6 4857 # Per bank write bursts +system.physmem.perBankWrBursts::7 4466 # Per bank write bursts +system.physmem.perBankWrBursts::8 5491 # Per bank write bursts +system.physmem.perBankWrBursts::9 5559 # Per bank write bursts +system.physmem.perBankWrBursts::10 5838 # Per bank write bursts +system.physmem.perBankWrBursts::11 5586 # Per bank write bursts +system.physmem.perBankWrBursts::12 5717 # Per bank write bursts +system.physmem.perBankWrBursts::13 5929 # Per bank write bursts +system.physmem.perBankWrBursts::14 5787 # Per bank write bursts +system.physmem.perBankWrBursts::15 5699 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 5140168291000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5136593386000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 95417 # Read request sizes (log2) +system.physmem.readPktSize::6 94617 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 81462 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 89319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 88760 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # 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Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 70 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 56 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 41433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 273.048440 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.990010 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 298.466349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16764 40.46% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10136 24.46% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4303 10.39% 75.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2529 6.10% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1659 4.00% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1139 2.75% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 786 1.90% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 657 1.59% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3460 8.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 41433 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4254 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.404325 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 181.210886 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4251 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1476 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 41697 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.270307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.374177 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.197981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16587 39.78% 39.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10275 24.64% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4266 10.23% 74.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2445 5.86% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1622 3.89% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1132 2.71% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 786 1.89% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 680 1.63% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3904 9.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41697 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4370 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.624485 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 178.940609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4367 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4254 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4254 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.149036 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.343940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.936401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 69 1.62% 1.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.16% 1.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 8 0.19% 2.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3652 85.85% 87.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 58 1.36% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 99 2.33% 91.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 64 1.50% 93.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 41 0.96% 94.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 93 2.19% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 12 0.28% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.19% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.26% 96.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.09% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.14% 97.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.05% 97.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 101 2.37% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.07% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.14% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4254 # Writes before turning the bus around for reads -system.physmem.totQLat 1082376548 # Total ticks spent queuing -system.physmem.totMemAccLat 2869439048 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 476550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11356.38 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4370 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4370 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.311213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.106663 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.785732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 51 1.17% 1.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 5 0.11% 1.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 8 0.18% 1.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3654 83.62% 85.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 60 1.37% 86.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 119 2.72% 89.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 59 1.35% 90.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 85 1.95% 92.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 116 2.65% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.30% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.11% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.21% 95.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.07% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.09% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 133 3.04% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.09% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.14% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.07% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.07% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.23% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4370 # Writes before turning the bus around for reads +system.physmem.totQLat 1101479246 # Total ticks spent queuing +system.physmem.totMemAccLat 2873335496 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 472495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11655.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30106.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30405.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.18 # Average write queue length when enqueuing -system.physmem.readRowHits 76603 # Number of row buffer hits during reads -system.physmem.writeRowHits 58733 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.10 # Row buffer hit rate for writes -system.physmem.avgGap 29060364.94 # Average gap between requests -system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 152447400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82937250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 356538000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 270228960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250406807040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 95253368040 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2241273741750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2587796068440 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.867367 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3687953773966 # Time in different power states -system.physmem_0.memoryStateTime::REF 128019840000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.15 # Average write queue length when enqueuing +system.physmem.readRowHits 75876 # Number of row buffer hits during reads +system.physmem.writeRowHits 65681 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes +system.physmem.avgGap 28011110.37 # Average gap between requests +system.physmem.pageHitRate 77.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153536040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 83535375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 346421400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 279618480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250238982240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94990329855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2239672524000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2585764947390 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.869445 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3685813216724 # Time in different power states +system.physmem_0.memoryStateTime::REF 127934040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18290517534 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17956780776 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 160786080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 87503625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 386872200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 257631840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250406807040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95642577720 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2237948975250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2584891153755 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.974840 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3687413088990 # Time in different power states -system.physmem_1.memoryStateTime::REF 128019840000 # Time in different power states +system.physmem_1.actEnergy 161655480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 87978000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 390663000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 295410240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250238982240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95244065640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2234394426750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2580813181350 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.044329 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3685435461238 # Time in different power states +system.physmem_1.memoryStateTime::REF 127934040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18838516010 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18309070012 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 818622179 # number of cpu cycles simulated +system.cpu0.numCycles 810473886 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70465386 # Number of instructions committed -system.cpu0.committedOps 143948929 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 131896754 # Number of integer alu accesses +system.cpu0.committedInsts 70312072 # Number of instructions committed +system.cpu0.committedOps 143658243 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 131612768 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 904463 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13997547 # number of instructions that are conditional controls -system.cpu0.num_int_insts 131896754 # number of integer instructions +system.cpu0.num_func_calls 897074 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13988759 # number of instructions that are conditional controls +system.cpu0.num_int_insts 131612768 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 241558700 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113520418 # number of times the integer registers were written +system.cpu0.num_int_register_reads 240911367 # number of times the integer registers were read +system.cpu0.num_int_register_writes 113282572 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82096977 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 54912679 # number of times the CC registers were written -system.cpu0.num_mem_refs 13231012 # number of memory refs -system.cpu0.num_load_insts 9870869 # Number of load instructions -system.cpu0.num_store_insts 3360143 # Number of store instructions -system.cpu0.num_idle_cycles 776995348.800534 # Number of idle cycles -system.cpu0.num_busy_cycles 41626830.199466 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050850 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949150 # Percentage of idle cycles -system.cpu0.Branches 15238298 # Number of branches fetched -system.cpu0.op_class::No_OpClass 84207 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 130532761 90.68% 90.74% # Class of executed instruction -system.cpu0.op_class::IntMult 57038 0.04% 90.78% # Class of executed instruction -system.cpu0.op_class::IntDiv 45915 0.03% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::MemRead 9869228 6.86% 97.67% # Class of executed instruction -system.cpu0.op_class::MemWrite 3360143 2.33% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82064957 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 54880945 # number of times the CC registers were written +system.cpu0.num_mem_refs 13139441 # number of memory refs +system.cpu0.num_load_insts 9809284 # Number of load instructions +system.cpu0.num_store_insts 3330157 # Number of store instructions +system.cpu0.num_idle_cycles 769348747.137634 # Number of idle cycles +system.cpu0.num_busy_cycles 41125138.862366 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050742 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949258 # Percentage of idle cycles +system.cpu0.Branches 15218344 # Number of branches fetched +system.cpu0.op_class::No_OpClass 83498 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 130336285 90.73% 90.78% # Class of executed instruction +system.cpu0.op_class::IntMult 55624 0.04% 90.82% # Class of executed instruction +system.cpu0.op_class::IntDiv 45353 0.03% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::MemRead 9807642 6.83% 97.68% # Class of executed instruction +system.cpu0.op_class::MemWrite 3330157 2.32% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143949292 # Class of executed instruction +system.cpu0.op_class::total 143658559 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1638295 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999362 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19673231 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1638807 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.004605 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1637472 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999430 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19610556 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1637984 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.972373 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 232.517984 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 254.861534 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 24.619844 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.454137 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.497776 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.048086 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 233.382237 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 253.425972 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 25.191221 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.455825 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.494973 # 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Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88575778 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4693238 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2575592 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4254114 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11522944 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3236162 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1812970 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3039112 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8088244 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19748 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10138 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30323 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 60209 # 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number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 297649 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1159923 # number of overall misses -system.cpu0.dcache.overall_misses::total 2062841 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2308605500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12073522500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14382128000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2733996493 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4762162878 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7496159371 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5042601993 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 16835685378 # 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8413667 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 163625 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 74092 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 228532 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466249 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8390792 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4622257 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 8254940 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21267989 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8554417 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4696349 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8483472 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21734238 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067712 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060544 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.162351 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.103574 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.035905 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036003 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.043192 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038678 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.879309 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.863170 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.867314 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.870865 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.054988 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050559 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116502 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.077901 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070755 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063379 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136727 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.094912 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13908.518842 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14643.021307 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10802.437775 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40378.031207 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34712.172010 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23035.124656 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21577.705954 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17505.916913 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13205.138922 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16941.437710 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14514.485339 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 10605.900974 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035170 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.033115 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.020363 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.863170 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.852384 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.554963 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050209 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065947 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.036509 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063034 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087132 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.047631 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12909.952150 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13489.646089 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13330.689592 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39030.706091 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38753.072065 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38860.256890 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14839.955280 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14474.596631 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14564.900232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20354.485766 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18370.866933 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18963.748409 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19163.136607 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17344.086440 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17864.262635 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164538.245286 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162011.647080 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163213.720165 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177659.963986 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200289.863734 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190256.220892 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164769.126780 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162777.138213 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163723.644922 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1547245 # number of writebacks +system.cpu0.dcache.writebacks::total 1547245 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 49 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 383157 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 383206 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1554 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32300 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 33854 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1603 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 415457 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 417060 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1603 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 415457 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 417060 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 163145 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 438935 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 602080 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 67710 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 103870 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 171580 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 65147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 193119 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 258266 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 230855 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 542805 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 773660 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 296002 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 735924 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1031926 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 186313 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 204652 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 390965 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3641 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3691 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 7332 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 189954 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 208343 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 398297 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2099080000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5941231000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8040311000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2625649990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3973863872 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6599513862 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 969909500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2805652000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3775561500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4724729990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9915094872 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14639824862 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5694639490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12720746872 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 18415386362 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30666876000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33145024000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63811900000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 650679500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 751025500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1401705000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31317555500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33896049500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65213605000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060310 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085775 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.047056 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036227 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032336 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.020407 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.868291 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.849390 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.553932 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050470 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065167 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.036489 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063668 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086004 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.047622 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12866.345889 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13535.559935 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13354.223691 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38777.876089 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38258.052104 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38463.188379 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14888.014797 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14528.099255 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14618.887116 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20466.223344 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18266.402984 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18922.814753 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19238.516936 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17285.408374 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17845.646260 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164598.691449 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161957.977445 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163216.400445 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178709.008514 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 203474.803576 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 191176.350245 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164869.155164 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162693.488622 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163731.097648 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 878679 # 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average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13114.883903 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13151.047561 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13233.353908 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13114.883903 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13151.047561 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25055 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 25055 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 25055 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 25055 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 25055 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 25055 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 174112 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 396176 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 570288 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 174112 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 396176 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 570288 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 174112 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 396176 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 570288 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2324463500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5197379983 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7521843483 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2324463500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5197379983 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7521843483 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2324463500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5197379983 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7521843483 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004416 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.109911 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004427 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004416 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.109911 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004427 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004416 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.109911 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004427 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13350.392276 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13118.866320 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13189.552442 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13350.392276 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13118.866320 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13189.552442 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13350.392276 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13118.866320 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13189.552442 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2607160707 # number of cpu cycles simulated +system.cpu1.numCycles 2606018119 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35907928 # Number of instructions committed -system.cpu1.committedOps 69695660 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64757843 # Number of integer alu accesses +system.cpu1.committedInsts 35722790 # Number of instructions committed +system.cpu1.committedOps 69377917 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64437935 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 501298 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6590213 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64757843 # number of integer instructions +system.cpu1.num_func_calls 498036 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6548156 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64437935 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119979371 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55719008 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119381439 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55453390 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36729292 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27266794 # number of times the CC registers were written -system.cpu1.num_mem_refs 4880817 # number of memory refs -system.cpu1.num_load_insts 2999293 # Number of load instructions -system.cpu1.num_store_insts 1881524 # Number of store instructions -system.cpu1.num_idle_cycles 2477690884.667310 # Number of idle cycles -system.cpu1.num_busy_cycles 129469822.332690 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049659 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950341 # Percentage of idle cycles -system.cpu1.Branches 7272679 # Number of branches fetched -system.cpu1.op_class::No_OpClass 37847 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64724112 92.87% 92.92% # Class of executed instruction -system.cpu1.op_class::IntMult 30276 0.04% 92.96% # Class of executed instruction -system.cpu1.op_class::IntDiv 24690 0.04% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::MemRead 2997578 4.30% 97.30% # Class of executed instruction -system.cpu1.op_class::MemWrite 1881524 2.70% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36402445 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27104510 # number of times the CC registers were written +system.cpu1.num_mem_refs 4834095 # number of memory refs +system.cpu1.num_load_insts 2964009 # Number of load instructions +system.cpu1.num_store_insts 1870086 # Number of store instructions +system.cpu1.num_idle_cycles 2478102522.985643 # Number of idle cycles +system.cpu1.num_busy_cycles 127915596.014357 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049085 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950915 # Percentage of idle cycles +system.cpu1.Branches 7225753 # Number of branches fetched +system.cpu1.op_class::No_OpClass 35671 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64456455 92.91% 92.96% # Class of executed instruction +system.cpu1.op_class::IntMult 31131 0.04% 93.00% # Class of executed instruction +system.cpu1.op_class::IntDiv 22623 0.03% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::MemRead 2962280 4.27% 97.30% # Class of executed instruction +system.cpu1.op_class::MemWrite 1870086 2.70% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69696027 # Class of executed instruction +system.cpu1.op_class::total 69378246 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29601973 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29601973 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 343203 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26791839 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26086008 # Number of BTB hits +system.cpu2.branchPred.lookups 29560975 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29560975 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 321330 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26625449 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 26036610 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.365500 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 612615 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 69103 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155854675 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.788435 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 603794 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 66654 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155113045 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 11239570 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 145909603 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29601973 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26698623 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 143043279 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 717621 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 104333 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 8734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9529 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 59780 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 573 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3640195 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 178301 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3755 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154823972 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.854554 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.033337 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 11047280 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145686023 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29560975 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26640404 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 142542790 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 677515 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 104928 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 5475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8867 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 68985 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 22 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3604542 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 166149 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3283 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154116964 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.860489 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.036370 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98922650 63.89% 63.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 904691 0.58% 64.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23796776 15.37% 79.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 606779 0.39% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 848220 0.55% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 866864 0.56% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 584872 0.38% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 770506 0.50% 82.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27522614 17.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98277439 63.77% 63.77% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 921613 0.60% 64.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23771065 15.42% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 603849 0.39% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 843324 0.55% 80.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 864608 0.56% 81.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 573617 0.37% 81.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 772001 0.50% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27489448 17.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154823972 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189933 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.936190 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10345115 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 94152716 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23674012 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5064791 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 359462 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 284127567 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 359462 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12498058 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76923279 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4647064 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 26307426 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12860875 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 282811276 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 202798 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5895071 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 49763 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4757971 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 337796416 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 617680837 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 379222279 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 178 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 324911571 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12884845 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 166150 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 167782 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24657180 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6871363 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3845087 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 401055 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 322271 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 280748481 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 429304 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278478009 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 108269 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 9486120 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 14384377 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 66849 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154823972 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.798675 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.397594 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154116964 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.190577 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.939225 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10113688 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 93745988 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 23732554 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5061206 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 339409 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283817902 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 339409 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12262766 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76655623 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4610961 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 26368994 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12755160 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 282570010 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 203292 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5910187 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 59652 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4622392 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 337562699 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 617313701 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 378956511 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 176 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 325317107 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12245592 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 169706 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 171154 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 24674635 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6903065 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3842483 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 404867 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 342392 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 280633357 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 431682 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 278499537 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 103065 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 9014489 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13791367 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 66778 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154116964 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.807066 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.400549 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 91620637 59.18% 59.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5352321 3.46% 62.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3836914 2.48% 65.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3858930 2.49% 67.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22596079 14.59% 82.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2789392 1.80% 84.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24067258 15.54% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 479282 0.31% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 223159 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 90926640 59.00% 59.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5330208 3.46% 62.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3853102 2.50% 64.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3864237 2.51% 67.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22585971 14.66% 82.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2780196 1.80% 83.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24046184 15.60% 99.53% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 494962 0.32% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 235464 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154823972 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154116964 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1768977 86.18% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 219653 10.70% 96.88% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 63974 3.12% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1774419 86.10% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 221659 10.76% 96.86% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 64684 3.14% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 83002 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 267565718 96.08% 96.11% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 58655 0.02% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 54123 0.02% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 92 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 7168633 2.57% 98.73% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3547786 1.27% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 87958 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 267524922 96.06% 96.09% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 58980 0.02% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 56493 0.02% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 63 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 7208859 2.59% 98.72% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3562262 1.28% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278478009 # Type of FU issued -system.cpu2.iq.rate 1.786780 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2052604 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007371 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713940607 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 290668150 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 276821518 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 256 # Number of floating instruction queue reads +system.cpu2.iq.FU_type_0::total 278499537 # Type of FU issued +system.cpu2.iq.rate 1.795462 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2060762 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007400 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 713279610 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 290083917 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 276907807 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 255 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280447483 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 128 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 731517 # Number of loads that had data forwarded from stores +system.cpu2.iq.fp_inst_queue_wakeup_accesses 101 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 280472218 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 745560 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1286395 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6167 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5109 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 663777 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1225052 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5875 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5188 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 625672 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 750358 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 29268 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 750058 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 26954 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 359462 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70735218 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 3134704 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 281177785 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 44449 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6871363 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3845087 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 251829 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 166997 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2638299 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5109 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 196795 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 202269 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 399064 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 277848009 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 7014778 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 573017 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 339409 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70544458 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 3078967 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 281065039 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 38553 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6903084 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3842483 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 256263 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 170697 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2578390 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5188 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 180466 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 193564 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 374030 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 277914745 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 7063605 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 530025 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10469775 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28224309 # Number of branches executed -system.cpu2.iew.exec_stores 3454997 # Number of stores executed -system.cpu2.iew.exec_rate 1.782738 # Inst execution rate -system.cpu2.iew.wb_sent 277647788 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 276821632 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 215782455 # num instructions producing a value -system.cpu2.iew.wb_consumers 353891684 # num instructions consuming a value +system.cpu2.iew.exec_refs 10537501 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28240197 # Number of branches executed +system.cpu2.iew.exec_stores 3473896 # Number of stores executed +system.cpu2.iew.exec_rate 1.791692 # Inst execution rate +system.cpu2.iew.wb_sent 277728046 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 276907908 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215869899 # num instructions producing a value +system.cpu2.iew.wb_consumers 354183211 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.776152 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609742 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.785201 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609487 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9482298 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 362455 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 346445 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 153408349 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.771036 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.652208 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9010167 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 364904 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 325088 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 152771285 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.780770 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.657176 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 95336110 62.15% 62.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4415580 2.88% 65.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1307869 0.85% 65.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24753928 16.14% 82.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 995070 0.65% 82.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 727248 0.47% 83.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 439603 0.29% 83.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23319103 15.20% 98.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2113838 1.38% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 94646882 61.95% 61.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4418156 2.89% 64.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1318603 0.86% 65.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24750822 16.20% 81.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 992364 0.65% 82.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 731797 0.48% 83.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 443039 0.29% 83.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23300929 15.25% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2168693 1.42% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 153408349 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137757751 # Number of instructions committed -system.cpu2.commit.committedOps 271691665 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 152771285 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137969360 # Number of instructions committed +system.cpu2.commit.committedOps 272050550 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8766278 # Number of memory references committed -system.cpu2.commit.loads 5584968 # Number of loads committed -system.cpu2.commit.membars 161958 # Number of memory barriers committed -system.cpu2.commit.branches 27804222 # Number of branches committed +system.cpu2.commit.refs 8894843 # Number of memory references committed +system.cpu2.commit.loads 5678032 # Number of loads committed +system.cpu2.commit.membars 160530 # Number of memory barriers committed +system.cpu2.commit.branches 27847068 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248326046 # Number of committed integer instructions. -system.cpu2.commit.function_calls 453891 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 49969 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 262767573 96.72% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 56460 0.02% 96.75% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 51419 0.02% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5584918 2.06% 98.83% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3181310 1.17% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 248702825 # Number of committed integer instructions. +system.cpu2.commit.function_calls 458806 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 52824 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 262991815 96.67% 96.69% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 56918 0.02% 96.71% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 54179 0.02% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5677987 2.09% 98.82% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3216811 1.18% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 271691665 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2113838 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 432438048 # The number of ROB reads -system.cpu2.rob.rob_writes 563770768 # The number of ROB writes -system.cpu2.timesIdled 121162 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1030703 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4911308393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137757751 # Number of Instructions Simulated -system.cpu2.committedOps 271691665 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.131368 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.131368 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.883886 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.883886 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 370162227 # number of integer regfile reads -system.cpu2.int_regfile_writes 221868711 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73082 # number of floating regfile reads +system.cpu2.commit.op_class_0::total 272050550 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2168693 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 431630642 # The number of ROB reads +system.cpu2.rob.rob_writes 563473683 # The number of ROB writes +system.cpu2.timesIdled 116646 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 996081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4908046353 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137969360 # Number of Instructions Simulated +system.cpu2.committedOps 272050550 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.124257 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.124257 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.889476 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.889476 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 370420908 # number of integer regfile reads +system.cpu2.int_regfile_writes 221942656 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73069 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 141178662 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108439379 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90543264 # number of misc regfile reads -system.cpu2.misc_regfile_writes 143975 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3552152 # Transaction distribution -system.iobus.trans_dist::ReadResp 3552152 # Transaction distribution -system.iobus.trans_dist::WriteReq 57748 # Transaction distribution -system.iobus.trans_dist::WriteResp 57748 # Transaction distribution -system.iobus.trans_dist::MessageReq 1661 # Transaction distribution -system.iobus.trans_dist::MessageResp 1661 # Transaction distribution +system.cpu2.cc_regfile_reads 141352578 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108476747 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90603281 # number of misc regfile reads +system.cpu2.misc_regfile_writes 149391 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3552124 # Transaction distribution +system.iobus.trans_dist::ReadResp 3552124 # Transaction distribution +system.iobus.trans_dist::WriteReq 57703 # Transaction distribution +system.iobus.trans_dist::WriteResp 57703 # Transaction distribution +system.iobus.trans_dist::MessageReq 1656 # Transaction distribution +system.iobus.trans_dist::MessageResp 1656 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) @@ -1163,15 +1166,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7124542 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3322 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3322 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7223122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7124404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95250 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95250 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7222966 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) @@ -1187,25 +1190,25 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3568515 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6644 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6644 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6602975 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2788160 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3568437 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6602845 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2765072 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 5737000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5295000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1213,62 +1216,62 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 140109000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 441000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 421000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11321000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11369000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 105499646 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 144756051 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 300163000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 299839000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 23378000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 30990000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1173000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1161000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47574 # number of replacements -system.iocache.tags.tagsinuse 0.102984 # Cycle average of tags in use +system.iocache.tags.replacements 47570 # number of replacements +system.iocache.tags.tagsinuse 0.092294 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47586 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000591236509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.102984 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006437 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006437 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000591335509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092294 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005768 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005768 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428661 # Number of tag accesses -system.iocache.tags.data_accesses 428661 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.tags.tag_accesses 428625 # Number of tag accesses +system.iocache.tags.data_accesses 428625 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 905 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses -system.iocache.demand_misses::total 909 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses -system.iocache.overall_misses::total 909 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126015772 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 126015772 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2387409874 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2387409874 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 126015772 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 126015772 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 126015772 # number of overall miss cycles -system.iocache.overall_miss_latency::total 126015772 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 905 # number of demand (read+write) misses +system.iocache.demand_misses::total 905 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 905 # number of overall misses +system.iocache.overall_misses::total 905 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128938756 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 128938756 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3283387295 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3283387295 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 128938756 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 128938756 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 128938756 # number of overall miss cycles +system.iocache.overall_miss_latency::total 128938756 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 905 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 905 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 905 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 905 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1277,337 +1280,323 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138631.212321 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 138631.212321 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 51100.382577 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 51100.382577 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138631.212321 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 138631.212321 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138631.212321 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 138631.212321 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 218 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 142473.763536 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70277.981485 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 70277.981485 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 142473.763536 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 142473.763536 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 18 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.111111 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 757 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 757 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 20232 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 20232 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 757 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 757 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 757 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 757 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88165772 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88165772 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1375809874 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1375809874 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88165772 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 88165772 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88165772 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 88165772 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.832783 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.832783 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.433048 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.433048 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.832783 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.832783 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.832783 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.832783 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 116467.334214 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68001.674278 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68001.674278 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 116467.334214 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 116467.334214 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 771 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 27816 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 27816 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 771 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 771 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 771 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 771 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 90388756 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1892587295 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1892587295 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 90388756 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 90388756 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.851934 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.595377 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.595377 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.851934 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.851934 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117235.740597 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68039.520240 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68039.520240 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 117235.740597 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 117235.740597 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 105183 # number of replacements -system.l2c.tags.tagsinuse 64828.721241 # Cycle average of tags in use -system.l2c.tags.total_refs 4684115 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169423 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.647456 # Average number of references to valid blocks. +system.l2c.tags.replacements 105297 # number of replacements +system.l2c.tags.tagsinuse 64829.932138 # Cycle average of tags in use +system.l2c.tags.total_refs 4653506 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169379 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.473925 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50898.132312 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.126487 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1607.202570 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5199.796885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 251.414397 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1573.306131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.399418 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.004770 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1229.783276 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4062.554995 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.776644 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51173.407982 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134359 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1534.003878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4961.516829 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 244.491161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1538.007484 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.330522 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1242.728330 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4127.311591 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.780844 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.024524 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.079343 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003836 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.024007 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000098 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.018765 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.061990 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989208 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6984 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54074 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.980225 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 41790330 # Number of tag accesses -system.l2c.tags.data_accesses 41790330 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 18694 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10376 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 14927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 8452 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 63394 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13067 # number of ReadReq hits -system.l2c.ReadReq_hits::total 128910 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.023407 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000127 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.018963 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.062978 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989226 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64082 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3909 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7185 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52613 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977814 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41530530 # Number of tag accesses +system.l2c.tags.data_accesses 41530530 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 18603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10268 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 13451 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7422 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 62068 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 13128 # number of ReadReq hits +system.l2c.ReadReq_hits::total 124940 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1547778 # number of Writeback hits -system.l2c.Writeback_hits::total 1547778 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 86 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 61 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 104 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 251 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57261 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 38255 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 63793 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 159309 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 284171 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 176684 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 403287 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 864142 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 469690 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 225324 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 620313 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 1315327 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 18694 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10378 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 284171 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 526951 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 14927 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 8452 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 176684 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 263579 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 63394 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13067 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 403287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 684106 # number of demand (read+write) hits -system.l2c.demand_hits::total 2467690 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 18694 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10378 # number of overall hits -system.l2c.overall_hits::cpu0.inst 284171 # number of overall hits -system.l2c.overall_hits::cpu0.data 526951 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 14927 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 8452 # number of overall hits -system.l2c.overall_hits::cpu1.inst 176684 # number of overall hits -system.l2c.overall_hits::cpu1.data 263579 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 63394 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13067 # number of overall hits -system.l2c.overall_hits::cpu2.inst 403287 # number of overall hits -system.l2c.overall_hits::cpu2.data 684106 # number of overall hits -system.l2c.overall_hits::total 2467690 # number of overall hits +system.l2c.Writeback_hits::writebacks 1547245 # number of Writeback hits +system.l2c.Writeback_hits::total 1547245 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 73 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 62 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 120 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 255 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56139 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 39496 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 63875 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 159510 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 289595 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 170749 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 390398 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 850742 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 472949 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 223727 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 618198 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 1314874 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 18603 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10270 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 289595 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 529088 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 13451 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7422 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 170749 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 263223 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 62068 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 13128 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 390398 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 682073 # number of demand (read+write) hits +system.l2c.demand_hits::total 2450068 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 18603 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10270 # number of overall hits +system.l2c.overall_hits::cpu0.inst 289595 # number of overall hits +system.l2c.overall_hits::cpu0.data 529088 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 13451 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7422 # number of overall hits +system.l2c.overall_hits::cpu1.inst 170749 # number of overall hits +system.l2c.overall_hits::cpu1.data 263223 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 62068 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 13128 # number of overall hits +system.l2c.overall_hits::cpu2.inst 390398 # number of overall hits +system.l2c.overall_hits::cpu2.data 682073 # number of overall hits +system.l2c.overall_hits::total 2450068 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 37 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 43 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 482 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 340 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 597 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1419 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 62694 # 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number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 455 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 314 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 620 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1389 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63544 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 27850 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 39321 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130715 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 5939 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 3363 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 5766 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15068 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 14540 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 4565 # 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mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017505 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014633 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010393 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019853 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.021511 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.013496 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017505 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.108452 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000583 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000077 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014633 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.073637 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.036124 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017505 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.108452 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000583 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000077 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014633 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.073637 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.036124 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 94065.789474 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22594.117647 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20861.809045 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21490.394877 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65214.425979 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69173.624917 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67578.214296 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70759.847522 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74695.191184 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73339.334574 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73365.249781 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76855.246755 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75980.110983 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70759.847522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66374.653027 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74695.191184 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71099.963222 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69738.569098 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70759.847522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66374.653027 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74695.191184 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71099.963222 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69738.569098 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152038.226472 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149511.634884 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150713.704820 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166159.963986 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 188788.548888 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178755.489022 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152286.703667 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150297.098054 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 151242.472487 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835106 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.837838 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.568127 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.413536 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.381032 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.231445 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019315 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014555 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010544 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019996 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.021822 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.013620 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.109644 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014555 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.072243 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036020 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.109644 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014555 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.072243 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036020 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 82787.878788 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22609.872611 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20978.225806 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21526.766595 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65325.332136 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69441.634241 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67734.960027 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70241.302409 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75397.762747 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73498.192573 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72655.969332 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77973.823508 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76651.312922 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70241.302409 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66357.704766 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75397.762747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71657.092559 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 70024.327007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70241.302409 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66357.704766 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75397.762747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71657.092559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70024.327007 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152098.675347 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149457.967672 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150716.387656 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167209.008514 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191973.178001 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 179675.531915 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152388.307169 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150211.166202 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 151249.478404 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5067102 # Transaction distribution -system.membus.trans_dist::ReadResp 5116344 # Transaction distribution -system.membus.trans_dist::WriteReq 13938 # Transaction distribution -system.membus.trans_dist::WriteResp 13938 # Transaction distribution -system.membus.trans_dist::Writeback 143722 # Transaction distribution -system.membus.trans_dist::CleanEvict 8694 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1684 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1684 # Transaction distribution -system.membus.trans_dist::ReadExReq 130671 # Transaction distribution -system.membus.trans_dist::ReadExResp 130671 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 49245 # Transaction distribution -system.membus.trans_dist::MessageReq 1661 # Transaction distribution -system.membus.trans_dist::MessageResp 1661 # Transaction distribution -system.membus.trans_dist::BadAddressError 3 # Transaction distribution +system.membus.trans_dist::ReadReq 5066901 # Transaction distribution +system.membus.trans_dist::ReadResp 5115808 # Transaction distribution +system.membus.trans_dist::WriteReq 13888 # Transaction distribution +system.membus.trans_dist::WriteResp 13888 # Transaction distribution +system.membus.trans_dist::Writeback 143652 # Transaction distribution +system.membus.trans_dist::CleanEvict 8856 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1645 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1645 # Transaction distribution +system.membus.trans_dist::ReadExReq 130459 # Transaction distribution +system.membus.trans_dist::ReadExResp 130459 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48907 # Transaction distribution +system.membus.trans_dist::MessageReq 1656 # Transaction distribution +system.membus.trans_dist::MessageResp 1656 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 466123 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 6 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10628209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142133 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142133 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10773664 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6644 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6644 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568515 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6075073 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17638016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27281604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3024768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3024768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30313016 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 794 # Total snoops (count) -system.membus.snoop_fanout::samples 5463823 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000304 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017433 # Request fanout histogram +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10626768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10772166 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568437 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6074345 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17606208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27248990 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3023616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3023616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30279230 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 694 # Total snoops (count) +system.membus.snoop_fanout::samples 5463095 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000303 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017408 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5462162 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1661 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5461439 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1656 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5463823 # Request fanout histogram -system.membus.reqLayer0.occupancy 233077000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5463095 # Request fanout histogram +system.membus.reqLayer0.occupancy 232635000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 304111500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 304127000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2346000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2322000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 540335137 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 583726731 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 4500 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1173000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1161000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1355052899 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1349926167 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 39163714 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 52433855 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1847,54 +1814,53 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 5228129 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7456139 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13940 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13940 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1629241 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 974526 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1670 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1670 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 290245 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 290245 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 879202 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1349341 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 1173 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 20232 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2636646 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15081470 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73733 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 221081 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18012930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56268288 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213600772 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 270696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 799584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270939340 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 164260 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10415384 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.028580 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.166622 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5228525 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7442369 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1636010 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 961008 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1644 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1644 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 290225 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 290225 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 865835 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1348541 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 1161 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 27816 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2596558 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15078411 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72306 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 219403 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17966678 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55412672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213513438 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 261576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 779088 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 269966774 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176011 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 10394757 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.029410 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.168953 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10117715 97.14% 97.14% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 297669 2.86% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 10089048 97.06% 97.06% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 305709 2.94% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10415384 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2866108499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 10394757 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2840392499 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 340500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 358500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 884325204 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 856033294 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1946611318 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1941516813 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 27584988 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 27469982 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 99698688 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 100352159 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal index 096700e63..898984ead 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal @@ -46,7 +46,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812519
+result 7812539
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json index f3e5c9bf3..feb4be957 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json @@ -3,6 +3,7 @@ "sim_quantum": 0, "system": { "kernel": "", + "mmap_using_noreserve": false, "kernel_addr_check": true, "rom": { "range": "1099243192320:1099251580927", @@ -57,9 +58,9 @@ "role": "SLAVE" }, "name": "iobus", + "forward_latency": 1, "clk_domain": "system.clk_domain", - "header_cycles": 1, - "width": 8, + "width": 16, "eventq_index": 0, "master": { "peer": [ @@ -81,10 +82,12 @@ ], "role": "MASTER" }, + "response_latency": 2, "cxx_class": "NoncoherentXBar", "path": "system.iobus", "type": "NoncoherentXBar", - "use_default_range": false + "use_default_range": false, + "frontend_latency": 2 }, "t1000": { "htod": { @@ -484,11 +487,11 @@ "work_end_ckpt_count": 0, "nvram_addr": 133429198848, "memories": [ - "system.nvram", - "system.physmem1", "system.hypervisor_desc", + "system.nvram", "system.partition_desc", "system.physmem0", + "system.physmem1", "system.rom" ], "work_begin_ckpt_count": 0, @@ -582,10 +585,10 @@ "ret_data16": 65535 }, "snoop_filter": null, + "forward_latency": 4, "clk_domain": "system.clk_domain", - "header_cycles": 1, "system": "system", - "width": 8, + "width": 16, "eventq_index": 0, "master": { "peer": [ @@ -601,10 +604,13 @@ ], "role": "MASTER" }, + "response_latency": 2, "cxx_class": "CoherentXBar", "path": "system.membus", + "snoop_response_latency": 4, "type": "CoherentXBar", - "use_default_range": false + "use_default_range": false, + "frontend_latency": 3 }, "nvram": { "range": "133429198848:133429207039", |