diff options
Diffstat (limited to 'tests/long/fs')
7 files changed, 7309 insertions, 6201 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index a9e8e7d4a..71c7ebea7 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,376 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.902683 # Number of seconds simulated -sim_ticks 1902682770000 # Number of ticks simulated -final_tick 1902682770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.898954 # Number of seconds simulated +sim_ticks 1898954186500 # Number of ticks simulated +final_tick 1898954186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192931 # Simulator instruction rate (inst/s) -host_op_rate 192931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6436506827 # Simulator tick rate (ticks/s) -host_mem_usage 296908 # Number of bytes of host memory used -host_seconds 295.61 # Real time elapsed on the host -sim_insts 57032045 # Number of instructions simulated -sim_ops 57032045 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 906816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24518592 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 73984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 789824 # Number of bytes read from this memory -system.physmem.bytes_read::total 28940032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 906816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 73984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 980800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7895360 # Number of bytes written to this memory -system.physmem.bytes_written::total 7895360 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 383103 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1156 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12341 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452188 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123365 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123365 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 476599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12886327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1393199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 38884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 415111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15210119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 476599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 38884 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4149593 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4149593 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4149593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 476599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12886327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1393199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 38884 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 415111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19359713 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 345291 # number of replacements -system.l2c.tagsinuse 65280.360301 # Cycle average of tags in use -system.l2c.total_refs 2575351 # Total number of references to valid blocks. -system.l2c.sampled_refs 410382 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.275497 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6143524000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53635.672684 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5378.326569 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6042.958234 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 144.667579 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 78.735234 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.818415 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.082067 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.092208 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002207 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001201 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996099 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 798441 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 696934 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 292090 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 99595 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1887060 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 812223 # number of Writeback hits -system.l2c.Writeback_hits::total 812223 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 566 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 46 # number of SCUpgradeReq hits +host_inst_rate 93254 # Simulator instruction rate (inst/s) +host_op_rate 93254 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3072830921 # Simulator tick rate (ticks/s) +host_mem_usage 330780 # Number of bytes of host memory used +host_seconds 617.98 # Real time elapsed on the host +sim_insts 57629320 # Number of instructions simulated +sim_ops 57629320 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 946048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24721152 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 36608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 493888 # Number of bytes read from this memory +system.physmem.bytes_read::total 28848320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 946048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 36608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 982656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7831936 # Number of bytes written to this memory +system.physmem.bytes_written::total 7831936 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14782 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386268 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 572 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7717 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450755 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122374 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122374 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 498194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13018298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 260084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15191688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 498194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517472 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4124342 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4124342 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4124342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 498194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13018298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 260084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19316030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450755 # Total number of read requests seen +system.physmem.writeReqs 122374 # Total number of write requests seen +system.physmem.cpureqs 604625 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28848320 # Total number of bytes read from memory +system.physmem.bytesWritten 7831936 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28848320 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7831936 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 7306 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28435 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28036 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28258 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28091 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28033 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28162 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28366 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28166 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28158 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28038 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7848 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7611 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7694 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7537 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7588 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7788 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7389 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7747 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7671 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7728 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7650 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7483 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry +system.physmem.totGap 1898947634000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 450755 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 123146 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 7306 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 322964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1794 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 4068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 6521684939 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13830350939 # Sum of mem lat for all requests +system.physmem.totBusLat 1802760000 # Total cycles spent in databus access +system.physmem.totBankLat 5505906000 # Total cycles spent in bank access +system.physmem.avgQLat 14470.45 # Average queueing delay per request +system.physmem.avgBankLat 12216.61 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30687.06 # Average memory access latency +system.physmem.avgRdBW 15.19 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.19 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.12 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgWrQLen 13.13 # Average write queue length over time +system.physmem.readRowHits 430277 # Number of row buffer hits during reads +system.physmem.writeRowHits 78021 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes +system.physmem.avgGap 3313298.81 # Average gap between requests +system.l2c.replacements 343856 # number of replacements +system.l2c.tagsinuse 65278.684390 # Cycle average of tags in use +system.l2c.total_refs 2547974 # Total number of references to valid blocks. +system.l2c.sampled_refs 408869 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.231761 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53716.705985 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5434.737424 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 5906.149934 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 139.277407 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 81.813640 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.819652 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.082928 # 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mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.331099 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001562 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.044386 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166714 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 48644.579246 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30096.622279 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 55700.059441 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 55103.470430 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 31127.631742 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10063.910014 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.755508 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10041.056259 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10112.851197 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10007.698969 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10060.030036 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59453.322940 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 114397.203146 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62799.785091 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 48644.579246 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38718.064012 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 55700.059441 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 111549.634263 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40474.601494 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 48644.579246 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38718.064012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 55700.059441 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 111549.634263 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40474.601494 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -347,39 +505,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.492574 # Cycle average of tags in use +system.iocache.replacements 41694 # number of replacements +system.iocache.tagsinuse 0.494943 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709348959000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.492574 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.030786 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.030786 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses -system.iocache.ReadReq_misses::total 177 # number of ReadReq misses +system.iocache.warmup_cycle 1705457230000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.494943 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030934 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030934 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses -system.iocache.demand_misses::total 41729 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses -system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21127998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21127998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11486516806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11486516806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11507644804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11507644804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11507644804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11507644804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21041998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21041998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9500949806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9500949806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9521991804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9521991804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9521991804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9521991804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -388,40 +546,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119367.220339 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119367.220339 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276437.158404 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 276437.158404 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 275770.921997 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 275770.921997 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 200533 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120931.022989 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120931.022989 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228652.045774 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228652.045774 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228202.842448 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228202.842448 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228202.842448 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228202.842448 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 192112 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24673 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23026 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.127629 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.343264 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11923998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11923998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9325812806 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9325812806 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9337736804 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9337736804 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9337736804 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9337736804 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11993000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11993000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338178524 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7338178524 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7350171524 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7350171524 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7350171524 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7350171524 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +588,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67367.220339 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67367.220339 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224437.158404 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 224437.158404 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68925.287356 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68925.287356 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176602.294089 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176602.294089 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176153.274313 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176153.274313 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176153.274313 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176153.274313 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +613,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8304100 # DTB read hits -system.cpu0.dtb.read_misses 28307 # DTB read misses -system.cpu0.dtb.read_acv 549 # DTB read access violations -system.cpu0.dtb.read_accesses 542239 # DTB read accesses -system.cpu0.dtb.write_hits 5411904 # DTB write hits -system.cpu0.dtb.write_misses 5987 # DTB write misses +system.cpu0.dtb.read_hits 8153093 # DTB read hits +system.cpu0.dtb.read_misses 30801 # DTB read misses +system.cpu0.dtb.read_acv 546 # DTB read access violations +system.cpu0.dtb.read_accesses 631302 # DTB read accesses +system.cpu0.dtb.write_hits 5186191 # DTB write hits +system.cpu0.dtb.write_misses 6023 # DTB write misses system.cpu0.dtb.write_acv 347 # DTB write access violations -system.cpu0.dtb.write_accesses 182798 # DTB write accesses -system.cpu0.dtb.data_hits 13716004 # DTB hits -system.cpu0.dtb.data_misses 34294 # DTB misses -system.cpu0.dtb.data_acv 896 # DTB access violations -system.cpu0.dtb.data_accesses 725037 # DTB accesses -system.cpu0.itb.fetch_hits 908718 # ITB hits -system.cpu0.itb.fetch_misses 19910 # ITB misses -system.cpu0.itb.fetch_acv 927 # ITB acv -system.cpu0.itb.fetch_accesses 928628 # ITB accesses +system.cpu0.dtb.write_accesses 217125 # DTB write accesses +system.cpu0.dtb.data_hits 13339284 # DTB hits +system.cpu0.dtb.data_misses 36824 # DTB misses +system.cpu0.dtb.data_acv 893 # DTB access violations +system.cpu0.dtb.data_accesses 848427 # DTB accesses +system.cpu0.itb.fetch_hits 954719 # ITB hits +system.cpu0.itb.fetch_misses 30502 # ITB misses +system.cpu0.itb.fetch_acv 1031 # ITB acv +system.cpu0.itb.fetch_accesses 985221 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,277 +641,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 102599658 # number of cpu cycles simulated +system.cpu0.numCycles 96359628 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 11825647 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 9917652 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 342692 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 8240217 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5044056 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11511160 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9658650 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 337362 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8089137 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5013359 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 768623 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 31919 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 23566044 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 60418395 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 11825647 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5812679 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11434253 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1624928 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 35275815 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31363 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 170412 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 309547 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7444211 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 224420 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 71849758 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.840899 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.174060 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 738841 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 28813 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 22209501 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 59836413 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11511160 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5752200 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11350991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1703319 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34574956 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 35024 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 203611 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 316697 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7365602 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 218420 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 69794661 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.857321 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.189603 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 60415505 84.09% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 744936 1.04% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1526054 2.12% 87.25% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 669496 0.93% 88.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2482176 3.45% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 513952 0.72% 92.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 559997 0.78% 93.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 746719 1.04% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4190923 5.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 58443670 83.74% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 721745 1.03% 84.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1525948 2.19% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 670208 0.96% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2529232 3.62% 91.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 511055 0.73% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 558087 0.80% 93.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 646305 0.93% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4188411 6.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 71849758 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.115260 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.588875 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 24832568 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34702410 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10423010 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 862232 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1029537 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 502827 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 32976 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 59359454 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 95150 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1029537 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 25748676 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14416729 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17004300 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9792924 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3857590 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 56337606 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6610 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 598180 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1362975 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 37819724 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 68629747 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 68286150 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 343597 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33121112 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4698612 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1343902 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 201432 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10333121 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8734327 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5677673 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1105299 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 704273 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50005822 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1695696 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 48865145 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 103608 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5731519 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2860845 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1151664 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 71849758 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.680102 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.326568 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 69794661 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.119460 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.620970 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23572170 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 33977525 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10309860 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 863665 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1071440 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 494315 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32656 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 58557743 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 90732 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1071440 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24508121 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14373596 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16410684 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9644673 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3786145 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 55387876 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6888 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 592503 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1353497 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 37339158 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 67830341 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 67526671 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 303670 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 32375017 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4964141 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1283235 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 190076 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10267361 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8584787 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5466291 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1084962 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 724878 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49128818 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1589448 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 47805943 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 98656 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5900406 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3193389 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1078704 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 69794661 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.684951 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.331704 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 50068220 69.68% 69.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9955153 13.86% 83.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4454682 6.20% 89.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2911875 4.05% 93.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2358569 3.28% 97.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1157257 1.61% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 610758 0.85% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 286058 0.40% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 47186 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 48560473 69.58% 69.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9626391 13.79% 83.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4360326 6.25% 89.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2905573 4.16% 93.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2277062 3.26% 97.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1128487 1.62% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 610541 0.87% 99.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 278212 0.40% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 47596 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 71849758 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 69794661 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 80509 12.84% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 294043 46.91% 59.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 252280 40.25% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 83272 13.43% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 13.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 288642 46.54% 59.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 248279 40.03% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2557 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 33918404 69.41% 69.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 54116 0.11% 69.53% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 12070 0.02% 69.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.56% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8648673 17.70% 87.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5478002 11.21% 98.47% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 750056 1.53% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 33277792 69.61% 69.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 52563 0.11% 69.73% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 13047 0.03% 69.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.76% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8484999 17.75% 87.51% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5253957 10.99% 98.50% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 718601 1.50% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 48865145 # Type of FU issued -system.cpu0.iq.rate 0.476270 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 626833 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012828 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 169818867 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57206555 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 47890608 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 491622 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 238128 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 232129 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 49232078 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 257343 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 523556 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 47805943 # Type of FU issued +system.cpu0.iq.rate 0.496120 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 620193 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012973 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 165689680 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 56419476 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 46799675 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 435716 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 211307 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 205983 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 48194794 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 228014 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 514272 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1075506 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2442 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 11895 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 454594 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1137404 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2618 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12330 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 467046 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 86028 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18608 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 143062 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1029537 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10326104 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 769928 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 54791843 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 549393 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8734327 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5677673 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1493453 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 559696 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5669 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 11895 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 183351 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 329192 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 512543 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 48451300 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8354077 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 413845 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1071440 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10277613 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 727728 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 53688552 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 610167 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8584787 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5466291 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1400307 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 521112 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4713 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12330 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 181936 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 316829 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 498765 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 47397397 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8205181 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 408546 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3090325 # number of nop insts executed -system.cpu0.iew.exec_refs 13784796 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7754310 # Number of branches executed -system.cpu0.iew.exec_stores 5430719 # Number of stores executed -system.cpu0.iew.exec_rate 0.472236 # Inst execution rate -system.cpu0.iew.wb_sent 48208648 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48122737 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24107105 # num instructions producing a value -system.cpu0.iew.wb_consumers 32426814 # num instructions consuming a value +system.cpu0.iew.exec_nop 2970286 # number of nop insts executed +system.cpu0.iew.exec_refs 13410008 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7582856 # Number of branches executed +system.cpu0.iew.exec_stores 5204827 # Number of stores executed +system.cpu0.iew.exec_rate 0.491880 # Inst execution rate +system.cpu0.iew.wb_sent 47094366 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 47005658 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23624719 # num instructions producing a value +system.cpu0.iew.wb_consumers 31676204 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.469034 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.743431 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.487815 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.745819 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6216029 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 544032 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 479899 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 70820221 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.684637 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.594318 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6363159 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 510744 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 465851 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 68723221 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.687218 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.593416 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 52470926 74.09% 74.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7676401 10.84% 84.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4235846 5.98% 90.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2227139 3.14% 94.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1283042 1.81% 95.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 528527 0.75% 96.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 441494 0.62% 97.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 421867 0.60% 97.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1534979 2.17% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 50805017 73.93% 73.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7482510 10.89% 84.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4158339 6.05% 90.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2211388 3.22% 94.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1226271 1.78% 95.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 519535 0.76% 96.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 434174 0.63% 97.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 401210 0.58% 97.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1484777 2.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 70820221 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 48486178 # Number of instructions committed -system.cpu0.commit.committedOps 48486178 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 68723221 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 47227841 # Number of instructions committed +system.cpu0.commit.committedOps 47227841 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12881900 # Number of memory references committed -system.cpu0.commit.loads 7658821 # Number of loads committed -system.cpu0.commit.membars 183715 # Number of memory barriers committed -system.cpu0.commit.branches 7346956 # Number of branches committed -system.cpu0.commit.fp_insts 229898 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 44900899 # Number of committed integer instructions. -system.cpu0.commit.function_calls 613493 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1534979 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12446628 # Number of memory references committed +system.cpu0.commit.loads 7447383 # Number of loads committed +system.cpu0.commit.membars 170869 # Number of memory barriers committed +system.cpu0.commit.branches 7170885 # Number of branches committed +system.cpu0.commit.fp_insts 203520 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 43794871 # Number of committed integer instructions. +system.cpu0.commit.function_calls 589410 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1484777 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123809295 # The number of ROB reads -system.cpu0.rob.rob_writes 110434143 # The number of ROB writes -system.cpu0.timesIdled 1033297 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 30749900 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3702120338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 45684021 # Number of Instructions Simulated -system.cpu0.committedOps 45684021 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 45684021 # Number of Instructions Simulated -system.cpu0.cpi 2.245854 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.245854 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.445265 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.445265 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 63838240 # number of integer regfile reads -system.cpu0.int_regfile_writes 34928793 # number of integer regfile writes -system.cpu0.fp_regfile_reads 112215 # number of floating regfile reads -system.cpu0.fp_regfile_writes 113746 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1561574 # number of misc regfile reads -system.cpu0.misc_regfile_writes 757779 # number of misc regfile writes +system.cpu0.rob.rob_reads 120629648 # The number of ROB reads +system.cpu0.rob.rob_writes 108253472 # The number of ROB writes +system.cpu0.timesIdled 983557 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26564967 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3700831730 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 44545141 # Number of Instructions Simulated +system.cpu0.committedOps 44545141 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 44545141 # Number of Instructions Simulated +system.cpu0.cpi 2.163191 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.163191 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.462280 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.462280 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 62595782 # number of integer regfile reads +system.cpu0.int_regfile_writes 34216642 # number of integer regfile writes +system.cpu0.fp_regfile_reads 100415 # number of floating regfile reads +system.cpu0.fp_regfile_writes 101247 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1454133 # number of misc regfile reads +system.cpu0.misc_regfile_writes 720721 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -785,245 +943,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 812060 # number of replacements -system.cpu0.icache.tagsinuse 510.054551 # Cycle average of tags in use -system.cpu0.icache.total_refs 6590229 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 812572 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.110332 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23200943000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.054551 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996200 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996200 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6590229 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6590229 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6590229 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6590229 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6590229 # number of overall hits -system.cpu0.icache.overall_hits::total 6590229 # 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number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7444210 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7444210 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7444210 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7444210 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7444210 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7444210 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114717 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.114717 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114717 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.114717 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114717 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.114717 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13884.448828 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13884.448828 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13884.448828 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13884.448828 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2511 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.771654 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.replacements 750148 # number of replacements +system.cpu0.icache.tagsinuse 510.325521 # Cycle average of tags in use +system.cpu0.icache.total_refs 6574672 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 750660 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.758522 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.325521 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996730 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996730 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6574672 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6574672 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6574672 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6574672 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6574672 # number of overall hits +system.cpu0.icache.overall_hits::total 6574672 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 790930 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 790930 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 790930 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 790930 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 790930 # number of overall misses +system.cpu0.icache.overall_misses::total 790930 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11244615993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11244615993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11244615993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11244615993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11244615993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11244615993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7365602 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7365602 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7365602 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7365602 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7365602 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7365602 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.107382 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.107382 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.107382 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.107382 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.107382 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.107382 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14216.954715 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14216.954715 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14216.954715 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14216.954715 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14216.954715 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14216.954715 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2954 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 318 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 148 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.959459 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 318 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41272 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 41272 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41272 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 41272 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41272 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 41272 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 812709 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 812709 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 812709 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 812709 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 812709 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 812709 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9799988995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9799988995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9799988995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9799988995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9799988995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9799988995 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109173 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.109173 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.109173 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12058.423119 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40102 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 40102 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 40102 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 40102 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 40102 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 40102 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 750828 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 750828 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 750828 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 750828 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 750828 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 750828 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9260198495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9260198495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9260198495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9260198495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9260198495 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9260198495 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.101937 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.101937 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.101937 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.101937 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.101937 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.101937 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12333.315347 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12333.315347 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12333.315347 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12333.315347 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12333.315347 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12333.315347 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1218511 # number of replacements -system.cpu0.dcache.tagsinuse 505.616339 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9815926 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1218945 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.052805 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 23286000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.616339 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987532 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987532 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6063177 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6063177 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3417347 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3417347 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151987 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 151987 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174443 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 174443 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9480524 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9480524 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9480524 # number of overall hits -system.cpu0.dcache.overall_hits::total 9480524 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1492446 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1492446 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1612731 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1612731 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19429 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19429 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4062 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4062 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3105177 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3105177 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3105177 # number of overall misses -system.cpu0.dcache.overall_misses::total 3105177 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34499425000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34499425000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55944257946 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 55944257946 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 264930500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 264930500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47614500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 47614500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 90443682946 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 90443682946 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 90443682946 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 90443682946 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7555623 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7555623 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5030078 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5030078 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 171416 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 171416 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178505 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 178505 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12585701 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12585701 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12585701 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12585701 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197528 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197528 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320617 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.320617 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113344 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113344 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.022756 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.022756 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.246723 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.246723 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.246723 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.246723 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23116.028989 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23116.028989 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34689.144033 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34689.144033 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13635.827886 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13635.827886 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11721.935007 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11721.935007 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 29126.739940 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 29126.739940 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1403245 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 435 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 52795 # number of cycles access was blocked +system.cpu0.dcache.replacements 1172092 # number of replacements +system.cpu0.dcache.tagsinuse 505.853040 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9524802 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1172488 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.123582 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21811000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.853040 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987994 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987994 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5943112 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5943112 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3262323 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3262323 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143230 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 143230 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 162594 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 162594 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9205435 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9205435 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9205435 # number of overall hits +system.cpu0.dcache.overall_hits::total 9205435 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1417911 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1417911 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1553318 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1553318 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17723 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17723 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5875 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5875 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2971229 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2971229 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2971229 # number of overall misses +system.cpu0.dcache.overall_misses::total 2971229 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31710477500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 31710477500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68102427025 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 68102427025 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 236251500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 236251500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44454500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44454500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 99812904525 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 99812904525 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 99812904525 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 99812904525 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7361023 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7361023 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4815641 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4815641 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160953 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 160953 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 168469 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 168469 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12176664 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12176664 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12176664 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12176664 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.192624 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.192624 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322557 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.322557 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110113 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110113 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.034873 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.034873 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244010 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.244010 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244010 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.244010 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22364.222790 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22364.222790 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43843.196966 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43843.196966 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13330.220617 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13330.220617 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7566.723404 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7566.723404 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33593.137562 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33593.137562 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33593.137562 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33593.137562 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2427231 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1005 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 46334 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.579127 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 62.142857 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 52.385527 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 143.571429 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 710192 # number of writebacks -system.cpu0.dcache.writebacks::total 710192 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 524907 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 524907 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1358576 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1358576 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4179 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4179 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1883483 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1883483 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1883483 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1883483 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 967539 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 967539 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254155 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 254155 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15250 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15250 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4062 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4062 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1221694 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1221694 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1221694 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1221694 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23357450000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23357450000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8081474275 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8081474275 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 163906000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 163906000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 39490500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 39490500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31438924275 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31438924275 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31438924275 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31438924275 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451861000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451861000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167064498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167064498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3618925498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3618925498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128055 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128055 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050527 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050527 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088965 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088965 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.022756 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.022756 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097070 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097070 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24141.094054 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24141.094054 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31797.423915 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31797.423915 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10747.934426 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10747.934426 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9721.935007 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9721.935007 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 669951 # number of writebacks +system.cpu0.dcache.writebacks::total 669951 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 478870 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 478870 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1309589 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1309589 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3866 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3866 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1788459 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1788459 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1788459 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1788459 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939041 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939041 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 243729 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 243729 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13857 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13857 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5874 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5874 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182770 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1182770 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182770 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1182770 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20515201000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20515201000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9973935364 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9973935364 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136652000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136652000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32706500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32706500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30489136364 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30489136364 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30489136364 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30489136364 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1471717500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1471717500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2287191498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2287191498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3758908998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3758908998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127569 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127569 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050612 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050612 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086093 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086093 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.034867 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.034867 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097134 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097134 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097134 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097134 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21846.970473 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21846.970473 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40922.234794 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40922.234794 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9861.586202 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9861.586202 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5568.011576 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5568.011576 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25777.739006 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25777.739006 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25777.739006 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25777.739006 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1035,22 +1193,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2472786 # DTB read hits -system.cpu1.dtb.read_misses 14686 # DTB read misses -system.cpu1.dtb.read_acv 33 # DTB read access violations -system.cpu1.dtb.read_accesses 413814 # DTB read accesses -system.cpu1.dtb.write_hits 1645990 # DTB write hits -system.cpu1.dtb.write_misses 3399 # DTB write misses -system.cpu1.dtb.write_acv 61 # DTB write access violations -system.cpu1.dtb.write_accesses 158815 # DTB write accesses -system.cpu1.dtb.data_hits 4118776 # DTB hits -system.cpu1.dtb.data_misses 18085 # DTB misses -system.cpu1.dtb.data_acv 94 # DTB access violations -system.cpu1.dtb.data_accesses 572629 # DTB accesses -system.cpu1.itb.fetch_hits 546471 # ITB hits -system.cpu1.itb.fetch_misses 10636 # ITB misses -system.cpu1.itb.fetch_acv 251 # ITB acv -system.cpu1.itb.fetch_accesses 557107 # ITB accesses +system.cpu1.dtb.read_hits 2751784 # DTB read hits +system.cpu1.dtb.read_misses 11470 # DTB read misses +system.cpu1.dtb.read_acv 7 # DTB read access violations +system.cpu1.dtb.read_accesses 320817 # DTB read accesses +system.cpu1.dtb.write_hits 1920140 # DTB write hits +system.cpu1.dtb.write_misses 2953 # DTB write misses +system.cpu1.dtb.write_acv 42 # DTB write access violations +system.cpu1.dtb.write_accesses 122077 # DTB write accesses +system.cpu1.dtb.data_hits 4671924 # DTB hits +system.cpu1.dtb.data_misses 14423 # DTB misses +system.cpu1.dtb.data_acv 49 # DTB access violations +system.cpu1.dtb.data_accesses 442894 # DTB accesses +system.cpu1.itb.fetch_hits 498760 # ITB hits +system.cpu1.itb.fetch_misses 8025 # ITB misses +system.cpu1.itb.fetch_acv 112 # ITB acv +system.cpu1.itb.fetch_accesses 506785 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1063,516 +1221,515 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 20144234 # number of cpu cycles simulated +system.cpu1.numCycles 23450533 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 3332472 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2756183 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 108633 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 2168857 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1160511 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3776767 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 3137470 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 107427 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2636449 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1329693 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 228547 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 10150 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 7838813 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 15883595 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3332472 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1389058 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2861385 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 534677 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 7961253 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 27792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 84864 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 61219 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1925840 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 71197 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 19177134 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.828257 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.199800 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 256698 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 10696 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 9578000 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17862357 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3776767 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1586391 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3193569 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 532728 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 8846684 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 29714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 64849 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 64234 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.CacheLines 2092153 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 72512 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 22109536 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.807903 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.182028 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 16315749 85.08% 85.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 188313 0.98% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 313367 1.63% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 233008 1.22% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 393584 2.05% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 151826 0.79% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 167771 0.87% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 278696 1.45% 94.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1134820 5.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 18915967 85.56% 85.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 225371 1.02% 86.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 332195 1.50% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 235368 1.06% 89.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 429129 1.94% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 160604 0.73% 91.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 176264 0.80% 92.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 387732 1.75% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1246906 5.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 19177134 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.165431 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.788493 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 7716271 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8310209 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2661595 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 156637 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 332421 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 147192 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 9531 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 15577857 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 28018 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 332421 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 7986115 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 672083 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6791538 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2542197 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 852778 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 14454091 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 131 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 86206 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 218054 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 9478411 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 17286766 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 17086477 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 200289 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 8045295 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1433108 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 570111 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 60569 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2590157 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2624799 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1738404 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 257229 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 149585 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12667252 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 630653 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 12308685 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 34992 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1859186 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 963032 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 447479 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 19177134 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.641842 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.313805 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 22109536 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.161053 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.761704 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 9287856 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 9344742 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2981707 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 172176 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 323054 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 161936 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 9554 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 17577560 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 27080 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 323054 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 9598975 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 567037 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 7834145 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2842462 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 943861 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 16294411 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 85147 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 230847 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 10570715 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 19279832 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 19004281 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 275551 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9242282 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1328425 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 653029 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 73319 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2960053 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2891333 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2010374 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 258927 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 184993 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 14228135 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 747471 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 13980669 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 34327 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1780795 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 830376 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 520995 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 22109536 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.632337 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.304677 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 13743416 71.67% 71.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2506419 13.07% 84.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1066336 5.56% 90.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 706714 3.69% 93.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 606260 3.16% 97.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 273557 1.43% 98.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 174545 0.91% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 89739 0.47% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10148 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15925897 72.03% 72.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2876428 13.01% 85.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1188641 5.38% 90.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 788361 3.57% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 710967 3.22% 97.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 312206 1.41% 98.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 203719 0.92% 99.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 91872 0.42% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 11445 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 19177134 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 22109536 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 4629 1.86% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 131937 52.95% 54.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 112626 45.20% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4072 1.54% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 138321 52.40% 53.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 121563 46.05% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7659302 62.23% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 19564 0.16% 62.42% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 14781 0.12% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2596890 21.10% 83.66% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1675725 13.61% 97.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 335297 2.72% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3973 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 8718475 62.36% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 23525 0.17% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14518 0.10% 62.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1986 0.01% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.68% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2887601 20.65% 83.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1950660 13.95% 97.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 379931 2.72% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 12308685 # Type of FU issued -system.cpu1.iq.rate 0.611028 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 249192 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020245 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 43789272 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15018387 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 11932725 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 289415 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 141077 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 136872 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 12402102 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 151024 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 115183 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 13980669 # Type of FU issued +system.cpu1.iq.rate 0.596177 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 263956 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.018880 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 49973211 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 16565755 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 13576031 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 395945 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 192396 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 186883 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 14033908 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 206744 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 127652 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 382493 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 2469 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 155910 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 343707 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 718 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1847 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 149646 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 398 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 20099 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8933 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 332421 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 409059 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 59053 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13963733 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 192284 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2624799 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1738404 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 567278 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49311 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2791 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 2469 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 54746 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 126604 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 181350 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 12183266 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2497630 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 125418 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 323054 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 323914 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 83587 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 15804070 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 217247 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2891333 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 2010374 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 666348 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 75335 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2938 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1847 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 54178 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 138289 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 192467 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 13856768 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2775542 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 123900 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 665828 # number of nop insts executed -system.cpu1.iew.exec_refs 4154589 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1827055 # Number of branches executed -system.cpu1.iew.exec_stores 1656959 # Number of stores executed -system.cpu1.iew.exec_rate 0.604802 # Inst execution rate -system.cpu1.iew.wb_sent 12107744 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 12069597 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5640555 # num instructions producing a value -system.cpu1.iew.wb_consumers 7931807 # num instructions consuming a value +system.cpu1.iew.exec_nop 828464 # number of nop insts executed +system.cpu1.iew.exec_refs 4708126 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2079937 # Number of branches executed +system.cpu1.iew.exec_stores 1932584 # Number of stores executed +system.cpu1.iew.exec_rate 0.590894 # Inst execution rate +system.cpu1.iew.wb_sent 13794604 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 13762914 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 6356145 # num instructions producing a value +system.cpu1.iew.wb_consumers 9022133 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.599159 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.711131 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.586891 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.704506 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1943114 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 183174 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 170211 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 18844713 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.633421 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.575988 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1892811 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 226476 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 180279 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 21786482 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.634671 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.584399 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 14387001 76.35% 76.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2066578 10.97% 87.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 777942 4.13% 91.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 478446 2.54% 93.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 347277 1.84% 95.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 135394 0.72% 96.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 132721 0.70% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 138400 0.73% 97.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 380954 2.02% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 16693912 76.63% 76.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2323450 10.66% 87.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 881751 4.05% 91.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 546550 2.51% 93.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 424121 1.95% 95.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 149663 0.69% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 143043 0.66% 97.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 194342 0.89% 98.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 429650 1.97% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 18844713 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 11936636 # Number of instructions committed -system.cpu1.commit.committedOps 11936636 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 21786482 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 13827253 # Number of instructions committed +system.cpu1.commit.committedOps 13827253 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3824800 # Number of memory references committed -system.cpu1.commit.loads 2242306 # Number of loads committed -system.cpu1.commit.membars 59908 # Number of memory barriers committed -system.cpu1.commit.branches 1711003 # Number of branches committed -system.cpu1.commit.fp_insts 135276 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 11053668 # Number of committed integer instructions. -system.cpu1.commit.function_calls 186526 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 380954 # number cycles where commit BW limit reached +system.cpu1.commit.refs 4408354 # Number of memory references committed +system.cpu1.commit.loads 2547626 # Number of loads committed +system.cpu1.commit.membars 77059 # Number of memory barriers committed +system.cpu1.commit.branches 1974738 # Number of branches committed +system.cpu1.commit.fp_insts 185573 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 12741220 # Number of committed integer instructions. +system.cpu1.commit.function_calls 216858 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 429650 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 32234171 # The number of ROB reads -system.cpu1.rob.rob_writes 28090700 # The number of ROB writes -system.cpu1.timesIdled 170938 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 967100 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3785218747 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 11348024 # Number of Instructions Simulated -system.cpu1.committedOps 11348024 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 11348024 # Number of Instructions Simulated -system.cpu1.cpi 1.775131 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.775131 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.563339 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.563339 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 15713233 # number of integer regfile reads -system.cpu1.int_regfile_writes 8535659 # number of integer regfile writes -system.cpu1.fp_regfile_reads 74431 # number of floating regfile reads -system.cpu1.fp_regfile_writes 74222 # number of floating regfile writes -system.cpu1.misc_regfile_reads 667576 # number of misc regfile reads -system.cpu1.misc_regfile_writes 284444 # number of misc regfile writes -system.cpu1.icache.replacements 292722 # number of replacements -system.cpu1.icache.tagsinuse 471.494279 # Cycle average of tags in use -system.cpu1.icache.total_refs 1621349 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 293230 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.529274 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1876700215000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 471.494279 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.920887 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.920887 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1621349 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1621349 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1621349 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1621349 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1621349 # number of overall hits -system.cpu1.icache.overall_hits::total 1621349 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 304491 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 304491 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 304491 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 304491 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 304491 # number of overall misses -system.cpu1.icache.overall_misses::total 304491 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4065162500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4065162500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4065162500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4065162500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4065162500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4065162500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1925840 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1925840 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1925840 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1925840 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1925840 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1925840 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158108 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.158108 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158108 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.158108 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158108 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.158108 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13350.681958 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13350.681958 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13350.681958 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13350.681958 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked +system.cpu1.rob.rob_reads 36982885 # The number of ROB reads +system.cpu1.rob.rob_writes 31761465 # The number of ROB writes +system.cpu1.timesIdled 211192 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1340997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3774455201 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13084179 # Number of Instructions Simulated +system.cpu1.committedOps 13084179 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 13084179 # Number of Instructions Simulated +system.cpu1.cpi 1.792282 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.792282 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.557948 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.557948 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 17801475 # number of integer regfile reads +system.cpu1.int_regfile_writes 9673582 # number of integer regfile writes +system.cpu1.fp_regfile_reads 97896 # number of floating regfile reads +system.cpu1.fp_regfile_writes 98917 # number of floating regfile writes +system.cpu1.misc_regfile_reads 828029 # number of misc regfile reads +system.cpu1.misc_regfile_writes 335588 # number of misc regfile writes +system.cpu1.icache.replacements 365714 # number of replacements +system.cpu1.icache.tagsinuse 472.361820 # Cycle average of tags in use +system.cpu1.icache.total_refs 1714322 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 366225 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 4.681062 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1888132363000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 472.361820 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.922582 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.922582 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1714323 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1714323 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1714323 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1714323 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1714323 # number of overall hits +system.cpu1.icache.overall_hits::total 1714323 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377830 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377830 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377830 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377830 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377830 # number of overall misses +system.cpu1.icache.overall_misses::total 377830 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5021047500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5021047500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5021047500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5021047500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5021047500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5021047500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2092153 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2092153 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2092153 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2092153 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2092153 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2092153 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.180594 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.180594 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.180594 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.180594 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.180594 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.180594 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13289.171056 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13289.171056 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13289.171056 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13289.171056 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13289.171056 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13289.171056 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 20 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.826087 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 3.333333 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11170 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 11170 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 11170 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 11170 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 11170 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 11170 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 293321 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 293321 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 293321 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 293321 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 293321 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 293321 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3385018500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3385018500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3385018500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3385018500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3385018500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3385018500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152308 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.152308 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.152308 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11540.321013 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11532 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 11532 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 11532 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 11532 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 11532 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 11532 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366298 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 366298 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 366298 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 366298 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 366298 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 366298 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4196886000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4196886000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4196886000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4196886000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4196886000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4196886000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.175082 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.175082 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.175082 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.175082 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.175082 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.175082 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11457.572796 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11457.572796 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11457.572796 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11457.572796 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11457.572796 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11457.572796 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 154238 # number of replacements -system.cpu1.dcache.tagsinuse 492.768701 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3312022 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 154750 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 21.402404 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 38606824000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 492.768701 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.962439 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.962439 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2009764 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2009764 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1195197 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1195197 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47136 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47136 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 45762 # 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number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 619314 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 619314 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 619314 # number of overall misses -system.cpu1.dcache.overall_misses::total 619314 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4275169500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4275169500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8473061608 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8473061608 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77853000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 77853000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49370500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49370500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12748231108 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12748231108 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12748231108 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12748231108 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2298529 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2298529 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1525746 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1525746 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54626 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 54626 # 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Cycle average of tags in use +system.cpu1.dcache.total_refs 3781655 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 178225 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 21.218432 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 31174945000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 493.227826 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.963336 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.963336 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2216837 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2216837 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1431438 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1431438 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 57301 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 67682 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 62715 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 62715 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4353333 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4353333 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4353333 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4353333 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.134863 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.134863 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.200725 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.200725 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153379 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.153379 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100869 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100869 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.161958 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.161958 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.161958 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.161958 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14423.884830 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14423.884830 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30003.227783 # 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number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 7912 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4032 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.788549 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 91.058036 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 102031 # number of writebacks -system.cpu1.dcache.writebacks::total 102031 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180109 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 180109 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 273076 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 273076 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 765 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 453185 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 453185 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 453185 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 453185 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 108656 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 108656 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57473 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57473 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6725 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6725 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4282 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 4282 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 166129 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 166129 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 166129 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 166129 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1328748500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1328748500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1211037987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1211037987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54734500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54734500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 40806500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 40806500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539786487 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2539786487 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539786487 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2539786487 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 686558000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 686558000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717533000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717533000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047272 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047272 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123110 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123110 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085561 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085561 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043441 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043441 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12228.947320 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12228.947320 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21071.424617 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21071.424617 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8138.959108 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8138.959108 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9529.775806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9529.775806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 122264 # number of writebacks +system.cpu1.dcache.writebacks::total 122264 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 218997 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 218997 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 293003 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 293003 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 737 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 737 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 512000 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 512000 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 512000 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 512000 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 126578 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 126578 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 66480 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 66480 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9644 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9644 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6325 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6325 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 193058 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 193058 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 193058 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 193058 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1500682500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1500682500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1627145493 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1627145493 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75395000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75395000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33822500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33822500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3127827993 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3127827993 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3127827993 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3127827993 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18098500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18098500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718992500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718992500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737091000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737091000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049398 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049398 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037121 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037121 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.142490 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.142490 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100853 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100853 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044347 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044347 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044347 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044347 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11855.792476 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11855.792476 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24475.714395 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24475.714395 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7817.814185 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.814185 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5347.430830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5347.430830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16201.493815 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16201.493815 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16201.493815 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16201.493815 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1581,170 +1738,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6652 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 169834 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 59752 40.24% 40.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.32% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.30% 41.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 283 0.19% 41.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 86412 58.19% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 148505 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 58939 49.14% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.61% 50.86% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 283 0.24% 51.09% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 58656 48.91% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 119936 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864736682500 98.02% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62604500 0.00% 98.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 575436000 0.03% 98.06% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 137989000 0.01% 98.06% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 36850597000 1.94% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1902363309000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986394 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6891 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 160705 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55206 40.22% 40.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 141 0.10% 40.32% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.40% 41.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 459 0.33% 42.06% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 79532 57.94% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 137263 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 54744 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 141 0.13% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.73% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 459 0.41% 51.34% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54290 48.66% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 111559 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864428350500 98.20% 98.20% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 66694000 0.00% 98.20% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571257500 0.03% 98.23% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 222612500 0.01% 98.25% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 33310195000 1.75% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1898599109500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991631 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.678795 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.807623 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed -system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed -system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed -system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed -system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed -system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed -system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed -system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed -system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed -system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed -system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed -system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed -system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 178 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.682618 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812739 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 383 0.25% 0.25% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3188 2.04% 2.29% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.32% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed -system.cpu0.kern.callpal::swpipl 141921 90.80% 93.12% # number of callpals executed -system.cpu0.kern.callpal::rdps 6055 3.87% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 97.00% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed -system.cpu0.kern.callpal::rti 4242 2.71% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 315 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 156308 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6637 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches +system.cpu0.kern.callpal::wripir 540 0.37% 0.37% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2997 2.06% 2.43% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.04% 2.47% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.47% # number of callpals executed +system.cpu0.kern.callpal::swpipl 130488 89.67% 92.14% # number of callpals executed +system.cpu0.kern.callpal::rdps 6655 4.57% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::rti 4254 2.92% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 145528 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6813 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1098 -system.cpu0.kern.mode_good::user 1098 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.165436 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.188170 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.283904 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1900423407500 99.92% 99.92% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1609733000 0.08% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.316739 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1896637292000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1952797500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3189 # number of times the context was actually changed +system.cpu0.kern.swap_context 2998 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2560 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 70963 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 22970 38.17% 38.17% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 3.20% 41.37% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 383 0.64% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 34900 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 60178 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 22406 47.94% 47.94% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 4.12% 52.06% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 383 0.82% 52.88% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 22023 47.12% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 46737 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874192202500 98.50% 98.50% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532510000 0.03% 98.53% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 178162000 0.01% 98.54% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 27779026000 1.46% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1902681900500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.975446 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2640 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 82284 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 28208 38.75% 38.75% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 2.64% 41.39% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 540 0.74% 42.13% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 42124 57.87% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 72796 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 27293 48.30% 48.30% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 3.40% 51.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 540 0.96% 52.66% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26753 47.34% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 56510 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872083396500 98.59% 98.59% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532362500 0.03% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 246280000 0.01% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 26091314000 1.37% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1898953353000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967562 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.631032 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.776646 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed -system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed -system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed -system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed -system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed -system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed -system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed -system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed -system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed -system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 148 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.635101 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.776279 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 283 0.45% 0.45% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1593 2.54% 3.00% # number of callpals executed -system.cpu1.kern.callpal::tbi 5 0.01% 3.00% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.01% # number of callpals executed -system.cpu1.kern.callpal::swpipl 54358 86.66% 89.67% # number of callpals executed -system.cpu1.kern.callpal::rdps 2709 4.32% 93.99% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.99% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 94.00% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 94.00% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.01% # number of callpals executed -system.cpu1.kern.callpal::rti 3511 5.60% 99.60% # number of callpals executed -system.cpu1.kern.callpal::callsys 200 0.32% 99.92% # number of callpals executed -system.cpu1.kern.callpal::imb 48 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 459 0.61% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2146 2.85% 3.47% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.47% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.48% # number of callpals executed +system.cpu1.kern.callpal::swpipl 66489 88.37% 91.85% # number of callpals executed +system.cpu1.kern.callpal::rdps 2102 2.79% 94.64% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.64% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.65% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.65% # number of callpals executed +system.cpu1.kern.callpal::rti 3842 5.11% 99.76% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 62728 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1948 # number of protection mode switches -system.cpu1.kern.mode_switch::user 639 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2607 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 948 -system.cpu1.kern.mode_good::user 639 -system.cpu1.kern.mode_good::idle 309 -system.cpu1.kern.mode_switch_good::kernel 0.486653 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 75240 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2162 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2922 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 928 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 464 +system.cpu1.kern.mode_switch_good::kernel 0.429232 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.118527 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.365037 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6500961500 0.34% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1047066000 0.06% 0.40% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1895133865000 99.60% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1594 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.158795 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334535 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 8174267000 0.43% 0.43% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 802919500 0.04% 0.47% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1889976158500 99.53% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2147 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 76f868d7e..135d2aacf 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.855236 # Number of seconds simulated -sim_ticks 1855236450500 # Number of ticks simulated -final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854370 # Number of seconds simulated +sim_ticks 1854370484500 # Number of ticks simulated +final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182093 # Simulator instruction rate (inst/s) -host_op_rate 182093 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6374280472 # Simulator tick rate (ticks/s) -host_mem_usage 298212 # Number of bytes of host memory used -host_seconds 291.05 # Real time elapsed on the host -sim_insts 52998368 # Number of instructions simulated -sim_ops 52998368 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory -system.physmem.bytes_written::total 7522688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445360 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117542 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 94446 # Simulator instruction rate (inst/s) +host_op_rate 94446 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3304859837 # Simulator tick rate (ticks/s) +host_mem_usage 326668 # Number of bytes of host memory used +host_seconds 561.10 # Real time elapsed on the host +sim_insts 52993965 # Number of instructions simulated +sim_ops 52993965 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7507712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7507712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388692 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445277 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117308 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117308 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 522597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13414950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15367872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 522597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 522597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 522597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13414950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19416530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445277 # Total number of read requests seen +system.physmem.writeReqs 117308 # Total number of write requests seen +system.physmem.cpureqs 564090 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28497728 # Total number of bytes read from memory +system.physmem.bytesWritten 7507712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28497728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7507712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28080 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27911 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28123 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27918 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27747 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27734 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7101 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7583 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7380 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7215 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6854 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7671 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7427 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7315 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7174 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854365055000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 445277 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 118080 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 175 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 331917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 3912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 6175508423 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13385774423 # Sum of mem lat for all requests +system.physmem.totBusLat 1780884000 # Total cycles spent in databus access +system.physmem.totBankLat 5429382000 # Total cycles spent in bank access +system.physmem.avgQLat 13870.66 # Average queueing delay per request +system.physmem.avgBankLat 12194.80 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30065.46 # Average memory access latency +system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgWrQLen 10.01 # Average write queue length over time +system.physmem.readRowHits 425232 # Number of row buffer hits during reads +system.physmem.writeRowHits 76485 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.20 # Row buffer hit rate for writes +system.physmem.avgGap 3296150.90 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255779 # Cycle average of tags in use +system.iocache.tagsinuse 1.265505 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704471567000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265505 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079094 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079094 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -55,14 +213,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 20930998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20930998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9501230806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9501230806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9522161804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9522161804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9522161804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9522161804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -79,19 +237,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120988.427746 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120988.427746 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228658.808385 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228658.808385 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228212.385956 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228212.385956 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 190847 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22837 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.356921 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -105,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11934000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11934000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338470481 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7338470481 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7350404481 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7350404481 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7350404481 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7350404481 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -121,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68982.658960 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68982.658960 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176609.320394 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176609.320394 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -146,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9942716 # DTB read hits -system.cpu.dtb.read_misses 44791 # DTB read misses -system.cpu.dtb.read_acv 565 # DTB read access violations -system.cpu.dtb.read_accesses 947396 # DTB read accesses -system.cpu.dtb.write_hits 6623666 # DTB write hits -system.cpu.dtb.write_misses 10259 # DTB write misses -system.cpu.dtb.write_acv 393 # DTB write access violations -system.cpu.dtb.write_accesses 338396 # DTB write accesses -system.cpu.dtb.data_hits 16566382 # DTB hits -system.cpu.dtb.data_misses 55050 # DTB misses -system.cpu.dtb.data_acv 958 # DTB access violations -system.cpu.dtb.data_accesses 1285792 # DTB accesses -system.cpu.itb.fetch_hits 1328947 # ITB hits -system.cpu.itb.fetch_misses 38142 # ITB misses -system.cpu.itb.fetch_acv 1080 # ITB acv -system.cpu.itb.fetch_accesses 1367089 # ITB accesses +system.cpu.dtb.read_hits 10013236 # DTB read hits +system.cpu.dtb.read_misses 44959 # DTB read misses +system.cpu.dtb.read_acv 558 # DTB read access violations +system.cpu.dtb.read_accesses 947796 # DTB read accesses +system.cpu.dtb.write_hits 6616814 # DTB write hits +system.cpu.dtb.write_misses 10390 # DTB write misses +system.cpu.dtb.write_acv 394 # DTB write access violations +system.cpu.dtb.write_accesses 338465 # DTB write accesses +system.cpu.dtb.data_hits 16630050 # DTB hits +system.cpu.dtb.data_misses 55349 # DTB misses +system.cpu.dtb.data_acv 952 # DTB access violations +system.cpu.dtb.data_accesses 1286261 # DTB accesses +system.cpu.itb.fetch_hits 1329992 # ITB hits +system.cpu.itb.fetch_misses 37108 # ITB misses +system.cpu.itb.fetch_acv 1110 # ITB acv +system.cpu.itb.fetch_accesses 1367100 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -174,277 +332,277 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 112948398 # number of cpu cycles simulated +system.cpu.numCycles 109331520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 13966796 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits +system.cpu.BPredUnit.lookups 14034298 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11727409 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 442398 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10070774 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5936443 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37395096 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81356871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67855364 83.40% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12232048 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11473805 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81356871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37116939 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19830183 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80190207 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479545 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38187514 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6228893 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1695379 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 248206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12171415 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10595299 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6961029 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1313529 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81356871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56509821 69.46% 69.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81356871 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 375615 47.50% 58.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326165 41.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38947584 68.15% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61688 0.11% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57074473 # Type of FU issued -system.cpu.iq.rate 0.505315 # Inst issue rate -system.cpu.iq.fu_busy_cnt 789329 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued +system.cpu.iq.rate 0.522738 # Inst issue rate +system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195876832 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1500833 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3663 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13623 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 580148 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17973 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 208284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1354175 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9957840 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684465 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64406962 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 718774 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10595299 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6961029 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1833098 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512595 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19043 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13623 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 239398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 420347 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 659745 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56634449 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10087078 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 517300 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3555305 # number of nop insts executed -system.cpu.iew.exec_refs 16665522 # number of memory reference insts executed -system.cpu.iew.exec_branches 8969939 # Number of branches executed -system.cpu.iew.exec_stores 6649129 # Number of stores executed -system.cpu.iew.exec_rate 0.500679 # Inst execution rate -system.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56121532 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27804186 # num instructions producing a value -system.cpu.iew.wb_consumers 37617732 # num instructions consuming a value +system.cpu.iew.exec_nop 3558099 # number of nop insts executed +system.cpu.iew.exec_refs 16729501 # number of memory reference insts executed +system.cpu.iew.exec_branches 8966109 # Number of branches executed +system.cpu.iew.exec_stores 6642423 # Number of stores executed +system.cpu.iew.exec_rate 0.518007 # Inst execution rate +system.cpu.iew.wb_sent 56249945 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56126682 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27860065 # num instructions producing a value +system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.496878 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back +system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80002696 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59120918 73.90% 73.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56188905 # Number of instructions committed -system.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80002696 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56184240 # Number of instructions committed +system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15476867 # Number of memory references committed -system.cpu.commit.loads 9095415 # Number of loads committed -system.cpu.commit.membars 226300 # Number of memory barriers committed -system.cpu.commit.branches 8447820 # Number of branches committed +system.cpu.commit.refs 15475347 # Number of memory references committed +system.cpu.commit.loads 9094466 # Number of loads committed +system.cpu.commit.membars 226347 # Number of memory barriers committed +system.cpu.commit.branches 8447798 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52034961 # Number of committed integer instructions. -system.cpu.commit.function_calls 740468 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52030338 # Number of committed integer instructions. +system.cpu.commit.function_calls 740415 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141682968 # The number of ROB reads -system.cpu.rob.rob_writes 129465441 # The number of ROB writes -system.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52998368 # Number of Instructions Simulated -system.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52998368 # Number of Instructions Simulated -system.cpu.cpi 2.131167 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads -system.cpu.ipc 0.469226 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74144483 # number of integer regfile reads -system.cpu.int_regfile_writes 40484328 # number of integer regfile writes -system.cpu.fp_regfile_reads 165992 # number of floating regfile reads -system.cpu.fp_regfile_writes 167427 # number of floating regfile writes -system.cpu.misc_regfile_reads 1993361 # number of misc regfile reads -system.cpu.misc_regfile_writes 946826 # number of misc regfile writes +system.cpu.rob.rob_reads 142220967 # The number of ROB reads +system.cpu.rob.rob_writes 129940455 # The number of ROB writes +system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27974649 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52993965 # Number of Instructions Simulated +system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated +system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads +system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74218754 # number of integer regfile reads +system.cpu.int_regfile_writes 40498790 # number of integer regfile writes +system.cpu.fp_regfile_reads 166070 # number of floating regfile reads +system.cpu.fp_regfile_writes 167447 # number of floating regfile writes +system.cpu.misc_regfile_reads 1994018 # number of misc regfile reads +system.cpu.misc_regfile_writes 947042 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -476,245 +634,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1020348 # number of replacements -system.cpu.icache.tagsinuse 510.019758 # Cycle average of tags in use -system.cpu.icache.total_refs 7661720 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1020856 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.505192 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 22969954000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.019758 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996132 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996132 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7661721 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7661721 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7661721 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7661721 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7661721 # number of overall hits -system.cpu.icache.overall_hits::total 7661721 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1079749 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079749 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1079749 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079749 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1079749 # number of overall misses -system.cpu.icache.overall_misses::total 1079749 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14523691994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14523691994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14523691994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14523691994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14523691994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14523691994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8741470 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8741470 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8741470 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8741470 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8741470 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8741470 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123520 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123520 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123520 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123520 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.replacements 1020188 # number of replacements +system.cpu.icache.tagsinuse 510.304097 # Cycle average of tags in use +system.cpu.icache.total_refs 7717774 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1020696 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.561286 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20124452000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.304097 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996688 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7717775 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7717775 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7717775 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7717775 # 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miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107836 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246054 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.547949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.547949 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27863.529126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27863.529126 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2571682 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946948 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks -system.cpu.dcache.writebacks::total 841878 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712313 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 712313 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642186 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642186 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5152 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048840 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048840 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083809 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083809 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 841139 # number of writebacks +system.cpu.dcache.writebacks::total 841139 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716695 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 716695 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1641513 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1641513 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5045 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5045 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2358208 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2358208 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2358208 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2358208 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084739 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084739 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300217 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300217 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17950 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17950 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384956 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384956 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384956 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712390769 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712390769 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907863269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31907863269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907863269 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31907863269 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997718998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997718998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421626998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421626998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048843 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084177 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084177 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091039 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.159135 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.159135 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -722,105 +880,109 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 338417 # number of replacements -system.cpu.l2cache.tagsinuse 65352.111585 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2559541 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403585 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.342012 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4707423000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 53923.419199 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 5354.651362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6074.041024 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.822806 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.081705 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092683 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997194 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 1005811 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 828504 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1834315 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 841878 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 841878 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.replacements 338360 # number of replacements +system.cpu.l2cache.tagsinuse 65364.997376 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2558215 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 53963.120653 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.081638 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.092341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997391 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1005648 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 828171 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1833819 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 841139 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 841139 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185452 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185452 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067951103 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067951103 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327873464 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16052895904 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327873464 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16052895904 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331389500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331389500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1881061000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1881061000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212450500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212450500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383388 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.166828 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.178458 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.178458 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -903,28 +1073,28 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211013 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105569 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818451122500 98.06% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64044500 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561305000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35293166500 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854369638500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694295 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -963,29 +1133,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175126 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191902 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.callpal::total 191972 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches system.cpu.kern.mode_good::kernel 1909 system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29748704000 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2690261500 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1821930665000 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 955cfdbb2..f1db1c28b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,212 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534173 # Number of seconds simulated -sim_ticks 2534173219000 # Number of ticks simulated -final_tick 2534173219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523636 # Number of seconds simulated +sim_ticks 2523635852000 # Number of ticks simulated +final_tick 2523635852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58476 # Simulator instruction rate (inst/s) -host_op_rate 75217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2445371941 # Simulator tick rate (ticks/s) -host_mem_usage 386340 # Number of bytes of host memory used -host_seconds 1036.31 # Real time elapsed on the host -sim_insts 60599410 # Number of instructions simulated -sim_ops 77948210 # Number of ops (including micro ops) simulated +host_inst_rate 60184 # Simulator instruction rate (inst/s) +host_op_rate 77414 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2506430956 # Simulator tick rate (ticks/s) +host_mem_usage 399764 # Number of bytes of host memory used +host_seconds 1006.86 # Real time elapsed on the host +sim_insts 60597347 # Number of instructions simulated +sim_ops 77945524 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3584 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9096016 # Number of bytes read from this memory -system.physmem.bytes_read::total 129435344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory +system.physmem.bytes_read::total 129436368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 56 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12470 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142159 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096893 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12490 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096909 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47170281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1389 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47367240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1420 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314927 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51075966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314927 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314927 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493669 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190160 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683829 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47170281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3604203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51289637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47367240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1420 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4779503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53759795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4799333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53983912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096909 # Total number of read requests seen +system.physmem.writeReqs 813132 # Total number of write requests seen +system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966202176 # Total number of bytes read from memory +system.physmem.bytesWritten 52040448 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129436368 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 363 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943955 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943427 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943111 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943293 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50098 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50033 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50667 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51122 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51107 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51028 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 1156323 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523634566000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 36 # Categorize read packet sizes +system.physmem.readPktSize::3 14942208 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 154665 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 1910341 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 59114 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 14955787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 2806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 46870409147 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317530293147 # Sum of mem lat for all requests +system.physmem.totBusLat 60386184000 # Total cycles spent in databus access +system.physmem.totBankLat 210273700000 # Total cycles spent in bank access +system.physmem.avgQLat 3104.71 # Average queueing delay per request +system.physmem.avgBankLat 13928.60 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 21033.31 # Average memory access latency +system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.52 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.avgWrQLen 12.37 # Average write queue length over time +system.physmem.readRowHits 15050555 # Number of row buffer hits during reads +system.physmem.writeRowHits 784512 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.48 # Row buffer hit rate for writes +system.physmem.avgGap 158618.99 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -69,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15049590 # DTB read hits -system.cpu.checker.dtb.read_misses 7303 # DTB read misses -system.cpu.checker.dtb.write_hits 11294593 # DTB write hits +system.cpu.checker.dtb.read_hits 15048983 # DTB read hits +system.cpu.checker.dtb.read_misses 7307 # DTB read misses +system.cpu.checker.dtb.write_hits 11294245 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -82,13 +240,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056893 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296782 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056290 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296434 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26344183 # DTB hits -system.cpu.checker.dtb.misses 9492 # DTB misses -system.cpu.checker.dtb.accesses 26353675 # DTB accesses -system.cpu.checker.itb.inst_hits 61778177 # ITB inst hits +system.cpu.checker.dtb.hits 26343228 # DTB hits +system.cpu.checker.dtb.misses 9496 # DTB misses +system.cpu.checker.dtb.accesses 26352724 # DTB accesses +system.cpu.checker.itb.inst_hits 61776100 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -105,36 +263,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61782648 # ITB inst accesses -system.cpu.checker.itb.hits 61778177 # DTB hits +system.cpu.checker.itb.inst_accesses 61780571 # ITB inst accesses +system.cpu.checker.itb.hits 61776100 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61782648 # DTB accesses -system.cpu.checker.numCycles 78238784 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61780571 # DTB accesses +system.cpu.checker.numCycles 78236084 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51719750 # DTB read hits -system.cpu.dtb.read_misses 77229 # DTB read misses -system.cpu.dtb.write_hits 11809411 # DTB write hits -system.cpu.dtb.write_misses 17373 # DTB write misses +system.cpu.dtb.read_hits 51390867 # DTB read hits +system.cpu.dtb.read_misses 77330 # DTB read misses +system.cpu.dtb.write_hits 11807590 # DTB write hits +system.cpu.dtb.write_misses 17145 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7767 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2639 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7744 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2913 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 528 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1315 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51796979 # DTB read accesses -system.cpu.dtb.write_accesses 11826784 # DTB write accesses +system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51468197 # DTB read accesses +system.cpu.dtb.write_accesses 11824735 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63529161 # DTB hits -system.cpu.dtb.misses 94602 # DTB misses -system.cpu.dtb.accesses 63623763 # DTB accesses -system.cpu.itb.inst_hits 13045523 # ITB inst hits -system.cpu.itb.inst_misses 12142 # ITB inst misses +system.cpu.dtb.hits 63198457 # DTB hits +system.cpu.dtb.misses 94475 # DTB misses +system.cpu.dtb.accesses 63292932 # DTB accesses +system.cpu.itb.inst_hits 11866859 # ITB inst hits +system.cpu.itb.inst_misses 12387 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -143,538 +301,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5168 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5196 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3109 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3124 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13057665 # ITB inst accesses -system.cpu.itb.hits 13045523 # DTB hits -system.cpu.itb.misses 12142 # DTB misses -system.cpu.itb.accesses 13057665 # DTB accesses -system.cpu.numCycles 475815628 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11879246 # ITB inst accesses +system.cpu.itb.hits 11866859 # DTB hits +system.cpu.itb.misses 12387 # DTB misses +system.cpu.itb.accesses 11879246 # DTB accesses +system.cpu.numCycles 471620131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15155227 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12146705 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783529 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10394615 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8308125 # Number of BTB hits +system.cpu.BPredUnit.lookups 14707897 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11700483 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783548 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9751137 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7864369 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454278 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82490 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31347726 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 100822937 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15155227 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9762403 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22167713 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5923551 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 130252 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97680521 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2843 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 98238 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209120 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13041690 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1002552 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6432 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155704074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.799073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.166371 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1453661 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82859 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 30173854 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 91943847 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14707897 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9318030 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20602156 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4980521 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 134933 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96636325 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2675 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 101652 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208965 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11862984 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 731347 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6597 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151294412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.758755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.115735 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133553129 85.77% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1381799 0.89% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755926 1.13% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2652519 1.70% 89.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2328486 1.50% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1136180 0.73% 91.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2905092 1.87% 93.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 785179 0.50% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9205764 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130709145 86.39% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1380335 0.91% 87.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1756131 1.16% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2339631 1.55% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2142384 1.42% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1132136 0.75% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2619139 1.73% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 785245 0.52% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8430266 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155704074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031851 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.211895 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33480524 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 97304946 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19992509 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1030333 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3895762 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2022425 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174533 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 117498058 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576273 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3895762 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35565671 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37584641 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53601603 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18869314 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6187083 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110088875 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21357 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1014287 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4146063 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 32391 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 114923514 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 504161217 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 504070393 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78734130 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36189383 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892416 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 798033 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12508562 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20972747 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13834973 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1961849 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2465756 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 100830951 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058696 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126177528 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24329335 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 64639752 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514100 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155704074 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.810368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523012 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151294412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.194953 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32008731 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96268896 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18723702 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1031258 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3261825 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2020367 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174818 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 109258714 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3261825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33805354 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36852775 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53319596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17901114 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6153748 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 104067610 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21499 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015662 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4122290 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31949 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 107816884 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 475027641 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 474936857 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90784 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78731329 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 29085554 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891358 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 796895 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12333147 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20062338 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13521403 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1975115 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2433562 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 96511960 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2056994 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123962105 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189941 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20009013 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 50083503 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 512489 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151294412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.531574 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 110503842 70.97% 70.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14006844 9.00% 79.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7305691 4.69% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6085046 3.91% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12721239 8.17% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2798387 1.80% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1680857 1.08% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 475213 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126955 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106913550 70.67% 70.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13863924 9.16% 79.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7098415 4.69% 84.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5869010 3.88% 88.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12472838 8.24% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2771623 1.83% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1718676 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 458210 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128166 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155704074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151294412 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57592 0.65% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370496 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418270 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 56852 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8372882 94.63% 95.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 417861 4.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59895243 47.47% 47.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95317 0.08% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 7 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53367566 42.30% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12453578 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58285332 47.02% 47.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95139 0.08% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52764596 42.57% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12451206 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126177528 # Type of FU issued -system.cpu.iq.rate 0.265182 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8846360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070110 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417165828 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127235505 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87177257 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23405 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134647760 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12462 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624931 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123962105 # Type of FU issued +system.cpu.iq.rate 0.262843 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8847599 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071373 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 408327002 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118594240 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86288141 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23234 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12518 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10286 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132433714 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12324 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 628913 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5256081 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7285 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30200 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2036035 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4346263 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7649 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29949 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1722835 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34106907 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1030049 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107855 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695994 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3895762 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28674144 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 449674 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103114750 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 233495 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20972747 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13834973 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466916 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113563 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3765 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30200 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 409921 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 292907 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 702828 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122963273 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52407414 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3214255 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3261825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27934565 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 435305 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98793776 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 231675 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20062338 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13521403 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1465659 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113955 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3708 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29949 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409673 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293589 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 703262 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121754884 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52078341 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2207221 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 225103 # number of nop insts executed -system.cpu.iew.exec_refs 64729141 # number of memory reference insts executed -system.cpu.iew.exec_branches 11726228 # Number of branches executed -system.cpu.iew.exec_stores 12321727 # Number of stores executed -system.cpu.iew.exec_rate 0.258426 # Inst execution rate -system.cpu.iew.wb_sent 121618308 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87187548 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47710631 # num instructions producing a value -system.cpu.iew.wb_consumers 88857501 # num instructions consuming a value +system.cpu.iew.exec_nop 224822 # number of nop insts executed +system.cpu.iew.exec_refs 64398044 # number of memory reference insts executed +system.cpu.iew.exec_branches 11600510 # Number of branches executed +system.cpu.iew.exec_stores 12319703 # Number of stores executed +system.cpu.iew.exec_rate 0.258163 # Inst execution rate +system.cpu.iew.wb_sent 120731241 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86298427 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47352499 # num instructions producing a value +system.cpu.iew.wb_consumers 88423671 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183238 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182983 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535518 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24186815 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544596 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612016 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151890748 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.495245 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19868331 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544505 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 611839 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148115015 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.527265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.512607 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 124092082 81.70% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13579714 8.94% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3980091 2.62% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2134436 1.41% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949184 1.28% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1000796 0.66% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1579621 1.04% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 721647 0.48% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2853177 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120340532 81.25% 81.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13566988 9.16% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3964696 2.68% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2137699 1.44% 94.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1955021 1.32% 95.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 974024 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1590640 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 730936 0.49% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2854479 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151890748 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60749791 # Number of instructions committed -system.cpu.commit.committedOps 78098591 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148115015 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747728 # Number of instructions committed +system.cpu.commit.committedOps 78095905 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27515604 # Number of memory references committed -system.cpu.commit.loads 15716666 # Number of loads committed -system.cpu.commit.membars 413138 # Number of memory barriers committed -system.cpu.commit.branches 10023383 # Number of branches committed +system.cpu.commit.refs 27514643 # Number of memory references committed +system.cpu.commit.loads 15716075 # Number of loads committed +system.cpu.commit.membars 413107 # Number of memory barriers committed +system.cpu.commit.branches 10023098 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69136784 # Number of committed integer instructions. -system.cpu.commit.function_calls 996034 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2853177 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69134339 # Number of committed integer instructions. +system.cpu.commit.function_calls 995983 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2854479 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249407638 # The number of ROB reads -system.cpu.rob.rob_writes 208557399 # The number of ROB writes -system.cpu.timesIdled 1773714 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320111554 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592442776 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60599410 # Number of Instructions Simulated -system.cpu.committedOps 77948210 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60599410 # Number of Instructions Simulated -system.cpu.cpi 7.851819 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.851819 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127359 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127359 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556670721 # number of integer regfile reads -system.cpu.int_regfile_writes 89963166 # number of integer regfile writes -system.cpu.fp_regfile_reads 8373 # number of floating regfile reads -system.cpu.fp_regfile_writes 2910 # number of floating regfile writes -system.cpu.misc_regfile_reads 132949410 # number of misc regfile reads -system.cpu.misc_regfile_writes 912934 # number of misc regfile writes -system.cpu.icache.replacements 989799 # number of replacements -system.cpu.icache.tagsinuse 511.593898 # Cycle average of tags in use -system.cpu.icache.total_refs 11967809 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990311 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.084900 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.593898 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11967809 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11967809 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11967809 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11967809 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11967809 # number of overall hits -system.cpu.icache.overall_hits::total 11967809 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1073749 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1073749 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1073749 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1073749 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1073749 # number of overall misses -system.cpu.icache.overall_misses::total 1073749 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14109467991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14109467991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14109467991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14109467991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14109467991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14109467991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13041558 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13041558 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13041558 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13041558 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13041558 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13041558 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082333 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082333 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082333 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082333 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082333 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082333 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13140.378236 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13140.378236 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13140.378236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13140.378236 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4599 # number of cycles access was blocked +system.cpu.rob.rob_reads 241309637 # The number of ROB reads +system.cpu.rob.rob_writes 199282329 # The number of ROB writes +system.cpu.timesIdled 1774359 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320325719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575563546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60597347 # Number of Instructions Simulated +system.cpu.committedOps 77945524 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60597347 # Number of Instructions Simulated +system.cpu.cpi 7.782851 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.782851 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 551501620 # number of integer regfile reads +system.cpu.int_regfile_writes 88408652 # number of integer regfile writes +system.cpu.fp_regfile_reads 8346 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 124084349 # number of misc regfile reads +system.cpu.misc_regfile_writes 912885 # number of misc regfile writes +system.cpu.icache.replacements 990639 # number of replacements +system.cpu.icache.tagsinuse 510.412932 # Cycle average of tags in use +system.cpu.icache.total_refs 10788740 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991151 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.885062 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.412932 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996900 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996900 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10788740 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10788740 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10788740 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10788740 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10788740 # number of overall hits +system.cpu.icache.overall_hits::total 10788740 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1074113 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1074113 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1074113 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1074113 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13142.730316 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13142.730316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.730316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13142.730316 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4157 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 287 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.029412 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 14.484321 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82910 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 82910 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 82910 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 82910 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 82910 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 82910 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991203 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7052500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7052500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7052500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7052500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.083555 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.083555 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.083555 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.083555 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.083555 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.083555 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11567.158784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11567.158784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11567.158784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11567.158784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11567.158784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11567.158784 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # 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number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7288115 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 284783 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 284783 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21214420 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21214420 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21214420 # number of overall hits -system.cpu.dcache.overall_hits::total 21214420 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 727409 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 727409 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962946 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962946 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13565 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13565 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3690355 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3690355 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3690355 # number of overall misses -system.cpu.dcache.overall_misses::total 3690355 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441109500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9441109500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104189875245 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104189875245 # 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Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35202000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994184 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13909872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13909872 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7289107 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7289107 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284200 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284200 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285733 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285733 # 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number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113952343741 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113952343741 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113952343741 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113952343741 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14639302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14639302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250721 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250721 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297775 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297775 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285750 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285750 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24890023 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24890023 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24890023 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24890023 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049827 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049827 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288918 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288918 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045588 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045588 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000059 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000059 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148294 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148294 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148294 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148294 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.338388 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.338388 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35257.523851 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35257.523851 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13353.370166 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13353.370166 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30872.659264 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30872.659264 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30872.659264 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30872.659264 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29185 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15466 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2496 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.692708 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.130435 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609382 # number of writebacks -system.cpu.dcache.writebacks::total 609382 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339956 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 339956 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713832 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713832 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1350 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1350 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3053788 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3053788 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3053788 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3053788 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387453 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387453 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249114 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249114 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12215 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12215 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636567 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636567 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636567 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4759977000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4759977000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8542104919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8542104919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141597500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141597500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 288500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 288500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13302081919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13302081919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13302081919 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13302081919 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356244500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356244500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41726674069 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41726674069 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224082918569 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224082918569 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024301 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024301 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040942 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040942 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000052 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025560 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025560 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025560 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025560 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12285.301701 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12285.301701 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.943235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.943235 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11592.099877 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11592.099877 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19233.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19233.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609134 # number of writebacks +system.cpu.dcache.writebacks::total 609134 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 342186 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 342186 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712531 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2712531 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1353 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1353 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3054717 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3054717 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3054717 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3054717 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387244 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387244 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249083 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249083 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12222 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12222 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636327 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636327 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636327 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636327 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4781960500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781960500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152753421 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152753421 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142066000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142066000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12934713921 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12934713921 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12934713921 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12934713921 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182355760000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182355760000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28006419847 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28006419847 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210362179847 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210362179847 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026452 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026452 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024299 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024299 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041044 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041044 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000059 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025566 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025566 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025566 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025566 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.701336 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.701336 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32731.071253 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32731.071253 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11623.793160 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11623.793160 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20327.149282 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20327.149282 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20327.149282 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20327.149282 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -682,149 +840,149 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64413 # number of replacements -system.cpu.l2cache.tagsinuse 51352.307141 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1928116 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129809 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.853485 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498979146000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36881.759655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 43.531667 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8178.474419 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6248.541162 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.562771 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000664 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64431 # number of replacements +system.cpu.l2cache.tagsinuse 51361.955976 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1930789 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129828 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40979.476225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42280.789844 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41609.810573 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10006.448382 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.448382 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37908.793347 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37908.793347 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38455.716975 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38455.716975 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -959,16 +1117,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1202929249396 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1202929249396 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068189786972 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068189786972 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88028 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 6d0b522dc..50e1ba197 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,71 +1,229 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603785 # Number of seconds simulated -sim_ticks 2603784540500 # Number of ticks simulated -final_tick 2603784540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.003417 # Number of seconds simulated +sim_ticks 1003417221500 # Number of ticks simulated +final_tick 1003417221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66983 # Simulator instruction rate (inst/s) -host_op_rate 86203 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2766471262 # Simulator tick rate (ticks/s) -host_mem_usage 391460 # Number of bytes of host memory used -host_seconds 941.19 # Real time elapsed on the host -sim_insts 63043892 # Number of instructions simulated -sim_ops 81133946 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +host_inst_rate 74785 # Simulator instruction rate (inst/s) +host_op_rate 96230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1214309093 # Simulator tick rate (ticks/s) +host_mem_usage 406952 # Number of bytes of host memory used +host_seconds 826.33 # Real time elapsed on the host +sim_insts 61797296 # Number of instructions simulated +sim_ops 79517775 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 44040192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 398208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4365108 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 424768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5242032 # Number of bytes read from this memory -system.physmem.bytes_read::total 131542884 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 398208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 424768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4259200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 410432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4376692 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 404672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5217200 # Number of bytes read from this memory +system.physmem.bytes_read::total 54451236 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 410432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 404672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4253056 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7288336 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7280144 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 5505024 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6222 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6637 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81933 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301920 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66550 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6323 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81545 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5667795 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66454 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823834 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46513268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 152934 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1676447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2013236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50519881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 152934 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1635773 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2799132 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1635773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46513268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 152934 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1682976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3170066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53319012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823226 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43890209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 409034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4361787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 403294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5199432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54265798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 409034 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 403294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4238572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 16942 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2999837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7255351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4238572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43890209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 409034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4378729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 403294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 8199269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 61521149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5667795 # Total number of read requests seen +system.physmem.writeReqs 823226 # Total number of write requests seen +system.physmem.cpureqs 281286 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 362738880 # Total number of bytes read from memory +system.physmem.bytesWritten 52686464 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 54451236 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7280144 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 148 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12596 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 354151 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 354519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 354412 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 354404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 354227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 354027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 353803 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 353914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 354718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 354198 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 354245 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 354391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 354136 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 354309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 354144 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 354049 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50660 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50996 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50931 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51753 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51624 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51424 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51487 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51682 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51566 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51627 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51620 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51624 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51572 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 1152068 # Number of times wr buffer was full causing retry +system.physmem.totGap 1003416092000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 105 # Categorize read packet sizes +system.physmem.readPktSize::3 5505024 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 162666 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 1908840 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 66454 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 12596 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 5540802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 75454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 3176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 46980948909 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 148397952909 # Sum of mem lat for all requests +system.physmem.totBusLat 22670588000 # Total cycles spent in databus access +system.physmem.totBankLat 78746416000 # Total cycles spent in bank access +system.physmem.avgQLat 8289.32 # Average queueing delay per request +system.physmem.avgBankLat 13894.02 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26183.34 # Average memory access latency +system.physmem.avgRdBW 361.50 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 52.51 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 54.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 7.26 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.59 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 11.87 # Average write queue length over time +system.physmem.readRowHits 5638305 # Number of row buffer hits during reads +system.physmem.writeRowHits 788804 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 95.82 # Row buffer hit rate for writes +system.physmem.avgGap 154585.25 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -75,246 +233,246 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72716 # number of replacements -system.l2c.tagsinuse 53054.127627 # Cycle average of tags in use -system.l2c.total_refs 1921007 # Total number of references to valid blocks. -system.l2c.sampled_refs 137887 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.931748 # Average number of references to valid blocks. +system.realview.nvmem.bw_read::cpu0.inst 64 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 383 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 446 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 64 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 383 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 446 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 64 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 383 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 446 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72379 # number of replacements +system.l2c.tagsinuse 54036.280833 # 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number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6278 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 82732 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165118 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 808528 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93002 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 250453593 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 258988799 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 830528 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 264569298 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 278824979 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1054568727 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 52203490 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38107108 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 90310598 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6565141 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4047401 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10612542 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2354972014 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3286542342 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5641514356 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 808528 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 250453593 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2613960813 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 830528 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 264569298 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3565367321 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6696083083 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 808528 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 250453593 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2613960813 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 830528 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 264569298 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3565367321 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6696083083 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4694165 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12372746053 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1876066 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154362129001 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166741445285 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 997094235 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17119323408 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 18116417643 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4694165 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13369840288 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1876066 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171481452409 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184857862928 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000465 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015839 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036423 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000291 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010400 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.029938 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016984 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.820488 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.823672 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.821821 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772137 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.738574 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.758967 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569218 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564317 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566528 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000465 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015839 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245795 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000291 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010400 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.242862 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.096019 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000465 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015839 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245795 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000291 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010400 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.242862 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.096019 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41253.392641 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45448.244336 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42172.627649 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.580595 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10197.245919 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10134.732129 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.441896 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.319307 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10030.758034 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37077.415004 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42906.932935 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.319659 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37453.051352 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43095.384144 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40553.319947 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37453.051352 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43095.384144 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40553.319947 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +665,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9065848 # DTB read hits -system.cpu0.dtb.read_misses 36360 # DTB read misses -system.cpu0.dtb.write_hits 5285915 # DTB write hits -system.cpu0.dtb.write_misses 6625 # DTB write misses +system.cpu0.dtb.read_hits 8990701 # DTB read hits +system.cpu0.dtb.read_misses 35639 # DTB read misses +system.cpu0.dtb.write_hits 5196869 # DTB write hits +system.cpu0.dtb.write_misses 6420 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2165 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 342 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2140 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 358 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9102208 # DTB read accesses -system.cpu0.dtb.write_accesses 5292540 # DTB write accesses +system.cpu0.dtb.perms_faults 552 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9026340 # DTB read accesses +system.cpu0.dtb.write_accesses 5203289 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14351763 # DTB hits -system.cpu0.dtb.misses 42985 # DTB misses -system.cpu0.dtb.accesses 14394748 # DTB accesses -system.cpu0.itb.inst_hits 4413372 # ITB inst hits -system.cpu0.itb.inst_misses 5476 # ITB inst misses +system.cpu0.dtb.hits 14187570 # DTB hits +system.cpu0.dtb.misses 42059 # DTB misses +system.cpu0.dtb.accesses 14229629 # DTB accesses +system.cpu0.itb.inst_hits 4354083 # ITB inst hits +system.cpu0.itb.inst_misses 5531 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -536,538 +694,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1363 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1472 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4418848 # ITB inst accesses -system.cpu0.itb.hits 4413372 # DTB hits -system.cpu0.itb.misses 5476 # DTB misses -system.cpu0.itb.accesses 4418848 # DTB accesses -system.cpu0.numCycles 70012496 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4359614 # ITB inst accesses +system.cpu0.itb.hits 4354083 # DTB hits +system.cpu0.itb.misses 5531 # DTB misses +system.cpu0.itb.accesses 4359614 # DTB accesses +system.cpu0.numCycles 68779590 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6217398 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4733750 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 327130 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 4014715 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3051469 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6151354 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4687077 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 326469 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3738602 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3006788 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 700588 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 31775 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12151517 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33217564 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6217398 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3752057 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7806548 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1581421 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 67728 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 22157211 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 54633 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 92488 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4411708 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 171100 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2593 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 43471985 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.986228 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.366083 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 689169 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 32083 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11912972 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32706056 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6151354 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3695957 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7689921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1565411 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 62995 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21287015 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 56402 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4352320 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 172729 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2628 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42226826 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.000152 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.378860 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35673429 82.06% 82.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 623255 1.43% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 822107 1.89% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 699884 1.61% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 794381 1.83% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 577438 1.33% 90.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 719535 1.66% 91.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 371399 0.85% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3190557 7.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34545116 81.81% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 600326 1.42% 83.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 813270 1.93% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 699242 1.66% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 789636 1.87% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 563805 1.34% 90.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 711205 1.68% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 369975 0.88% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3134251 7.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 43471985 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088804 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.474452 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12679354 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 22114744 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7023055 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 583785 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1071047 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 976895 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 65884 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41430285 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 215511 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1071047 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13270486 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5876098 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14061413 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6963478 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2229463 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40231881 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 440788 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1249784 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 63 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40621534 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 181781749 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 181747462 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34287 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31667723 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8953810 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 461246 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 417498 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5499956 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7912486 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5888217 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1140849 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1237786 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37992607 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 949484 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38225982 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 89034 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6781394 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14357702 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 260797 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 43471985 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.879325 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.495049 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42226826 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.089436 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.475520 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12413850 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21262916 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6920770 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 571279 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1058011 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 957289 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65649 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40810463 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 214284 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1058011 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12995838 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5806909 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13316140 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6858946 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2190982 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39610027 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2116 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435032 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1231897 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 105 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39982485 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 178864927 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178830724 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34203 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31105315 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8877169 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 451261 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 410052 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5376793 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7771036 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5796008 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1117778 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1234382 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37385936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 932152 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37680469 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87348 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6705798 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14225412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 253293 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42226826 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.892335 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27798434 63.95% 63.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6055917 13.93% 77.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3289826 7.57% 85.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2491193 5.73% 91.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2118698 4.87% 96.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 969648 2.23% 98.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 500024 1.15% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 192302 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 55943 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26789201 63.44% 63.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5974229 14.15% 77.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3183905 7.54% 85.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2487856 5.89% 91.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2118052 5.02% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 933005 2.21% 98.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 499456 1.18% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188083 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53039 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 43471985 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42226826 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25214 2.35% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 458 0.04% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 837969 78.03% 80.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 210208 19.58% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25386 2.38% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 456 0.04% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 843676 78.98% 81.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 198710 18.60% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22961950 60.07% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 49879 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 12 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9545903 24.97% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5615312 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22597326 59.97% 60.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48684 0.13% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 696 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9468734 25.13% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5512785 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38225982 # Type of FU issued -system.cpu0.iq.rate 0.545988 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1073849 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028092 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 121121114 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45731569 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35283041 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8365 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4658 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3880 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39243245 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4372 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 321528 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37680469 # Type of FU issued +system.cpu0.iq.rate 0.547844 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1068228 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028350 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 118776881 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45031578 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34706639 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8278 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4652 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38692178 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4305 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 310856 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1492825 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3508 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13401 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 615446 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1466992 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3639 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12971 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 614314 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149535 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5390 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192663 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5266 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1071047 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4218607 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98464 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39061403 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 95550 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7912486 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5888217 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 616723 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40108 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2851 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13401 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 172679 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 129654 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 302333 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37800204 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9383648 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 425778 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1058011 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4168228 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 100403 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38437075 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 94997 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7771036 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5796008 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 609484 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39021 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3188 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12971 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 173285 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 127529 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 300814 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37265519 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9306913 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 414950 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119312 # number of nop insts executed -system.cpu0.iew.exec_refs 14941647 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4991029 # Number of branches executed -system.cpu0.iew.exec_stores 5557999 # Number of stores executed -system.cpu0.iew.exec_rate 0.539907 # Inst execution rate -system.cpu0.iew.wb_sent 37583639 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35286921 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18740450 # num instructions producing a value -system.cpu0.iew.wb_consumers 35992151 # num instructions consuming a value +system.cpu0.iew.exec_nop 118987 # number of nop insts executed +system.cpu0.iew.exec_refs 14762216 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4927541 # Number of branches executed +system.cpu0.iew.exec_stores 5455303 # Number of stores executed +system.cpu0.iew.exec_rate 0.541811 # Inst execution rate +system.cpu0.iew.wb_sent 37049261 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34710512 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18431396 # num instructions producing a value +system.cpu0.iew.wb_consumers 35371181 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.504009 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520682 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.504663 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.521085 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6642216 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688687 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 262418 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 42437322 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.753690 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.709171 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6565608 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 678859 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 262014 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41204670 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.762989 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.718954 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 30360862 71.54% 71.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5984991 14.10% 85.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1981270 4.67% 90.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1011467 2.38% 92.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 801137 1.89% 94.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 524678 1.24% 95.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395620 0.93% 96.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 217374 0.51% 97.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1159923 2.73% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29337596 71.20% 71.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5890386 14.30% 85.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1942613 4.71% 90.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 987342 2.40% 92.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 788686 1.91% 94.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 508616 1.23% 95.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 388471 0.94% 96.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 215239 0.52% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1145721 2.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 42437322 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24255943 # Number of instructions committed -system.cpu0.commit.committedOps 31984592 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41204670 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23832067 # Number of instructions committed +system.cpu0.commit.committedOps 31438729 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11692432 # Number of memory references committed -system.cpu0.commit.loads 6419661 # Number of loads committed -system.cpu0.commit.membars 234476 # Number of memory barriers committed -system.cpu0.commit.branches 4345348 # Number of branches committed +system.cpu0.commit.refs 11485738 # Number of memory references committed +system.cpu0.commit.loads 6304044 # Number of loads committed +system.cpu0.commit.membars 231899 # Number of memory barriers committed +system.cpu0.commit.branches 4278221 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28253924 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499843 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1159923 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27759030 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489603 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1145721 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 79019948 # The number of ROB reads -system.cpu0.rob.rob_writes 78326882 # The number of ROB writes -system.cpu0.timesIdled 363516 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26540511 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5137512787 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24175201 # Number of Instructions Simulated -system.cpu0.committedOps 31903850 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24175201 # Number of Instructions Simulated -system.cpu0.cpi 2.896046 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.896046 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.345298 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.345298 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176381452 # number of integer regfile reads -system.cpu0.int_regfile_writes 35063385 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3376 # number of floating regfile reads -system.cpu0.fp_regfile_writes 954 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47472836 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527620 # number of misc regfile writes -system.cpu0.icache.replacements 404634 # number of replacements -system.cpu0.icache.tagsinuse 511.577738 # Cycle average of tags in use -system.cpu0.icache.total_refs 3973841 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 405146 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.808417 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7097415000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.577738 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3973841 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3973841 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3973841 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3973841 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3973841 # number of overall hits -system.cpu0.icache.overall_hits::total 3973841 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 437728 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 437728 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 437728 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 437728 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 437728 # number of overall misses -system.cpu0.icache.overall_misses::total 437728 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5954762997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5954762997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5954762997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5954762997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5954762997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5954762997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4411569 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4411569 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4411569 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4411569 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4411569 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4411569 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099223 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099223 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099223 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099223 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099223 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099223 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13603.797328 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13603.797328 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13603.797328 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13603.797328 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2654 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77195085 # The number of ROB reads +system.cpu0.rob.rob_writes 77069186 # The number of ROB writes +system.cpu0.timesIdled 361877 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26552764 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 1938011770 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23751325 # Number of Instructions Simulated +system.cpu0.committedOps 31357987 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23751325 # Number of Instructions Simulated +system.cpu0.cpi 2.895821 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.895821 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.345325 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.345325 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 173747096 # number of integer regfile reads +system.cpu0.int_regfile_writes 34492759 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3279 # number of floating regfile reads +system.cpu0.fp_regfile_writes 922 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46707854 # number of misc regfile reads +system.cpu0.misc_regfile_writes 520465 # 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mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.091841 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091841 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.091841 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11991.416985 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11991.416985 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11991.416985 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32125 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091303 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091303 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.091303 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091303 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.091303 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12019.826805 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12019.826805 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12019.826805 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12019.826805 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12019.826805 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12019.826805 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275305 # number of replacements -system.cpu0.dcache.tagsinuse 476.472696 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9563233 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275817 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.672384 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 50121000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.472696 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.930611 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.930611 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5934886 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5934886 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3237835 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3237835 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174610 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174610 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171576 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171576 # 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number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10959928 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062616 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062616 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333492 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333492 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048124 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048124 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.041714 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.041714 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179812 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.179812 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179812 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.179812 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13780.026095 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13780.026095 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38332.080117 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38332.080117 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10019.066591 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10019.066591 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6278.418231 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6278.418231 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33481.367440 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33481.367440 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33481.367440 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33481.367440 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8182 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3189 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 586 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.962457 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 40.367089 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255914 # number of writebacks -system.cpu0.dcache.writebacks::total 255914 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200897 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 200897 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449259 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1449259 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 477 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 477 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650156 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1650156 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650156 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1650156 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189112 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189112 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131030 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131030 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8426 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8426 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7752 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7752 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320142 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320142 # 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number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6796961991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6796961991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6796961991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6796961991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432598000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432598000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1289898395 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1289898395 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14722496395 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14722496395 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029900 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029900 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027195 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027195 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045915 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045915 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043227 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043227 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028730 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028730 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12307.688037 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12307.688037 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34109.978562 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34109.978562 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7952.053169 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.053169 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7463.299794 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7463.299794 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256407 # number of writebacks +system.cpu0.dcache.writebacks::total 256407 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200970 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 200970 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450977 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1450977 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1651947 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1651947 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1651947 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1651947 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188383 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188383 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130394 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130394 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318777 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318777 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2337539000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2337539000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4029396491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4029396491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66744000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66744000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31921000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31921000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6366935491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6366935491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6366935491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6366935491 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13497539000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13497539000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1126787391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1126787391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14624326391 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14624326391 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030296 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030296 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027498 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027498 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045785 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045785 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041703 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041703 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029086 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029086 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12408.439190 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12408.439190 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30901.701696 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30901.701696 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7985.642498 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7985.642498 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4280.101904 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4280.101904 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1077,27 +1235,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43411799 # DTB read hits -system.cpu1.dtb.read_misses 44882 # DTB read misses -system.cpu1.dtb.write_hits 7014123 # DTB write hits -system.cpu1.dtb.write_misses 11858 # DTB write misses +system.cpu1.dtb.read_hits 42793425 # DTB read hits +system.cpu1.dtb.read_misses 43166 # DTB read misses +system.cpu1.dtb.write_hits 6855715 # DTB write hits +system.cpu1.dtb.write_misses 11673 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2347 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3336 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 317 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3409 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 352 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43456681 # DTB read accesses -system.cpu1.dtb.write_accesses 7025981 # DTB write accesses +system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42836591 # DTB read accesses +system.cpu1.dtb.write_accesses 6867388 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50425922 # DTB hits -system.cpu1.dtb.misses 56740 # DTB misses -system.cpu1.dtb.accesses 50482662 # DTB accesses -system.cpu1.itb.inst_hits 9129638 # ITB inst hits -system.cpu1.itb.inst_misses 6055 # ITB inst misses +system.cpu1.dtb.hits 49649140 # DTB hits +system.cpu1.dtb.misses 54839 # DTB misses +system.cpu1.dtb.accesses 49703979 # DTB accesses +system.cpu1.itb.inst_hits 7790428 # ITB inst hits +system.cpu1.itb.inst_misses 6195 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1106,122 +1264,122 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1576 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1551 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1653 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1608 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9135693 # ITB inst accesses -system.cpu1.itb.hits 9129638 # DTB hits -system.cpu1.itb.misses 6055 # DTB misses -system.cpu1.itb.accesses 9135693 # DTB accesses -system.cpu1.numCycles 413048277 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7796623 # ITB inst accesses +system.cpu1.itb.hits 7790428 # DTB hits +system.cpu1.itb.misses 6195 # DTB misses +system.cpu1.itb.accesses 7796623 # DTB accesses +system.cpu1.numCycles 407481845 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9610060 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7888453 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 467347 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6680212 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5602853 # Number of BTB hits +system.cpu1.BPredUnit.lookups 8945563 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7276620 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 457303 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6059330 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5044901 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 834872 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50683 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 20902821 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71155819 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9610060 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6437725 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15200148 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4519747 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 75962 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 79085155 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 48956 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142448 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9127576 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 837727 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3443 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 118542872 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.725366 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.076680 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 808900 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 49599 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 19209398 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61160390 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8945563 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5853801 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13372143 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3528800 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 72716 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77592776 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4530 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48363 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 137630 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7788411 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 558980 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3579 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 112853111 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.663918 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.993452 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 103350754 87.18% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 840912 0.71% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1013712 0.86% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2056350 1.73% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1628340 1.37% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 605586 0.51% 92.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2262195 1.91% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 445115 0.38% 94.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6339908 5.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99488795 88.16% 88.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 820731 0.73% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 982302 0.87% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1718236 1.52% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1416689 1.26% 92.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 588425 0.52% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1946926 1.73% 94.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 433337 0.38% 95.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5457670 4.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 118542872 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.023266 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.172270 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 22607772 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78712094 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13698658 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 543937 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2980411 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1178240 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102814 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 80488884 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 342985 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2980411 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 24131061 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32829819 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41497762 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12625753 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4478066 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74194515 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19311 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 694411 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3187694 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 34028 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 78612274 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 341980095 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 341920829 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50181552 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28430722 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 479709 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 419295 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8182404 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13956070 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8535310 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1073815 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1496663 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 66987245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1207542 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 91662010 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 107326 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18596353 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52788554 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 287891 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 118542872 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.773239 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.509704 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 112853111 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021953 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.150094 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20594111 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77223821 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12189210 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 529456 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2316513 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1140486 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100773 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 70872122 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 333080 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2316513 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21811188 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31999564 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40913868 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11406608 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4405370 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 66851676 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19516 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 679552 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3147713 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33677 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70148588 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 306845192 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 306785894 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59298 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49106817 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 21041771 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 463027 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 405725 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7962793 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12778752 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8032472 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1035556 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1464082 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 61394803 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1176532 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88185041 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108507 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 14048968 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 37726295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 276552 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 112853111 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.781414 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519020 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 87045508 73.43% 73.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8827320 7.45% 80.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4565356 3.85% 84.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3971386 3.35% 88.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10748062 9.07% 97.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1958505 1.65% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1059536 0.89% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 289761 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 77438 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 82669825 73.25% 73.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8481760 7.52% 80.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4273659 3.79% 84.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3671895 3.25% 87.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10427666 9.24% 97.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1949609 1.73% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1042899 0.92% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 262209 0.23% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73589 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 118542872 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 112853111 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 27804 0.35% 0.35% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 991 0.01% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 26972 0.34% 0.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available @@ -1249,395 +1407,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7575099 95.91% 96.28% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 294066 3.72% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7550123 96.09% 96.44% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 279583 3.56% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39285679 42.86% 43.20% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61425 0.07% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44600762 48.66% 91.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7398685 8.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36904735 41.85% 42.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59478 0.07% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1462 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43687858 49.54% 91.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7217483 8.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 91662010 # Type of FU issued -system.cpu1.iq.rate 0.221916 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7897960 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.086164 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 309913949 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 86800137 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55536555 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14796 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 99238492 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7741 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 357612 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88185041 # Type of FU issued +system.cpu1.iq.rate 0.216415 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7857674 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089104 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 297228981 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 76628774 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53465228 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15030 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8076 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6856 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95720841 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7877 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 343881 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3966417 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4317 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17649 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1516764 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3018668 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4236 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17116 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1176826 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31964885 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1028430 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906521 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 692078 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2980411 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24884610 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 372296 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68300564 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 134907 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13956070 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8535310 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 896808 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67508 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3396 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17649 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 244559 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 171299 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 415858 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 88842251 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43794323 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2819759 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2316513 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24121346 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 362647 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 62677152 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 130612 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12778752 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8032472 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 873727 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64946 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17116 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 239035 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 168853 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 407888 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86386034 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43162344 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1799007 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105777 # number of nop insts executed -system.cpu1.iew.exec_refs 51113945 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7256967 # Number of branches executed -system.cpu1.iew.exec_stores 7319622 # Number of stores executed -system.cpu1.iew.exec_rate 0.215089 # Inst execution rate -system.cpu1.iew.wb_sent 87693649 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55543356 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30809625 # num instructions producing a value -system.cpu1.iew.wb_consumers 54951337 # num instructions consuming a value +system.cpu1.iew.exec_nop 105817 # number of nop insts executed +system.cpu1.iew.exec_refs 50303914 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6949979 # Number of branches executed +system.cpu1.iew.exec_stores 7141570 # Number of stores executed +system.cpu1.iew.exec_rate 0.212000 # Inst execution rate +system.cpu1.iew.wb_sent 85560494 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53472084 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29815301 # num instructions producing a value +system.cpu1.iew.wb_consumers 53181116 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.134472 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560671 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131226 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560637 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 18558974 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 919651 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 366370 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 115610884 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.426428 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.387814 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14046998 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899980 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 358444 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 110583599 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.436135 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.404322 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 98380656 85.10% 85.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8456019 7.31% 92.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2240447 1.94% 94.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1287846 1.11% 95.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1284560 1.11% 96.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 584416 0.51% 97.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1022455 0.88% 97.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531646 0.46% 98.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1822839 1.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 93772628 84.80% 84.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8260056 7.47% 92.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2160964 1.95% 94.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1246626 1.13% 95.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1244768 1.13% 96.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 580382 0.52% 97.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 994186 0.90% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 530445 0.48% 98.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1793544 1.62% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 115610884 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38938330 # Number of instructions committed -system.cpu1.commit.committedOps 49299735 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 110583599 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38115610 # Number of instructions committed +system.cpu1.commit.committedOps 48229427 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17008199 # Number of memory references committed -system.cpu1.commit.loads 9989653 # Number of loads committed -system.cpu1.commit.membars 202304 # Number of memory barriers committed -system.cpu1.commit.branches 6136573 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43691789 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556207 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1822839 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16615730 # Number of memory references committed +system.cpu1.commit.loads 9760084 # Number of loads committed +system.cpu1.commit.membars 196512 # Number of memory barriers committed +system.cpu1.commit.branches 5981373 # Number of branches committed +system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42745221 # Number of committed integer instructions. +system.cpu1.commit.function_calls 536771 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1793544 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 180532357 # The number of ROB reads -system.cpu1.rob.rob_writes 138785705 # The number of ROB writes -system.cpu1.timesIdled 1423841 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294505405 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4793867333 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38868691 # Number of Instructions Simulated -system.cpu1.committedOps 49230096 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38868691 # Number of Instructions Simulated -system.cpu1.cpi 10.626761 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.626761 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094102 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094102 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 397649399 # number of integer regfile reads -system.cpu1.int_regfile_writes 58356680 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4927 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes -system.cpu1.misc_regfile_reads 90861332 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429704 # number of misc regfile writes -system.cpu1.icache.replacements 621691 # number of replacements -system.cpu1.icache.tagsinuse 498.705536 # Cycle average of tags in use -system.cpu1.icache.total_refs 8457096 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 622203 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.592181 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74944474500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.705536 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974034 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974034 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8457096 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8457096 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8457096 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8457096 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8457096 # number of overall hits -system.cpu1.icache.overall_hits::total 8457096 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 670427 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 670427 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 670427 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 670427 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 670427 # number of overall misses -system.cpu1.icache.overall_misses::total 670427 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8963788993 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8963788993 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8963788993 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8963788993 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8963788993 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8963788993 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9127523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9127523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9127523 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9127523 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9127523 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9127523 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073451 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073451 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073451 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073451 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073451 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073451 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13370.268490 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13370.268490 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13370.268490 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13370.268490 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked +system.cpu1.rob.rob_reads 169976861 # The number of ROB reads +system.cpu1.rob.rob_writes 126957772 # The number of ROB writes +system.cpu1.timesIdled 1410203 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294628734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1598708296 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38045971 # Number of Instructions Simulated +system.cpu1.committedOps 48159788 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38045971 # Number of Instructions Simulated +system.cpu1.cpi 10.710250 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.710250 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093369 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093369 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 386616069 # number of integer regfile reads +system.cpu1.int_regfile_writes 55621377 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5021 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes +system.cpu1.misc_regfile_reads 80414047 # number of misc regfile reads +system.cpu1.misc_regfile_writes 414877 # number of misc regfile writes +system.cpu1.icache.replacements 603717 # number of replacements +system.cpu1.icache.tagsinuse 477.821623 # Cycle average of tags in use +system.cpu1.icache.total_refs 7136949 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 604229 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 11.811662 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74643061500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 477.821623 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.933245 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.933245 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7136949 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7136949 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7136949 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7136949 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7136949 # number of overall hits +system.cpu1.icache.overall_hits::total 7136949 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 651410 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 651410 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 651410 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 651410 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 651410 # number of overall misses +system.cpu1.icache.overall_misses::total 651410 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8713848493 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8713848493 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8713848493 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8713848493 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8713848493 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8713848493 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7788359 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7788359 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7788359 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7788359 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7788359 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7788359 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.083639 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.083639 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.083639 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.083639 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.083639 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.083639 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13376.903169 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13376.903169 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13376.903169 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13376.903169 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13376.903169 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13376.903169 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2264 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 195 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.184211 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.610256 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48189 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 48189 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 48189 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 48189 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 48189 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 48189 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622238 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 622238 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 622238 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 622238 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 622238 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 622238 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328903994 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328903994 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328903994 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7328903994 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328903994 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7328903994 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3208500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3208500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3208500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3208500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068172 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.068172 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.068172 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11778.297041 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47151 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 47151 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 47151 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 47151 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 47151 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 47151 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 604259 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 604259 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 604259 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 604259 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 604259 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 604259 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7123176495 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7123176495 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7123176495 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7123176495 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7123176495 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7123176495 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2925000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2925000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2925000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2925000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077585 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077585 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077585 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.077585 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077585 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.077585 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11788.283658 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11788.283658 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11788.283658 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11788.283658 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11788.283658 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11788.283658 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363699 # number of replacements -system.cpu1.dcache.tagsinuse 487.062362 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13149394 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 364069 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.117862 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 71012585000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.062362 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951294 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951294 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8615849 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8615849 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4289025 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4289025 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104659 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 104659 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100738 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100738 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12904874 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12904874 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12904874 # number of overall hits -system.cpu1.dcache.overall_hits::total 12904874 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 398775 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 398775 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1559814 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1559814 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14251 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14251 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10935 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10935 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1958589 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1958589 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1958589 # number of overall misses -system.cpu1.dcache.overall_misses::total 1958589 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5911762000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5911762000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56390406018 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 56390406018 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131021000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 131021000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 76240500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 76240500 # 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number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12680 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10565 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10565 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 390734 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 390734 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 390734 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 390734 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2822036500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2822036500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5251302714 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5251302714 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90148000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90148000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32112000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32112000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8073339214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8073339214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8073339214 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8073339214 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168945425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168945425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26941470024 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26941470024 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195886895024 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195886895024 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026029 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026029 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028353 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028353 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108401 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108401 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096945 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096945 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026944 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026944 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026944 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026944 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12330.303229 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12330.303229 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32442.684686 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32442.684686 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7109.463722 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7109.463722 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3039.469948 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3039.469948 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20661.982868 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20661.982868 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20661.982868 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20661.982868 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1659,18 +1817,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1218779341193 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1218779341193 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 421898642152 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 421898642152 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 421898642152 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 421898642152 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43799 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43084 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53911 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 52242 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index c4b901e8a..df36d5962 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,212 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534173 # Number of seconds simulated -sim_ticks 2534173219000 # Number of ticks simulated -final_tick 2534173219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523636 # Number of seconds simulated +sim_ticks 2523635852000 # Number of ticks simulated +final_tick 2523635852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83771 # Simulator instruction rate (inst/s) -host_op_rate 107754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3503174864 # Simulator tick rate (ticks/s) -host_mem_usage 385312 # Number of bytes of host memory used -host_seconds 723.39 # Real time elapsed on the host -sim_insts 60599410 # Number of instructions simulated -sim_ops 77948210 # Number of ops (including micro ops) simulated +host_inst_rate 45530 # Simulator instruction rate (inst/s) +host_op_rate 58565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1896155435 # Simulator tick rate (ticks/s) +host_mem_usage 399768 # Number of bytes of host memory used +host_seconds 1330.92 # Real time elapsed on the host +sim_insts 60597347 # Number of instructions simulated +sim_ops 77945524 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3584 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9096016 # Number of bytes read from this memory -system.physmem.bytes_read::total 129435344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory +system.physmem.bytes_read::total 129436368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 56 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12470 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142159 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096893 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12490 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096909 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47170281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1389 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47367240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1420 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314927 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51075966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314927 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314927 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493669 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190160 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683829 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47170281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3604203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51289637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47367240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1420 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4779503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53759795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4799333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53983912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096909 # Total number of read requests seen +system.physmem.writeReqs 813132 # Total number of write requests seen +system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966202176 # Total number of bytes read from memory +system.physmem.bytesWritten 52040448 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129436368 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 363 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943955 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943427 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943111 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943293 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50098 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50033 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50667 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51122 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51107 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51028 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 1156323 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523634566000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 36 # Categorize read packet sizes +system.physmem.readPktSize::3 14942208 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 154665 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 1910341 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 59114 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 14955787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 2806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 46870409147 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317530293147 # Sum of mem lat for all requests +system.physmem.totBusLat 60386184000 # Total cycles spent in databus access +system.physmem.totBankLat 210273700000 # Total cycles spent in bank access +system.physmem.avgQLat 3104.71 # Average queueing delay per request +system.physmem.avgBankLat 13928.60 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 21033.31 # Average memory access latency +system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.52 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.avgWrQLen 12.37 # Average write queue length over time +system.physmem.readRowHits 15050555 # Number of row buffer hits during reads +system.physmem.writeRowHits 784512 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.48 # Row buffer hit rate for writes +system.physmem.avgGap 158618.99 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -69,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51719750 # DTB read hits -system.cpu.dtb.read_misses 77229 # DTB read misses -system.cpu.dtb.write_hits 11809411 # DTB write hits -system.cpu.dtb.write_misses 17373 # DTB write misses +system.cpu.dtb.read_hits 51390867 # DTB read hits +system.cpu.dtb.read_misses 77330 # DTB read misses +system.cpu.dtb.write_hits 11807590 # DTB write hits +system.cpu.dtb.write_misses 17145 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4263 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2639 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4249 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2913 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 528 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1315 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51796979 # DTB read accesses -system.cpu.dtb.write_accesses 11826784 # DTB write accesses +system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51468197 # DTB read accesses +system.cpu.dtb.write_accesses 11824735 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63529161 # DTB hits -system.cpu.dtb.misses 94602 # DTB misses -system.cpu.dtb.accesses 63623763 # DTB accesses -system.cpu.itb.inst_hits 13045523 # ITB inst hits -system.cpu.itb.inst_misses 12142 # ITB inst misses +system.cpu.dtb.hits 63198457 # DTB hits +system.cpu.dtb.misses 94475 # DTB misses +system.cpu.dtb.accesses 63292932 # DTB accesses +system.cpu.itb.inst_hits 11866859 # ITB inst hits +system.cpu.itb.inst_misses 12387 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -98,538 +256,538 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2586 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2600 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3109 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3124 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13057665 # ITB inst accesses -system.cpu.itb.hits 13045523 # DTB hits -system.cpu.itb.misses 12142 # DTB misses -system.cpu.itb.accesses 13057665 # DTB accesses -system.cpu.numCycles 475815628 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11879246 # ITB inst accesses +system.cpu.itb.hits 11866859 # DTB hits +system.cpu.itb.misses 12387 # DTB misses +system.cpu.itb.accesses 11879246 # DTB accesses +system.cpu.numCycles 471620131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15155227 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12146705 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783529 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10394615 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8308125 # Number of BTB hits +system.cpu.BPredUnit.lookups 14707897 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11700483 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783548 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9751137 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7864369 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454278 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82490 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31347726 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 100822937 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15155227 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9762403 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22167713 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5923551 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 130252 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97680521 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2843 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 98238 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209120 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13041690 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1002552 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6432 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155704074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.799073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.166371 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1453661 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82859 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 30173854 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 91943847 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14707897 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9318030 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20602156 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4980521 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 134933 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96636325 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2675 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 101652 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208965 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11862984 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 731347 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6597 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151294412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.758755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.115735 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133553129 85.77% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1381799 0.89% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755926 1.13% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2652519 1.70% 89.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2328486 1.50% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1136180 0.73% 91.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2905092 1.87% 93.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 785179 0.50% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9205764 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130709145 86.39% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1380335 0.91% 87.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1756131 1.16% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2339631 1.55% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2142384 1.42% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1132136 0.75% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2619139 1.73% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 785245 0.52% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8430266 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155704074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031851 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.211895 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33480524 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 97304946 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19992509 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1030333 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3895762 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2022425 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174533 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 117498058 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576273 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3895762 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35565671 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37584641 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53601603 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18869314 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6187083 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110088875 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21357 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1014287 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4146063 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 32391 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 114923514 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 504161217 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 504070393 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78734130 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36189383 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892416 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 798033 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12508562 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20972747 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13834973 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1961849 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2465756 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 100830951 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058696 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126177528 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24329335 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 64639752 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514100 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155704074 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.810368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523012 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151294412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.194953 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32008731 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96268896 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18723702 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1031258 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3261825 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2020367 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174818 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 109258714 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3261825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33805354 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36852775 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53319596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17901114 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6153748 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 104067610 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21499 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015662 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4122290 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31949 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 107816884 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 475027641 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 474936857 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90784 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78731329 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 29085554 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891358 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 796895 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12333147 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20062338 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13521403 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1975115 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2433562 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 96511960 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2056994 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123962105 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189941 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20009013 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 50083503 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 512489 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151294412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.531574 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 110503842 70.97% 70.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14006844 9.00% 79.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7305691 4.69% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6085046 3.91% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12721239 8.17% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2798387 1.80% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1680857 1.08% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 475213 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126955 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106913550 70.67% 70.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13863924 9.16% 79.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7098415 4.69% 84.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5869010 3.88% 88.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12472838 8.24% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2771623 1.83% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1718676 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 458210 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128166 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155704074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151294412 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57592 0.65% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370496 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418270 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 56852 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8372882 94.63% 95.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 417861 4.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59895243 47.47% 47.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95317 0.08% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 7 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53367566 42.30% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12453578 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58285332 47.02% 47.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95139 0.08% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52764596 42.57% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12451206 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126177528 # Type of FU issued -system.cpu.iq.rate 0.265182 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8846360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070110 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417165828 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127235505 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87177257 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23405 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134647760 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12462 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624931 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123962105 # Type of FU issued +system.cpu.iq.rate 0.262843 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8847599 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071373 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 408327002 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118594240 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86288141 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23234 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12518 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10286 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132433714 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12324 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 628913 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5256081 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7285 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30200 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2036035 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4346263 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7649 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29949 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1722835 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34106907 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1030049 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107855 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695994 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3895762 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28674144 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 449674 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103114750 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 233495 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20972747 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13834973 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466916 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113563 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3765 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30200 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 409921 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 292907 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 702828 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122963273 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52407414 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3214255 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3261825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27934565 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 435305 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98793776 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 231675 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20062338 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13521403 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1465659 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113955 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3708 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29949 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409673 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293589 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 703262 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121754884 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52078341 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2207221 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 225103 # number of nop insts executed -system.cpu.iew.exec_refs 64729141 # number of memory reference insts executed -system.cpu.iew.exec_branches 11726228 # Number of branches executed -system.cpu.iew.exec_stores 12321727 # Number of stores executed -system.cpu.iew.exec_rate 0.258426 # Inst execution rate -system.cpu.iew.wb_sent 121618308 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87187548 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47710631 # num instructions producing a value -system.cpu.iew.wb_consumers 88857501 # num instructions consuming a value +system.cpu.iew.exec_nop 224822 # number of nop insts executed +system.cpu.iew.exec_refs 64398044 # number of memory reference insts executed +system.cpu.iew.exec_branches 11600510 # Number of branches executed +system.cpu.iew.exec_stores 12319703 # Number of stores executed +system.cpu.iew.exec_rate 0.258163 # Inst execution rate +system.cpu.iew.wb_sent 120731241 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86298427 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47352499 # num instructions producing a value +system.cpu.iew.wb_consumers 88423671 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183238 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182983 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535518 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24186815 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544596 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612016 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151890748 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.495245 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19868331 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544505 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 611839 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148115015 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.527265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.512607 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 124092082 81.70% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13579714 8.94% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3980091 2.62% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2134436 1.41% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949184 1.28% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1000796 0.66% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1579621 1.04% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 721647 0.48% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2853177 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120340532 81.25% 81.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13566988 9.16% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3964696 2.68% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2137699 1.44% 94.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1955021 1.32% 95.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 974024 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1590640 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 730936 0.49% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2854479 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151890748 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60749791 # Number of instructions committed -system.cpu.commit.committedOps 78098591 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148115015 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747728 # Number of instructions committed +system.cpu.commit.committedOps 78095905 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27515604 # Number of memory references committed -system.cpu.commit.loads 15716666 # Number of loads committed -system.cpu.commit.membars 413138 # Number of memory barriers committed -system.cpu.commit.branches 10023383 # Number of branches committed +system.cpu.commit.refs 27514643 # Number of memory references committed +system.cpu.commit.loads 15716075 # Number of loads committed +system.cpu.commit.membars 413107 # Number of memory barriers committed +system.cpu.commit.branches 10023098 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69136784 # Number of committed integer instructions. -system.cpu.commit.function_calls 996034 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2853177 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69134339 # Number of committed integer instructions. +system.cpu.commit.function_calls 995983 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2854479 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249407638 # The number of ROB reads -system.cpu.rob.rob_writes 208557399 # The number of ROB writes -system.cpu.timesIdled 1773714 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320111554 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592442776 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60599410 # Number of Instructions Simulated -system.cpu.committedOps 77948210 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60599410 # Number of Instructions Simulated -system.cpu.cpi 7.851819 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.851819 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127359 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127359 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556670718 # number of integer regfile reads -system.cpu.int_regfile_writes 89963165 # number of integer regfile writes -system.cpu.fp_regfile_reads 8373 # number of floating regfile reads -system.cpu.fp_regfile_writes 2910 # number of floating regfile writes -system.cpu.misc_regfile_reads 132949410 # number of misc regfile reads -system.cpu.misc_regfile_writes 912934 # number of misc regfile writes -system.cpu.icache.replacements 989799 # number of replacements -system.cpu.icache.tagsinuse 511.593898 # Cycle average of tags in use -system.cpu.icache.total_refs 11967809 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990311 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.084900 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.593898 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11967809 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11967809 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11967809 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11967809 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11967809 # number of overall hits -system.cpu.icache.overall_hits::total 11967809 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1073749 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1073749 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1073749 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1073749 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1073749 # number of overall misses -system.cpu.icache.overall_misses::total 1073749 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14109467991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14109467991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14109467991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14109467991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14109467991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14109467991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13041558 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13041558 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13041558 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13041558 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13041558 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13041558 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082333 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082333 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082333 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082333 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082333 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082333 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13140.378236 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13140.378236 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13140.378236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13140.378236 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4599 # number of cycles access was blocked +system.cpu.rob.rob_reads 241309637 # The number of ROB reads +system.cpu.rob.rob_writes 199282329 # The number of ROB writes +system.cpu.timesIdled 1774359 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320325719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575563546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60597347 # Number of Instructions Simulated +system.cpu.committedOps 77945524 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60597347 # Number of Instructions Simulated +system.cpu.cpi 7.782851 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.782851 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 551501617 # number of integer regfile reads +system.cpu.int_regfile_writes 88408651 # number of integer regfile writes +system.cpu.fp_regfile_reads 8346 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 124084349 # number of misc regfile reads +system.cpu.misc_regfile_writes 912885 # number of misc regfile writes +system.cpu.icache.replacements 990639 # number of replacements +system.cpu.icache.tagsinuse 510.412932 # Cycle average of tags in use +system.cpu.icache.total_refs 10788740 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991151 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.885062 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.412932 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996900 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996900 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10788740 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10788740 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10788740 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10788740 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10788740 # number of overall hits +system.cpu.icache.overall_hits::total 10788740 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1074113 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1074113 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1074113 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1074113 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1074113 # number of overall misses +system.cpu.icache.overall_misses::total 1074113 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14116777488 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14116777488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14116777488 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14116777488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14116777488 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14116777488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11862853 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11862853 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11862853 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11862853 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11862853 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11862853 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.090544 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.090544 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.090544 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.090544 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.090544 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.090544 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13142.730316 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13142.730316 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13142.730316 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13142.730316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.730316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13142.730316 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4157 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 287 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.029412 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 14.484321 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83395 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 83395 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 83395 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 83395 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 83395 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 83395 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990354 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 990354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 990354 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 990354 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 990354 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 990354 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11451236993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11451236993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11451236993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11451236993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11451236993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11451236993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075938 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075938 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075938 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.771487 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.771487 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82910 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 82910 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 82910 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 82910 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 82910 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 82910 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991203 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991203 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991203 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991203 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991203 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991203 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11465402488 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11465402488 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11465402488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11465402488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11465402488 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11465402488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7052500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7052500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7052500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7052500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.083555 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.083555 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.083555 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.083555 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.083555 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.083555 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11567.158784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11567.158784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11567.158784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11567.158784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11567.158784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11567.158784 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30791.342498 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25421 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15604 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2521 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.083697 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.948905 # average number of cycles each access was blocked +system.cpu.dcache.replacements 645056 # number of replacements +system.cpu.dcache.tagsinuse 511.994184 # Cycle average of tags in use +system.cpu.dcache.total_refs 21772057 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645568 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.725428 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35202000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994184 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13909872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13909872 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7289107 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7289107 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284200 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284200 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285733 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285733 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21198979 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21198979 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21198979 # number of overall hits +system.cpu.dcache.overall_hits::total 21198979 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 729430 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 729430 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2961614 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2961614 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13575 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13575 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3691044 # 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number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113952343741 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113952343741 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113952343741 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113952343741 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14639302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14639302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250721 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250721 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297775 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297775 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285750 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285750 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24890023 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24890023 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24890023 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24890023 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049827 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049827 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288918 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288918 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045588 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045588 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000059 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000059 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148294 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148294 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148294 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148294 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.338388 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.338388 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35257.523851 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35257.523851 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13353.370166 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13353.370166 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30872.659264 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30872.659264 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30872.659264 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30872.659264 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29185 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15466 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2496 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 253 # 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number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636567 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636567 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636567 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4759977000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4759977000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8542104919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8542104919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141597500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141597500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 288500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 288500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13302081919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13302081919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13302081919 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13302081919 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356244500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356244500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41726674069 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41726674069 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224082918569 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224082918569 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024301 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024301 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040942 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040942 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000052 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # 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average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19233.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19233.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609134 # number of writebacks +system.cpu.dcache.writebacks::total 609134 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 342186 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 342186 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712531 # 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average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -637,149 +795,149 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64413 # number of replacements -system.cpu.l2cache.tagsinuse 51352.307141 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1928116 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129809 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.853485 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222789 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090365 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41044.839598 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40459.418744 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40773.060165 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40005.288298 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40005.288298 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40261.502586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40261.502586 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12366 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143867 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156290 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2968112 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 506752203 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 451262870 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 961020185 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29368926 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29368926 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5049223821 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5049223821 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2968112 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 37000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 506752203 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5500486691 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6010244006 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2968112 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 37000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506752203 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5500486691 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6010244006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4470659 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166682463030 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166686933689 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18112015818 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18112015818 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4470659 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184794478848 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184798949507 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000672 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026724 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015556 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984569 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984569 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541026 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541026 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000672 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222853 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090296 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000672 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222853 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090296 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40979.476225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42280.789844 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41609.810573 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10006.448382 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.448382 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37908.793347 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37908.793347 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38455.716975 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38455.716975 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -914,16 +1072,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1202929249396 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1202929249396 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068189786972 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068189786972 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88028 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 908c82993..0613cfd5e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,84 +1,242 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133289 # Number of seconds simulated -sim_ticks 5133289198000 # Number of ticks simulated -final_tick 5133289198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.128875 # Number of seconds simulated +sim_ticks 5128875494000 # Number of ticks simulated +final_tick 5128875494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170996 # Simulator instruction rate (inst/s) -host_op_rate 338013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2151657827 # Simulator tick rate (ticks/s) -host_mem_usage 361992 # Number of bytes of host memory used -host_seconds 2385.74 # Real time elapsed on the host -sim_insts 407952579 # Number of instructions simulated -sim_ops 806410876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2466560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2496 # Number of bytes read from this memory +host_inst_rate 179743 # Simulator instruction rate (inst/s) +host_op_rate 355302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2259848354 # Simulator tick rate (ticks/s) +host_mem_usage 404644 # Number of bytes of host memory used +host_seconds 2269.57 # Real time elapsed on the host +sim_insts 407937807 # Number of instructions simulated +sim_ops 806381430 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2484160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1078720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10839424 # Number of bytes read from this memory -system.physmem.bytes_read::total 14387648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1078720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1078720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9551232 # Number of bytes written to this memory -system.physmem.bytes_written::total 9551232 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 39 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1082048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10897856 # Number of bytes read from this memory +system.physmem.bytes_read::total 14467456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1082048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1082048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9613376 # Number of bytes written to this memory +system.physmem.bytes_written::total 9613376 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169366 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224807 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149238 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149238 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 480503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 486 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 170279 # Number of read requests responded to by this memory +system.physmem.num_reads::total 226054 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 150209 # Number of write requests responded to by this memory +system.physmem.num_writes::total 150209 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 484348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 574 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2111594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2802813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1860646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1860646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1860646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 480503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2124804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2820785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1874363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1874363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1874363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 484348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 574 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2111594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4663458 # Total bandwidth to/from this memory (bytes/s) -system.iocache.replacements 47577 # number of replacements -system.iocache.tagsinuse 0.116486 # Cycle average of tags in use +system.physmem.bw_total::cpu.inst 210972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2124804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4695148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 226054 # Total number of read requests seen +system.physmem.writeReqs 150209 # Total number of write requests seen +system.physmem.cpureqs 390083 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14467456 # Total number of bytes read from memory +system.physmem.bytesWritten 9613376 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14467456 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9613376 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 85 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3870 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13592 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 14969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 14927 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13783 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14903 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15009 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 10212 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 10302 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8995 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 10163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9599 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 10025 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 10268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 10138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 10156 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 5128875413000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 226054 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 150209 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3870 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 177383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1091 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3329517724 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7605839724 # Sum of mem lat for all requests +system.physmem.totBusLat 903876000 # Total cycles spent in databus access +system.physmem.totBankLat 3372446000 # Total cycles spent in bank access +system.physmem.avgQLat 14734.40 # Average queueing delay per request +system.physmem.avgBankLat 14924.37 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 33658.77 # Average memory access latency +system.physmem.avgRdBW 2.82 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.82 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 14.06 # Average write queue length over time +system.physmem.readRowHits 199198 # Number of row buffer hits during reads +system.physmem.writeRowHits 88428 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.87 # Row buffer hit rate for writes +system.physmem.avgGap 13631091.58 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.091613 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.116486 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007280 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007280 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses -system.iocache.ReadReq_misses::total 912 # number of ReadReq misses +system.iocache.warmup_cycle 4991895066000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.091613 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.005726 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.005726 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses -system.iocache.demand_misses::total 47632 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses -system.iocache.overall_misses::total 47632 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138482932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 138482932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9931610160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9931610160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10070093092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10070093092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10070093092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10070093092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143697932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 143697932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8983849160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 8983849160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 9127547092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9127547092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 9127547092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9127547092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -87,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151845.320175 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 151845.320175 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212577.272260 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 212577.272260 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 211414.450202 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 211414.450202 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 71516 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157736.478595 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 157736.478595 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192291.291952 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 192291.291952 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 191630.389704 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 191630.389704 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56345 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8861 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7566 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.070872 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.447132 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91058932 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 91058932 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7502170160 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7502170160 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7593229092 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7593229092 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96295990 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96295990 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6552154765 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 6552154765 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6648450755 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6648450755 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -129,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99845.320175 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 99845.320175 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160577.272260 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 160577.272260 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105703.611416 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105703.611416 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140243.038634 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 140243.038634 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -150,141 +308,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 448600431 # number of cpu cycles simulated +system.cpu.numCycles 448887765 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86509944 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86509944 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1185802 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81830934 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79445705 # Number of BTB hits +system.cpu.BPredUnit.lookups 86493598 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86493598 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1184200 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81985656 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79438611 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27983612 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427293864 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86509944 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79445705 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164022517 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5056605 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 118707 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 62987614 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36438 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 56602 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9268852 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 518204 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3676 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 259039385 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.256241 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.417856 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28044653 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427268280 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86493598 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79438611 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164008180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5056188 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 124973 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62751260 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 62335 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9257771 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 519239 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3803 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 258861392 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.258152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.417945 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95447322 36.85% 36.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1594478 0.62% 37.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71953209 27.78% 65.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971457 0.38% 65.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1620147 0.63% 66.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2451072 0.95% 67.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1123457 0.43% 67.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1423255 0.55% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82454988 31.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95283812 36.81% 36.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1591927 0.61% 37.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71954404 27.80% 65.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 971846 0.38% 65.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1615863 0.62% 66.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2450126 0.95% 67.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1121647 0.43% 67.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1424659 0.55% 68.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82447108 31.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 259039385 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192844 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952504 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31701157 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60460157 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159747770 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3296725 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3833576 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840199157 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1214 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3833576 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34469655 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37373675 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10858241 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159947646 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12556592 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836331491 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21404 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5918645 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4820353 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7887 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998118157 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816257155 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816256355 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 800 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964383755 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33734395 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 466799 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473697 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28937943 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17313250 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10261817 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1158356 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 954062 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829878064 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256439 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824382236 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167222 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23705426 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36106397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203573 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 259039385 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.182459 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.385421 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 258861392 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192684 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.951838 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31762033 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60235448 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159762632 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3267698 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3833581 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840104917 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1244 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3833581 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34530134 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37412206 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10702091 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159938633 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12444747 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836257763 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19698 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5896480 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4716940 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7816 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 997992319 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816026440 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816025416 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1024 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964353103 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33639209 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 466352 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 473282 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28808345 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17312855 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10260076 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1206444 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 946818 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829834961 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1255797 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824342965 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165215 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23689940 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36113140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 203193 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 258861392 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.184496 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.385380 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72064876 27.82% 27.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15723846 6.07% 33.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10360482 4.00% 37.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7566572 2.92% 40.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75946167 29.32% 70.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3904049 1.51% 71.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72535410 28.00% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 783527 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 154456 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72001826 27.81% 27.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15596239 6.02% 33.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10365970 4.00% 37.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7555139 2.92% 40.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75952295 29.34% 70.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3901347 1.51% 71.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72539766 28.02% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 795622 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 153188 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 259039385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 258861392 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 355366 33.47% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553588 52.14% 85.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152800 14.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 354431 33.41% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 554175 52.24% 85.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152275 14.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 305432 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796570576 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 306719 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796534260 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -313,246 +471,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18033245 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9472983 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18029662 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9472324 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824382236 # Type of FU issued -system.cpu.iq.rate 1.837676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1061754 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001288 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1909166354 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854849744 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819707401 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 374 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 65 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825138441 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1650685 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824342965 # Type of FU issued +system.cpu.iq.rate 1.836412 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1060881 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1908906757 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854790380 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819662460 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825097030 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1650086 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3332850 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26850 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11358 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1844760 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3338406 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26898 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11294 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1845192 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932315 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11695 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932288 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11793 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3833576 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26046353 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2116686 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831134503 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342849 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17313250 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10261817 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725973 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1616805 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16237 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11358 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 710415 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 622755 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1333170 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822369106 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17608498 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2013129 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3833581 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26182715 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2118325 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831090758 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 325842 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17312855 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10260082 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 724912 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1616921 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11294 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 708686 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 624381 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1333067 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822327193 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17600649 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2015771 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26834247 # number of memory reference insts executed -system.cpu.iew.exec_branches 83283502 # Number of branches executed -system.cpu.iew.exec_stores 9225749 # Number of stores executed -system.cpu.iew.exec_rate 1.833188 # Inst execution rate -system.cpu.iew.wb_sent 821860005 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819707466 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640500741 # num instructions producing a value -system.cpu.iew.wb_consumers 1046431080 # num instructions consuming a value +system.cpu.iew.exec_refs 26823265 # number of memory reference insts executed +system.cpu.iew.exec_branches 83275848 # Number of branches executed +system.cpu.iew.exec_stores 9222616 # Number of stores executed +system.cpu.iew.exec_rate 1.831922 # Inst execution rate +system.cpu.iew.wb_sent 821819072 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819662518 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640525310 # num instructions producing a value +system.cpu.iew.wb_consumers 1046521436 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.827255 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612081 # average fanout of values written-back +system.cpu.iew.wb_rate 1.825985 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612052 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24617133 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052864 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1189777 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255221218 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.159655 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.852368 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24603279 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052602 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1189396 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255043204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.161744 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.853415 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83203030 32.60% 32.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11920052 4.67% 37.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4017826 1.57% 38.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74972744 29.38% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2476508 0.97% 69.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1494072 0.59% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1000652 0.39% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70934036 27.79% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5202298 2.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83146159 32.60% 32.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11856679 4.65% 37.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3955758 1.55% 38.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74970525 29.40% 68.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2479858 0.97% 69.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1486016 0.58% 69.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 951787 0.37% 70.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70929950 27.81% 97.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5266472 2.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255221218 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407952579 # Number of instructions committed -system.cpu.commit.committedOps 806410876 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255043204 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407937807 # Number of instructions committed +system.cpu.commit.committedOps 806381430 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22397454 # Number of memory references committed -system.cpu.commit.loads 13980397 # Number of loads committed -system.cpu.commit.membars 473477 # Number of memory barriers committed -system.cpu.commit.branches 82193415 # Number of branches committed +system.cpu.commit.refs 22389336 # Number of memory references committed +system.cpu.commit.loads 13974446 # Number of loads committed +system.cpu.commit.membars 473457 # Number of memory barriers committed +system.cpu.commit.branches 82191509 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735346024 # Number of committed integer instructions. +system.cpu.commit.int_insts 735317730 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5202298 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5266472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080968615 # The number of ROB reads -system.cpu.rob.rob_writes 1665910047 # The number of ROB writes -system.cpu.timesIdled 1218526 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 189561046 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9817975385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407952579 # Number of Instructions Simulated -system.cpu.committedOps 806410876 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407952579 # Number of Instructions Simulated -system.cpu.cpi 1.099639 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.099639 # CPI: Total CPI of All Threads -system.cpu.ipc 0.909390 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.909390 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508324148 # number of integer regfile reads -system.cpu.int_regfile_writes 977861305 # number of integer regfile writes -system.cpu.fp_regfile_reads 65 # number of floating regfile reads -system.cpu.misc_regfile_reads 265169626 # number of misc regfile reads -system.cpu.misc_regfile_writes 402500 # number of misc regfile writes -system.cpu.icache.replacements 1068646 # number of replacements -system.cpu.icache.tagsinuse 510.896112 # Cycle average of tags in use -system.cpu.icache.total_refs 8129454 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1069158 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.603604 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.896112 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997844 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997844 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8129454 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8129454 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8129454 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8129454 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8129454 # number of overall hits -system.cpu.icache.overall_hits::total 8129454 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1139394 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1139394 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1139394 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1139394 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1139394 # number of overall misses -system.cpu.icache.overall_misses::total 1139394 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15246811490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15246811490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15246811490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15246811490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15246811490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15246811490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9268848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9268848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9268848 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9268848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9268848 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9268848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122927 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122927 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122927 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122927 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122927 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122927 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13381.509373 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13381.509373 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13381.509373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13381.509373 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5114 # number of cycles access was blocked +system.cpu.rob.rob_reads 1080683249 # The number of ROB reads +system.cpu.rob.rob_writes 1665823647 # The number of ROB writes +system.cpu.timesIdled 1223181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190026373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9808860643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407937807 # Number of Instructions Simulated +system.cpu.committedOps 806381430 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407937807 # Number of Instructions Simulated +system.cpu.cpi 1.100383 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.100383 # CPI: Total CPI of All Threads +system.cpu.ipc 0.908775 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.908775 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508172140 # number of integer regfile reads +system.cpu.int_regfile_writes 977803744 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.misc_regfile_reads 265152690 # number of misc regfile reads +system.cpu.misc_regfile_writes 402177 # number of misc regfile writes +system.cpu.icache.replacements 1074366 # number of replacements +system.cpu.icache.tagsinuse 510.322538 # Cycle average of tags in use +system.cpu.icache.total_refs 8113553 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1074878 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.548348 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56079311000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.322538 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996724 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996724 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8113553 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8113553 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8113553 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8113553 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8113553 # number of overall hits +system.cpu.icache.overall_hits::total 8113553 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1144218 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1144218 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1144218 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1144218 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1144218 # number of overall misses +system.cpu.icache.overall_misses::total 1144218 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15461286493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15461286493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15461286493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15461286493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15461286493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15461286493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9257771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9257771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9257771 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9257771 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9257771 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13512.535630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13512.535630 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7080 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 251 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.519084 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.207171 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68044 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68044 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68044 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68044 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68044 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68044 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071350 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1071350 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1071350 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1071350 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1071350 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1071350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12542463990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12542463990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12542463990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12542463990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12542463990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12542463990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115586 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115586 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12721673493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12721673493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12721673493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12721673493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116345 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116345 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116345 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11811.107938 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11811.107938 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11811.107938 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11811.107938 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11811.107938 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11811.107938 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9707 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.043772 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 27693 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9719 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.849367 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5100157918000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.043772 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377736 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.377736 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27843 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 27843 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 10271 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.965877 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 29367 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 10284 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.855601 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5103910768500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.965877 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.435367 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.435367 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 29379 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 29379 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27846 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 27846 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27846 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 27846 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10592 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10592 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10592 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10592 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10592 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10592 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116124000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116124000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116124000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 116124000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116124000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 116124000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38435 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38435 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 29382 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 29382 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29382 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 29382 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11163 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 11163 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11163 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 11163 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11163 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 11163 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 123160000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 123160000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 123160000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 123160000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 123160000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 123160000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40542 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 40542 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38438 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 38438 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38438 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 38438 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275582 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275582 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275561 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.275561 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275561 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.275561 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10963.368580 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10963.368580 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10963.368580 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10963.368580 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40545 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 40545 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40545 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 40545 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275344 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275344 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275324 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.275324 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275324 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.275324 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11032.876467 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11032.876467 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11032.876467 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11032.876467 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,78 +719,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1540 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1540 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10592 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10592 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10592 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10592 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10592 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10592 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94940000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94940000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94940000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94940000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94940000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94940000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275582 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275582 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275561 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275561 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8963.368580 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1731 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1731 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11163 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11163 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11163 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 11163 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11163 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 11163 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 100834000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 100834000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 100834000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 100834000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 100834000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 100834000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275344 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275344 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275324 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275324 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9032.876467 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 107637 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 11.991971 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 139374 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 107653 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.294660 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.991971 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749498 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.749498 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139374 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 139374 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139374 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 139374 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139374 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 139374 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108671 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 108671 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108671 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 108671 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108671 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 108671 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1362724500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1362724500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1362724500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1362724500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1362724500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1362724500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248045 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 248045 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248045 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 248045 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248045 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 248045 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.438110 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.438110 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.438110 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.438110 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.438110 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.438110 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12539.909451 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12539.909451 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12539.909451 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12539.909451 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109401 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.751867 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 137796 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109417 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.259366 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100515626500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.751867 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.859492 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.859492 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137796 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 137796 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137796 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 137796 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137796 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 137796 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110443 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110443 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110443 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110443 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110443 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110443 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1382584000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1382584000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1382584000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1382584000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1382584000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1382584000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248239 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 248239 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248239 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 248239 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248239 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 248239 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.444906 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.444906 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.444906 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.444906 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.444906 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.444906 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12518.529920 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12518.529920 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12518.529920 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12518.529920 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,146 +799,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 32720 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 32720 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108671 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108671 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108671 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 108671 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108671 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 108671 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1145382500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1145382500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1145382500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.438110 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.438110 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.438110 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10539.909451 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 36585 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 36585 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110443 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110443 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110443 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110443 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110443 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110443 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1161698000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1161698000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1161698000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.444906 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.444906 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.444906 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10518.529920 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10518.529920 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10518.529920 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673658 # number of replacements -system.cpu.dcache.tagsinuse 511.992942 # Cycle average of tags in use -system.cpu.dcache.total_refs 19220297 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1674170 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.480493 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 32836000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.992942 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11126575 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11126575 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8088656 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8088656 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19215231 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19215231 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19215231 # number of overall hits -system.cpu.dcache.overall_hits::total 19215231 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2269640 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2269640 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169424 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037961 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037961 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118731 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118731 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118731 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118731 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13978.693758 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13978.693758 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30776.793435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30776.793435 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16049.720081 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16049.720081 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 366322 # number of cycles access was blocked +system.cpu.dcache.replacements 1672817 # number of replacements +system.cpu.dcache.tagsinuse 511.996932 # Cycle average of tags in use +system.cpu.dcache.total_refs 19210877 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1673329 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.480634 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.996932 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11119324 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11119324 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8086692 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8086692 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19206016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19206016 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19206016 # number of overall hits +system.cpu.dcache.overall_hits::total 19206016 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2269518 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2269518 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318969 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318969 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2588487 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2588487 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2588487 # number of overall misses +system.cpu.dcache.overall_misses::total 2588487 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32394569000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32394569000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9644667991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9644667991 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42039236991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42039236991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42039236991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42039236991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13388842 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13388842 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8405661 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8405661 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21794503 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21794503 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21794503 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21794503 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169508 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169508 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037947 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037947 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14273.766060 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14273.766060 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30237.007330 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30237.007330 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16240.853051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16240.853051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16240.853051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16240.853051 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 395046 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42954 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42533 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.528240 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.287988 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1573837 # number of writebacks -system.cpu.dcache.writebacks::total 1573837 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 884183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26057 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 26057 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 910240 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 910240 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 910240 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 910240 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1385457 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26073299491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26073299491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26073299491 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26073299491 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296962500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296962500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470375500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470375500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767338000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767338000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103422 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103422 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076984 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076984 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12331.629202 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12331.629202 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30664.847675 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30664.847675 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1572293 # number of writebacks +system.cpu.dcache.writebacks::total 1572293 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885972 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 885972 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24759 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 24759 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 910731 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 910731 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 910731 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 910731 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1383546 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1383546 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294210 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 294210 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1677756 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1677756 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1677756 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1677756 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17475799000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17475799000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8804968491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8804968491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26280767491 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26280767491 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26280767491 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26280767491 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296545000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296545000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470181000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470181000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766726000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766726000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103336 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103336 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035001 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035001 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076981 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076981 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076981 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076981 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12631.165859 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12631.165859 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29927.495636 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29927.495636 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15664.236928 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15664.236928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15664.236928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15664.236928 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -788,141 +946,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113860 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91489954000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91489954000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000827 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015730 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026977 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916178 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916178 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015730 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102360 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.065824 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000447 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015730 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102360 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.065824 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47107.105814 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51997.122677 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50491.707979 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.673804 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.673804 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38288.169829 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38288.169829 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47107.105814 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41274.047687 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41806.458269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47107.105814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41274.047687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41806.458269 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index ccb436843..c24f73d04 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,77 +1,235 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.205007 # Number of seconds simulated -sim_ticks 5205006924000 # Number of ticks simulated -final_tick 5205006924000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.205006 # Number of seconds simulated +sim_ticks 5205006494000 # Number of ticks simulated +final_tick 5205006494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143770 # Simulator instruction rate (inst/s) -host_op_rate 275863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6917470976 # Simulator tick rate (ticks/s) -host_mem_usage 505276 # Number of bytes of host memory used -host_seconds 752.44 # Real time elapsed on the host -sim_insts 108178578 # Number of instructions simulated -sim_ops 207571464 # Number of ops (including micro ops) simulated +host_inst_rate 176611 # Simulator instruction rate (inst/s) +host_op_rate 338881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8497542071 # Simulator tick rate (ticks/s) +host_mem_usage 459536 # Number of bytes of host memory used +host_seconds 612.53 # Real time elapsed on the host +sim_insts 108179755 # Number of instructions simulated +sim_ops 207574747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 173936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 174032 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 86216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 870514880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 69689841 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 49504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 870539632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 69693671 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 20312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 157070368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 27207776 # Number of bytes read from this memory -system.physmem.bytes_read::total 1124848049 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 870514880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 157070368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1027585248 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 157047256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 27202450 # Number of bytes read from this memory +system.physmem.bytes_read::total 1124848257 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 870539632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 157047256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1027586888 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 48549302 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 21364054 # Number of bytes written to this memory -system.physmem.bytes_written::total 72904476 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 48549554 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 21360352 # Number of bytes written to this memory +system.physmem.bytes_written::total 72901026 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 818 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 21742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 21754 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 10777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 108814360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 12175547 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 6188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 108817454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 12176562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 6184 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2539 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 19633796 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4005942 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144671709 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 19630907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4005282 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144672277 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 7160367 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2936343 # Number of write requests responded to by this memory -system.physmem.num_writes::total 10143448 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 7160394 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2935820 # Number of write requests responded to by this memory +system.physmem.num_writes::total 10142952 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 6766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 33417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 33436 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 16564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 167245672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13389001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 9511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 167250441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13389738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 9505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 30176784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5227231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 216108848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 167245672 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 30176784 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197422456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 30172346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5226209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 216108906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 167250441 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 30172346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197422787 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 574659 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 9327423 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 4104520 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 14006605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 9327472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 4103809 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 14005943 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 581425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 33417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 33436 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 16567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 167245672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 22716424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 9511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 167250441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 22717210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 9505 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 30176784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 9331751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 230115453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 30172346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 9330018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 230114849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 818 # Total number of read requests seen +system.physmem.writeReqs 46736 # Total number of write requests seen +system.physmem.cpureqs 47248 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 52352 # Total number of bytes read from memory +system.physmem.bytesWritten 2991104 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 35216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 322 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 3080 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 3056 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2944 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2640 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3024 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 2800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 3152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 3016 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 63209426000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 306 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 512 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 46736 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 40984666 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 52278666 # Sum of mem lat for all requests +system.physmem.totBusLat 3272000 # Total cycles spent in databus access +system.physmem.totBankLat 8022000 # Total cycles spent in bank access +system.physmem.avgQLat 50103.50 # Average queueing delay per request +system.physmem.avgBankLat 9806.85 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 63910.35 # Average memory access latency +system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.57 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.15 # Average write queue length over time +system.physmem.readRowHits 695 # Number of row buffer hits during reads +system.physmem.writeRowHits 45891 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.19 # Row buffer hit rate for writes +system.physmem.avgGap 1329213.65 # Average gap between requests system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -114,52 +272,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10410013848 # number of cpu cycles simulated +system.cpu0.numCycles 10410012988 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 93129090 # Number of instructions committed -system.cpu0.committedOps 179514856 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 169447650 # Number of integer alu accesses +system.cpu0.committedInsts 93132190 # Number of instructions committed +system.cpu0.committedOps 179521943 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 169453705 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16553172 # number of instructions that are conditional controls -system.cpu0.num_int_insts 169447650 # number of integer instructions +system.cpu0.num_conditional_control_insts 16554212 # number of instructions that are conditional controls +system.cpu0.num_int_insts 169453705 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 418656867 # number of times the integer registers were read -system.cpu0.num_int_register_writes 211655789 # number of times the integer registers were written +system.cpu0.num_int_register_reads 418670977 # number of times the integer registers were read +system.cpu0.num_int_register_writes 211662649 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 20197632 # number of memory refs -system.cpu0.num_load_insts 13022518 # Number of load instructions -system.cpu0.num_store_insts 7175114 # Number of store instructions -system.cpu0.num_idle_cycles 9667682114.054142 # Number of idle cycles -system.cpu0.num_busy_cycles 742331733.945857 # Number of busy cycles -system.cpu0.not_idle_fraction 0.071309 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.928691 # Percentage of idle cycles +system.cpu0.num_mem_refs 20198672 # number of memory refs +system.cpu0.num_load_insts 13023532 # Number of load instructions +system.cpu0.num_store_insts 7175140 # Number of store instructions +system.cpu0.num_idle_cycles 9667664508.054142 # Number of idle cycles +system.cpu0.num_busy_cycles 742348479.945857 # Number of busy cycles +system.cpu0.not_idle_fraction 0.071311 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.928689 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10407072224 # number of cpu cycles simulated +system.cpu1.numCycles 10407071288 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15049488 # Number of instructions committed -system.cpu1.committedOps 28056608 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 27537877 # Number of integer alu accesses +system.cpu1.committedInsts 15047565 # Number of instructions committed +system.cpu1.committedOps 28052804 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 27533880 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1864532 # number of instructions that are conditional controls -system.cpu1.num_int_insts 27537877 # number of integer instructions +system.cpu1.num_conditional_control_insts 1864518 # number of instructions that are conditional controls +system.cpu1.num_int_insts 27533880 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 71380294 # number of times the integer registers were read -system.cpu1.num_int_register_writes 31003707 # number of times the integer registers were written +system.cpu1.num_int_register_reads 71369326 # number of times the integer registers were read +system.cpu1.num_int_register_writes 30999444 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 6975131 # number of memory refs -system.cpu1.num_load_insts 4014934 # Number of load instructions -system.cpu1.num_store_insts 2960197 # Number of store instructions -system.cpu1.num_idle_cycles 10279839396.425842 # Number of idle cycles -system.cpu1.num_busy_cycles 127232827.574158 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012226 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987774 # Percentage of idle cycles +system.cpu1.num_mem_refs 6973948 # number of memory refs +system.cpu1.num_load_insts 4014274 # Number of load instructions +system.cpu1.num_store_insts 2959674 # Number of store instructions +system.cpu1.num_idle_cycles 10279858503.692720 # Number of idle cycles +system.cpu1.num_busy_cycles 127212784.307279 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012224 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987776 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |